13. What is IDDQ Testing? Why is it done?

Ans: IDDQ Testing can detect certain types of circuit faults in CMOS circuits th
at are difficult or impossible to detect by other methods.
IDDQ testing, when used with standard functional or scan testing, provides an ad
ditional measure of quality assurance against defective devices.
IDDQ testing refers to the integrated circuit (IC) testing method based upon mea
surement of steady state power-supply current. Iddq stands for quiescent Idd, or
quiescent power-supply current. Majority of IC s are manufactured using complement
ary metal oxide semiconductor (CMOS) technology. In steady state, when all switching
transients are settled-down, a CMOS circuit dissipates almost zero static curre
nt. The leakage current
in a defect-free CMOS circuit is negligible (on the order of few nano amperes).
However, in case of a defect such as gate-oxide short or short between two metal
lines, a conduction
path from power-supply (Vdd) to ground (Gnd) is formed and subsequently the circ
uit dissipates significantly high current. This faulty current is a few orders o
f magnitude
higher than the fault-free leakage current. Thus, by monitoring the power-supply
current, one may distinguish between faulty and fault-free circuits.
Why do IDDQ Testing?
For functional testing, a tester applies a sequence of input data and detects th
e results in the sequence of output data. Then, the output sequence is compared
against the expected behavior of the device. An advantage of functional testing
is that it exercises the device as it would actually be used in the target appli
cation. However, this type of testing has only a limited ability to tests the in
tegrity of a device's internal nodes.
with functional testing only, an internal defect could slide by undetected.
The methodology for scan testing is all the sequential elements of the device ar
e connected into chains and used as primary inputs and primary outputs for testi
ng purposes. Using automatic test-pattern generation (ATPG) techniques, you have
the capability to test a much larger number of internal faults than with functi
onal testing alone. The goal of ATPG is to set all nodes of the circuit to both
0 and 1, and to propagate any defects to nodes where they can be detected by tes
t equipment.
Using both functional and scan testing you greatly increases your odds at findin
g an internal defect, but what if the defect is not controllable or can't be obs
erved? That is where IDDQ testing can help.
14. If one needs to do synthesis/STA with scan replaced FF (not stitched) and ne
ed do generate timing and other reports. What should be values of SE, SI and SO
pins since design is not stitched?
Ans: We need not constrain the SE, SI and SO pins for synthesis / STA of a scan
replaced but not stitched design. But we will not be able to do any test relate
d STA.
15. Can you briefly describe the points to be considered, while re-ordering the
scan chain in Physical Design?

Ans: Scan chain reordering needs to respect 3 important Logical constraints.

1. Clock domain timing constraints
2. User specified scan segment positions
3. Minimizing clock domain traversals
each active edge of each clock is considered to be in a separate clock domain. B
oth edges of a clock and clocks with different timings may be used to control ed
ge-triggered scan flip flops of a scan chain.
In order to construct functional scan chains, two consecutive scan flip flops A
and B (A serially driving B)
1) must be clocked at the same time or
2) B must be clocked before A.
In the first case, we say that A and B have compatible clock domains.
In the second case, we say that A and B have incompatible clock domains.