IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE

Differential Ring Oscillators with Multipath Delay Stages

S. S. Mohan1, W. S. Chan2, D. M. Colleran1, S. F. Greenwood3,
J. E. Gamble4 and I. G. Kouznetsov5
1

Sabio Labs, Palo Alto, CA, 2Marvell Semiconductor, Sunnyvale, CA, 3ATI Technologies, Santa Clara, CA,
4
Synopsys, Hillsboro, OR, 5Cypress Semiconductor, San Jose, CA

Abstract
This work presents a differential ring oscillator architecture
along with a design methodology that yields a compact, wellmatched layout. A process independent attribute called the
effective number of stages quantifies performance trade-offs
in speed, jitter and power consumption. Design guidelines
eliminate undesired modes of operation and guarantee robust
differential oscillation. Theoretical predictions for four, five
and six stage oscillators agree with measurements of CMOS
90nm and 0.13m implementations operating from 25 MHz
to 6 GHz.
Keywords: Differential Ring Oscillator, CMOS VCO, Jitter
and Multiphase.
Introduction
CMOS ring oscillators are ubiquitous in clocking and datarecovery applications [1], [2]. While single-ended rings are
well understood, easy to size and convenient to port over
processes, they are limited to an odd number of delay stages
(N), and therefore cannot provide complementary outputs. As
a result, differential ring oscillators are preferred for
multiphase clocking applications [1].
Differential operation can be realized by using delay stages
with source-coupled pairs biased by tail current sources.
However, supply rejection is compromised in this approach
because of the finite output impedance of the tail current

sources as well as oscillation at the tail node [2]. Differential

oscillation can be realized without tail current sources for odd
N by coupling two single-ended ring oscillators with dual
input inverters [3]. Differential oscillators without tail current
sources for even N are not common. While a circuit that
combines cross-coupling with the selective feed-forward of
the (slower) PMOS path has been proposed [4], this
implementation is difficult to model and cumbersome to port
over processes while ensuring robust operation.
This work describes a differential ring oscillator
architecture that is suitable for both even and odd N. The
companion design methodology permits systematic design
trade-offs while ensuring robust operation and convenient
porting over processes.
Architecture
Fig 1 illustrates a generalized N stage implementation of
the architecture. Each stage consists of a multiple-input delay
cell with m inverter pairs where m N. Each path within the
delay cell is characterized by its path number, i, and its
normalized drive strength, ki. The path number denotes the
number of delay stages between the input and output of the
path. Thus, the cross-coupled, regular and feed-forward paths
are labeled 0, 1 and 2, with corresponding drive strengths of
k0, k1 and k2, respectively. If all delay stages are identical in
terms of composition and loading capacitance, and if all
inverters in the oscillator's delay stage have the same channel

Fig. 1. Architecture: (a) CMOS inverter. (b) Delay stage with m inverter pairs. (c) N stage differential ring oscillator.

0-7803-9023-7/05/$20.00 2005 IEEE.

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length, finger widths, and PMOS-to-NMOS width ratio, then

ki is the ratio of the number of gate fingers allocated to the
path, nfi, to the total number of gate fingers in a cell:
nf
k i = i = (m 1i) .
(1)

nf

dominant oscillation mode is the one with the smallest

positive Ap. Thus, the design goal is to constrain ki such that
A1 is the smallest among all positive Ap. This condition is
necessary but not sufficient as A1 must be also smaller than
the lowest available gain.

i =0

This approach enables all of the oscillator devices to be

merged into two diffusion areas, one for the NMOS
transistors and the other for the PMOS ones. The result is a
compact, well-matched layout which facilitates the generation
of 2N uniformly spaced output phases from an N stage
differential oscillator.
The design methodology, valid for any value of m such that
m N, permits the systematic trade-off of speed, jitter and
power consumption. Implementations with k0, k1 and k2
(m=3) exhibit enhanced performance flexibility compared to
prior art. Since no tail-current pairs are needed nor desired,
the oscillator can be combined with a voltage-to-current (V2I)
converter, to realize a voltage controlled oscillator (VCO)
whose tuning range and power supply rejection is comparable
to one that uses a conventional single-ended ring [5], [6].
Oscillation Conditions
This section provides design guidelines for ensuring robust
oscillation. As expected, the even and odd numbered paths in
the multiple-input delay stage play different roles. For
convenience, the sums of the normalized strengths of the even
numbered paths and the odd numbered paths are denoted as
ksum_even((=k0+ k2+ k4+), and ksum_odd(= k1+ k3+ k5+),
respectively. Note that ksum_even+ ksum_odd=1.
Consider an N stage differential oscillator with ksum_even=0.
In the case of odd N, this corresponds to two independent
single-ended ring oscillators. Since the two rings are not
linked, their phase relationship is not fixed. The addition of
ksum_even couples these two rings with a unique phase
relationship. The designers goal is to choose ksum_even so as to
favor differential oscillation over common-mode oscillation.
In the case of even N, ksum_even also plays the pivotal role of
eliminating DC states.
The feed-forward (k2, k3, ) paths must be sized prudently
to avoid undesired modes of operation. Conditions for stable
differential oscillation are developed based on the minimum
required gain and the lowest available gain.

B. Lowest Available Gain

Implementations with even N exhibit a zero current DC
state with zero gain. The judicious use of ksum_even increases
the lowest available gain for the desired differential mode by
generating negative resistance and by increasing the rings
current consumption. Oscillation start-up can be guaranteed
over all process and supply variations by constraining ksum_even
to be between 0.37 and 0.63. This condition is obtained from
a worst case analysis at both the short-channel and longchannel approximation extremes. In most CMOS sub-micron
processes, this requirement can be relaxed for practical
voltage tuning ranges to 0.25 < ksum_even < 0.75. Thus, the
lowest available gain requirement is usually satisfied in the
process of meeting the minimum required gain:
(3)
(0 < A1< Ap ) or ( Ap < 0) for 1<p N.
Performance Measures
A. Effective Number of Stages (Neff)
The effective number of stages, Neff, is both a convenient
and compelling measure of the oscillator's performance:
N
N eff = i = (m 1) .
(4)

k i
i

i =0

This relation is derived from large signal delay considerations

and facilitates the comparison of oscillators with the same
loading, device sizes and control voltage. The attribute Neff
can be understood as the number of stages of a conventional
(hypothetical) single-ended ring oscillator that exhibits the

A. Minimum Required Gain

Oscillators with multiple delay paths may exhibit more
than one mode. An analysis based on the Barkenhausen
criteria for oscillation yields the minimum required gain, Ap,
for each mode (p) :
1
, for 1 p N .
(2)
A p = i = (m 1)
i

( k i ) cos p + 1

i=0
N
The mode numbered p=1 corresponds to the desired
differential oscillation with 2N distinct output phases. All the
other modes exhibit N or fewer distinct phases. A negative Ap
indicates a mode that cannot be sustained. The mode
numbered p=N refers to the zero frequency (DC) state. The

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Fig. 2 Validity of Neff: Comparison of simulated tuning curves of 0.13m

differential ring oscillators with conventional single-ended oscillators.

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same speed as the differential ring oscillator. As expected,

Neff approaches N as k1 approaches 1. Furthermore Neff
quantitatively captures the increase in speed as the amount of
cross-coupling (k0) is decreased and feed-forward (k2, k3, )
is increased. The validity of Neff is illustrated in Fig. 2 using
simulations that benchmark the tuning curves of a variety of
differential oscillators (with equal total drive strengths and
capacitance loading per node) with reference to their singleended counterparts.
B. Jitter
The jitter performance of this architecture can be inferred
from an impulse sensitivity function (ISF) based derivation.
The single-ended ring oscillator treatment from reference [7]
is expanded to incorporate oscillators with multiple-input
differential delay stages by noting that the ratio of the delay
per stage and the rise/fall times is proportional to the ratio
between the Neff and N. The standard deviation of the jitter is
given in terms of the notation in [7] by:
2
N eff
2 2 i n
T , where 0.75
. (5)
3
N
Nq max 0 3 f
The 1/f3 corner of the phase noise is minimized by setting the
ratio of the inverters PMOS to NMOS widths to achieve
equal rise and fall times in the nominal process corner [7].

T =

Design Implications
The design methodology is independent of process
parameters and control voltage. The expressions in (1)-(4)
are functions of only the normalized drive strengths, ki, and
the number of stages, N, thereby permitting the design of
robust, easy to port oscillators. This design framework also
quantifies the limitations of previous work that relied on dual
input inverters to couple oscillators [1],[3]. For example, the
fastest (minimum Neff) theoretical implementations using only
k0 and k1 are Neff=4.6 for N=4 (k0=0.13, k1=0.87) and Neff=6.4
for N=6 (k0=0.07, k1=0.93). Interestingly, the fastest possible
two stage realization (N=2, k0=1/3, k1=2/3, Neff=3) has the
same Ne ff as that of a single-ended three stage oscillator. On
the other hand, even N implementations based only on k1 and

k2 are plagued by insufficient differential mode gain at small

k2 and undesired modes of oscillation at large k2.
The combined use of k0, k1 and k2 offers significant
advantages. While k2 increases speed at the expense of
multiple oscillation modes, k0 suppresses undesired modes at
the expense of reduced speeds. Together, k0 and k2 eliminate
DC states, increase the available differential mode gain and
enable the desired speed and jitter to be achieved while
providing immunity from undesired modes. In this case, the
fastest theoretical limits of Neff for N=4, 5 and 6 are 2.84, 2.98
and 3.00, respectively. Practical limits of Neff are somewhat
larger due to the need for some margin and because all ki must
be rational fractions (determined by the total number of
fingers). For example, an N=4 implementation with Neff =3.2
can be realized using k0=2/12, k1=5/12 and, k2=5/12.
While other paths (such as k3) are not needed for N=4, 5
and 6, they may prove useful for realizing small Neff for larger
N. Equations (1)-(5) are valid for all such cases.
Measurements
Table 1 tabulates the details of eight oscillators fabricated
using 0.13m and 90nm CMOS processes. In each design, a
total of twelve transistor fingers per oscillating node is
partitioned among the cross-coupling, input and feed-forward
paths using (1)-(4) to yield a desired Neff while ensuring
differential oscillation. As expected, the lowest available
gain requirement is automatically met once (3) is satisfied
with sufficient margin to ensure that A1 is significantly lower
than all other positive Ap.
The normalized drives strengths of the two 0.13m four
stage oscillators are the same as those of the two 90nm four
stage oscillators, permitting comparison of the methodology
across processes.
The ratio between the oscillation
frequencies of osc1 and osc2 is within 2% of that between
osc3 and osc4 in accordance with theoretical predictions. The
total drive strengths of the five and six stage 90nm oscillators
(osc5-osc8) are kept equal while Neff is varied from four to
seven. The voltage-to-frequency curves and the current-tofrequency curves of the oscillators are plotted in Fig. 3 and 4,
respectively. Jitter measurements are presented in Fig. 5.
The normalized phase mismatch errors are shown in Fig. 6.

TABLE I
FABRICATED OSCILLATORS
Osc ID

CMOS
Process

1
2
3
4
5
6
7
8

130nm
130nm
90nm
90nm
90nm
90nm
90nm
90nm

Num
Stages
N
4
4
4
4
5
6
6
6

Transistor Fingers
total
path allocation
0
1
2
12
2
5
5
12
2
8
2
12
2
5
5
12
2
8
2
14
2
10
2
14
0
7
7
14
2
10
2
14
2
12
0

Neff

3.2
4.0
3.2
4.0
5.0
4.0
6.0
7.0

desired
p=1
2.17
1.57
2.17
1.57
1.31
1.46
1.20
1.13

Gain for Modes

undesired
DC
p
Ap
p=N
-6.00
2
4.00
3.00
2
inf
-6.00
2
4.00
3.00
2
inf
-2.33
4
2.56
inf
4
2.00
2.33
4
3.50
1.40
4
3.50

Area
um^2
54x46
54x46
40x26
40x26
58x28
69x31
69x31
69x31

Sample Measurements
freq.
volt.
cur.
GHz
V
mA
2.80
1.2
4.79
2.11
1.2
3.92
5.95
1.0
5.68
4.55
1.0
5.17
3.62
1.0
5.84
4.93
1.0
8.03
3.10
1.0
6.27
2.73
1.0
5.15

Notes:
1.The drawn channel lengths of all devices are set to 160nm for osc1-osc2 and 120nm for osc3-osc8.
2.Layout area includes 10um wide control voltage and ground planes (designed to comply with electromigration and IR drop requirements) , as
well as matched interconnects, dummy poly fingers and poly fill to ensure good phase matching.
3.Oscillators with a given number of stages in a given process technology have the same area (example: osc6-osc8) as the different instances are
configured by via and contact connections.
4.The measured oscillators are loaded by the input capacitance of the buffers which drive the phase selectors and IO circuits in the test setup. The
effective fan-out is approximately 2.5 for osc1-osc2, 2.2 for osc3-osc4 and 2.0 for osc5-osc8.

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Fig. 5 Measured jitter for 90nm oscillators.

Fig. 3 Measured voltage-to-frequency tuning curves for 90nm oscillators.

Fig. 6 Measured phase mismatch (normalized by the oscillation period).

Fig. 4 Measured current-to-frequency tuning curves for 90nm oscillators.

Conclusion
The differential ring oscillator architecture and design
methodology described in this work permit the systematic
tradeoff of speed, jitter and power consumption. The design
equations are process independent, thereby ensuring robust
operation.
Performance is quantified in terms of the
normalized drive strengths, ki, and the effective number of
stages, Neff. Theoretical predictions agree with measurements
of 90nm and 0.13m CMOS implementations operating from
25MHz to 6GHz over a wide range of control voltages and
currents. While primarily intended for CMOS inverter based
implementations, this methodology provides a general design
framework for multiphase oscillators and is valid for many
oscillator families.
Acknowledgment
The authors thank Prof. Ali Hajimiri for helpful
discussions, Cathy Chang and Becky Sun for layout, and
Xiling Shen and Matthew Parker for board design.
Note: The authors completed this work while at Barcelona
Design, CA.

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