Beruflich Dokumente
Kultur Dokumente
Module 1
1
Jun15
With the help of neat cross sections and appropriate masks, give the
process flow of N-well CMOS technology.
Jun15
Dec15
Dec15
Dec15
Dec15
Dec13
Module 2
1
Jun15
Jun15
Draw static CMOS NAND and NOR gates. Size all transistors in
NAND and NOR gate to provide worst case equal rise and fall delay
for both gates. Assume mobility of electron is two times higher than
that of holes. Magnitude of threshold voltage for all transistors is same.
Jun15
Jun15
Jun15
Dec15
Dec15
Draw 2 input CMOS NOR gate and using equivalent inverter approach
and derive expression for VIL,VIH,VOL and VOH.
Dec15
Dec13
10
Dec13
11
Dec13
Module 3:
1 Implement master slave D flip flop using C2MOS logic style
Jun15
Jun15
Jun15
Dec15
5 Design clocked D-FF and implement using standard CMOS logic style.
Dec15
Dec15
Dec15
Dec12
Dec12
Module 5
1 Explain 4*4 bit array multiplier with the help of necessary hardware for
the generation and addition of partial product.
Jun15
Dec15
Jun15
Dec15
Jun15
Dec12
4 Show the implementation of four bit carry look ahead adder along with
all equations.
5 Draw and explain manchester carry out circuit using carry kill bit. Also
draw k-input dynamic manchester carry chain.
Module 4
1 Implement NOR based 2:4 decoder.
Jun15
Jun15
Jun15
Dec15
Dec15
Dec15
7 Draw schematic for 6T SRAM cell and explain its stability criteria
Module 6
1 With the help of suitable diagrams explain how clock is generated and
stabilized in VLSI chip.
Jun15
Jun15
Jun15
Jun15
Dec15
Dec15
7 Draw and explain clock generation and stabilization network. And explain
how this clock is distributed in an integrated circuit.
Dec12