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Resistors
Capacitors
Bipolar transistors
Power components
N Diffusion resistor
Polysilicon resistor
Polysilicon capacitor
P-cells
NMOS transistor
Polysilicon capacitor
Lithography
Lithography
NA = n sin
Rayleighs equations:
resolution = k1
NA
NA2
Lithography
Example: which is the critical dimension that can be achieved with
=248 nm?
Reasonable NA for air is 0,8
Guess k1=0,4
resolution = 0, 4
248nm
= 124nm
0,8
resolution = 0,3
193nm
= 72nm
0,8
Lithography
436 nm: used down to 3 m technologies
365 nm: used down to 0,6 m technologies
248 nm: used down to 130 nm technologies
193 nm in air (dry lithography)
Lithography
436 nm: used down to 3 m technologies
365 nm: used down to 0,6 m technologies
248 nm: used down to 130 nm technologies
193 nm in air (dry lithography)
157 nm: needs special lens materials
Lithography
436 nm: used down to 3 m technologies
365 nm: used down to 0,6 m technologies
248 nm: used down to 130 nm technologies
193 nm in air (dry lithography)
157 nm: needs special lens materials
EUV (=13 nm). New approach: mirrors, no
lenses
Optimistic forecast: ready for
22 nm technology node
(2011)
Lithography
436 nm: used down to 3 m technologies
365 nm: used down to 0,6 m technologies
248 nm: used down to 130 nm technologies
193 nm in air (dry lithography)
193 nm in liquid (immersion lithography)
Lithography
193 nm in air (dry lithography)
193 nm in liquid (immersion lithography)
Heterogeneous mask
Lithography
ABOVE WAVELENGTH
SUB WAVELENGTH
3m
Silicon feature size
0.6m
1
436nm
365nm
Lithography Wavelength
0.25m
193nm
target layout
0.13m
0.1
0.05m
1980
1990
2000
2008
result
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Fabrication process
limitations
Lateral diffusion
Etching under protection
Boundary dependent
etching
Three-dimensional effects
Chemical Mechanical
Polishing (CMP)
Surface topography
Fabrication process
limitations
Narrowing after
annealing
Inherent grain variability
Proximity effects
Mask productions
Mask alignment
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2 ( ) A
=
+ S 2 D 2
2
WL
2 (VT ) =
AV2T
WL
+ SV2T D 2
L W
tox
2
interlayer
distance tox
2
C dielectric tox L W
+
+
=
+
C dielectric tox L W
oxide damage
impurities
temperature
stress
bias conditions
growth rate
grain size
width W
etching inaccuracy
mask alignment
from Franco Maloberti, Layout of Analog CMOS ICs
12
Relative inaccuracies of
physical parameters
Crystal orientation
variations
Components required to be
laid in a determined
orientation
Pressure gradients
Thermal gradients
W=L= 0.5 m d= 5m
W=L= 10 m d= 5m
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Parasitic coupling
Capacitive coupling
Couplings through the power supply
Couplings through the substrate
Parasitic resistances
Contacts
Interconnect
14
Some manufacturing
distortions can be
predicted and fixed
by introducing
modifications to the
mask
OPC: Optical
Proximity Correction
15
16
PO.W.1a
Minimum gate length of PMOS
PO.W-2a
Minimum gate length of NMOS
PO.W.3
Minimum POLY1 width for interconnect
PO.S.1
Minimum POLY1 spacing
PO.C.1
Minimum POLY 1 to DIFF spacing
PO.C.2
Minimum DIFF extension of GATE
PO.O.1
Minimum POLY1 extension of GATE
Optimized layouts:
Bad layout
Optimized layout
17
Optimized layouts:
Optimize efficiency of vias/contacts
Optimized layout
All transistors in the same
orientation
Optimized layouts:
Possible shortcircuit of nodes A and
B due to diffussion flaring and mask
misalingment
Possible shortcircuit due to
poly flaring
Possible shortcircuit due to
diffussion flaring
18
Dissipating
device
T1
Device 1
T2
Device 2
Dissipating
device
T1
Device 2
Device 1
T2
Interdigitated structures
Resistors R1 and R2
19
Interdigitated structures
Common centroid:
20
Coincidence
Symmetry
Dispersion
Compactness
21
Dummies
Reference cell
22
MOS Transistors
stacked structures
No big contacts!!!
Lower parasitic capacitances
Lower area
Analogue applications
Resistances
Bended structures
Dummy structures
45 degrees (avoid non
laminar current flow)
Contacts
Piezoresistive effect
23
CMP:
IR drops
Parasitic capacitance and couplings
Kelvin connections
24
Electromigration
Temperature
Current density
Conductor Shape
Material
25
Latch-up
Activation:
26
Rules:
I/O
transistors
surrounded
by pick-ups
and guard
rings
I/O and core
transistors
separated
by guard
rings
27
CMP
Chemical Mechanical
Polishing or Chemical
Mechanical Planarization
Removal any irregular
topography
Surface within the depth
of field of a
photolithography system.
(TSMC)
Design rules:
Minimum % coverage of
Metal layers
Polysilicon layers
Capacitor Layers
28
Pattern for M1
Pattern for M2
Pattern for M3
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30
Slots
Corners
Pads
dishing
31
ratio =
2[(L1 + W 1) Z1]
W 2 L2
Contact(Via) area
W 2 L2
32
Fab. 2
ESD
Electrostatic Discharge
Damage in dielectrics due to IC manipulation (mainly gate
oxide)
33
34
References
The art of Analog Layout, 2nd Edition. Alan Hastings. Ed. Prentice Hall
Nano-CMOS Circuit and Physical Design. B.P. Wong et al. WileyInterscience, IEEE Press
CMOS Circuit Design, Layout and Simulation. R. J. Baker. Wiley IEEE
Press
Layout of Analog and Mixed Analog-Digital Circuits. Franco Maloberti.
http://www.wikipedia.org/
35