Introduction

Flip-flops are synchronous bistable devices. The term synchronous means the output changes state
only when the clock input is triggered. That is, changes in the output occur in synchronization with
the clock.
Flip-flop is a kind of multivibrator. There are three types of multivibrators:

1.
2.
3.

Monostable multivibrator (also called one-shot) has only one stable state. It produces a single pulse in response to a
triggering input.
Bistable multivibrator exhibits two stable states. It is able to retain the two SET and RESET states indefinitely. It is
commonly used as a basic building block for counters, registers and memories.
Astable multivibrator has no stable state at all. It is used primarily as an oscillator to generate periodic pulse waveforms
for timing purposes.

In this tutorial, the three basic categories of bistable elements are emphasized: edge-triggered
flip-flop, pulse-triggered (master-slave) flip-flop, and data lock-out flip-flop. Their operating
characteristics and basic applications will also be discussed.
Edge-Triggered Flip-flops
An edge-triggered flip-flop changes states either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock
pulse on the control input. The three basic types are introduced here: S-R, J-K and D.

Click on one the following types of flip-flop. Then

its logic symbol will be shown on the left. Notice the
small triangle, called the dynamic input indicator, is
used to identify an edge-triggered flip-flop.
Positive edge-triggered (without bubble at Clock
input):
S-R, J-K, and D.
Negative edge-triggered (with bubble at Clock
input):
S-R, J-K, and D.

The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to the flip-flop's output only
on the triggering edge of the clock pulse.On the other hand, the direct set (SET) and clear (CLR) inputs are called asynchronous
inputs, as they are inputs that affect the state of the flip-flop independent of the clock. For the synchronous operations to work
properly, these asynchronous inputs must both be kept LOW.
Edge-triggered S-R flip-flop
The basic operation is illustrated below, along with the truth table for this type of flip-flop. The
operation and truth table for a negative edge-triggered flip-flop are the same as those for a
positive except that the falling edge of the clock pulse is the triggering edge.

As S = 1, R = 0. Flip-flop SETS on the rising clock edge.

Note that the S and R inputs can be changed at any time when the clock input is LOW or HIGH (except for a very short interval
around the triggering transition of the clock) without affecting the output. This is illustrated in the timing diagram below:

Edge-triggered J-K flip-flop

The J-K flip-flop works very similar to S-R flip-flop. The only difference is that this flip-flop has NO invalid state. The outputs
toggle (change to the opposite state) when both J and K inputs are HIGH. The truth table is shown below.

Edge-triggered D flip-flop
The operations of a D flip-flop is much more simpler. It has only one input addition to the clock. It is very useful when a single data
bit (0 or 1) is to be stored. If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores a 1. If there
is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a 0. The truth table below summarize the
operations of the positive edge-triggered D flip-flop. As before, the negative edge-triggered flip-flop works the same except that the
falling edge of the clock pulse is the triggering edge.

Pulse-Triggered (Master-Slave) Flip-flops

The term pulse-triggered means that data are entered into the flip-flop on the rising edge of the clock pulse, but the output does not
reflect the input state until the falling edge of the clock pulse. As this kind of flip-flops are sensitive to any change of the input levels
during the clock pulse is still HIGH, the inputs must be set up prior to the clock pulse's rising edge and must not be changed before
the falling edge. Otherwise, ambiguous results will happen.
The three basic types of pulse-triggered flip-flops are S-R, J-K and D. Their logic symbols are shown below. Notice that they do not
have the dynamic input indicator at the clock input but have postponed output symbols at the outputs.

The truth tables for the above pulse-triggered flip-flops are all the same as that for the edge-triggered flip-flops, except for the way
they are clocked. These flip-flops are also called Master-Slave flip-flops simply because their internal construction are divided into
two sections. The slave section is basically the same as the master section except that it is clocked on the inverted clock pulse and is
controlled by the outputs of the master section rather than by the external inputs. The logic diagram for a basic master-slave S-R
flip-flop is shown below.

Data Lock-Out Flip-flops

The data lock-out flip-flop is similar to the pulse-triggered (master-slave) flip-flop except it has a dynamic clock input. The dynamic
clock disables (locks out) the data inputs after the rising edge of the clock pulse. Therefore, the inputs do not need to be held
constant while the clock pulse is HIGH.
The master section of this flip-flop is like an edge-triggered device. The slave section becomes a pulse-triggered device to produce a
postponed output on the falling edge of the clock pulse.
The logic symbols of S-R, J-K and D data lock-out flip-flops are shown below. Notice they all have the dynamic input indicator as
well as the postponed output symbol.

Again, the above data lock-out flip-flops have same the truth tables as that for the edge-triggered flip-flops, except for the way they
are clocked.
Operating Characteristics
The operating characteristics mention here apply to all flip-flops regardless of the particular form of the circuit. They are typically
found in data sheets for integrated circuits. They specify the performance, operating requirements, and operating limitations of the
circuit.
Propagation Delay Time - is the interval of time required after an input signal has been applied for the resulting output change to
occur.
Set-Up Time - is the minimum interval required for the logic levels to be maintained constantly on
the inputs (J and K, or S and R, or D) prior to the triggering edge of the clock pulse in order for the
levels to be reliably clocked into the flip-flop.
Hold Time - is the minimum interval required for the logic levels to remain on the inputs after the
triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
Maximum Clock Frequency - is the highest rate that a flip-flop can be reliably triggered.
Power Dissipation - is the total power consumption of the device.
Pulse Widths - are the minimum pulse widths specified by the manufacturer for the Clock, SET and
CLEAR inputs.

Applications

Frequency Division
When a pulse waveform is applied to the clock input of a J-K flip-flop that is connected to toggle, the Q output is a square wave with
half the frequency of the clock input. If more flip-flops are connected together as shown in the figure below, further division of the
clock frequency can be achieved.

The Q output of the second flip-flop is one-fourth the frequency of the original clock input. This is because the frequency of the
clock is divided by 2 by the first flip-flop, then divided by 2 again by the second flip-flop. If more flip-flops are connected this way,
the frequency division would be 2 to the power n, where n is the number of flip-flops.

Parallel Data Storage

In digital systems, data are normally stored in groups of bits that represent numbers, codes, or other information. So, it is common
to take several bits of data on parallel lines and store them simultaneously in a group of flip-flops. This operation is illustrated in the
figure below.

Each of the three parallel data lines is connected to the D input of a flip-flop. Since all the clock inputs are
connected to the same clock, the data on the D inputs are stored simultaneously by the flip-flops on the
positive edge of the clock. Registers, a group of flip-flops use for data storage, will be explained in more
detail in a later chapter.

Counting

Another very important application of flip-flops is in digital counters, which are

covered in detail in the next chapter.
A counter that counts from 0 to 3 is illustrated in the timing
diagram on the right. The two-bit binary sequence repeats
every four clock pulses. When it counts to 3, it recycles back
to 0 to begin the sequence again.

Table of Contents
Introduction
Asynchronous (Ripple) Counters
Asynchronous Decade Counters
Asynchronous Up-Down Counters
Synchronous Counters
Synchronous Decade Counters
Synchronous Up-Down Counters
Applications

Introduction
Circuits for counting events are frequently used in computers and other digital systems. Since a
counter circuit must remember its past states, it has to possess memory. The chapter about flipflops introduced how flip-flops are connected to make a counter. The number of flip-flops used and
how they are connected determine the number of states and the sequence of the states that the
counter goes through in each complete cycle.
Counters can be classified into two broad categories according to the way they are clocked:

1.
2.

Asynchronous (Ripple) Counters - the first flip-flop is clocked by the external clock pulse,
and then each successive flip-flop is clocked by the Q or Q' output of the previous flip-flop.
Synchronous Counters - all memory elements are simultaneously triggered by the same
clock.

In this tutorial, pure binary, decade and up-down counters within the two categories will be
introduced.

Asynchronous
(Ripple) Counters

A two-bit asynchronous counter is shown on the left. The external clock is

connected to the clock input of the first flip-flop (FF0) only. So, FF0 changes state
at the falling edge of each clock pulse, but FF1 changes only when triggered by
the falling edge of the Q output of FF0. Because of the inherent propagation
delay through a flip-flop, the transition of the input clock pulse and a transition of
the Q output of FF0 can never occur at exactly the same time. Therefore, the flipflops cannot be triggered simultaneously, producing an asynchronous operation.

Note that for simplicity, the transitions of Q0, Q1 and CLK in the timing diagram above are shown as simultaneous even though this
is an asynchronous counter. Actually, there is some small delay between the CLK, Q0 and Q1 transitions.
Usually, all the CLEAR inputs are connected together, so that a single pulse can clear all the flipflops before counting starts. The clock pulse fed into FF0 is rippled through the other counters
after propagation delays, like a ripple on water, hence the name Ripple Counter.
The 2-bit ripple counter circuit above has four different states, each one corresponding to a count
value. Similarly, a counter with n flip-flops can have 2 to the power n states. The number of states
in a counter is known as its mod (modulo) number. Thus a 2-bit counter is a mod-4 counter.
A mod-n counter may also described as a divide-by-n counter. This is because the most significant
flip-flop (the furthest flip-flop from the original clock pulse) produces one pulse for every n pulses
at the clock input of the least significant flip-flop (the one triggers by the clock pulse). Thus, the
above counter is an example of a divide-by-4 counter.

The following is a three-bit asynchronous binary counter

and its timing diagram for one cycle. It
works exactly the same way as a two-bit asynchronous binary counter mentioned above, except it
has eight states due to the third flip-flop.

Asynchronous
Decade Counters
The binary counters previously introduced have two to the power n states. But counters with states less than this number are also
possible. They are designed to have the number of states in their sequences, which are called truncated sequences. These sequences
are achieved by forcing the counter to recycle before going through all of its normal states.
A common modulus for counters with truncated sequences is ten. A counter with ten states in its
sequence is called a decade counter. The circuit below is an implementation of a decade counter.

Once the counter counts to ten (1010), all the flip-flops are being cleared. Notice that only Q1 and Q3 are used to decode the count of
ten. This is called partial decoding, as none of the other states (zero to nine) have both Q1 and Q3 HIGH at the same time.
The sequence of the decade counter is shown in the table below:

Asynchronous
Up-Down Counters
In certain applications a counter must be able to count both up and down. The circuit below is a 3-bit up-down counter. It counts
up or down depending on the status of the control signals UP and DOWN. When the UP input is at 1 and the DOWN input is at 0,
the NAND network between FF0 and FF1 will gate the non-inverted output (Q) of FF0 into the clock input of FF1. Similarly, Q of
FF1 will be gated through the other NAND network into the clock input of FF2. Thus the counter will count up.

When the control input UP is at 0 and DOWN is at 1, the inverted outputs of FF0 and FF1 are gated
into the clock inputs of FF1 and FF2 respectively. If the flip-flops are initially reset to 0's, then the
counter will go through the following sequence as input pulses are applied.

Notice that an asynchronous up-down counter is slower than an up counter or a down counter because of
the additional propagation delay introduced by the NAND networks.

Synchronous Counters
In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all
the flip-flops change state simultaneously (in parallel). The circuit below is a 3-bit synchronous counter. The J and K inputs of FF0
are connected to HIGH. FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to
the output of an AND gate that is fed by the outputs of FF0 and FF1.

Pay attention to what happens after the 3rd clock pulse. Both outputs of FF0 and FF1 are HIGH.
The positive edge of the 4th clock pulse will cause FF2 to change its state due to the AND gate.

The count sequence for the 3-bit counter is shown on the right.
The most important advantage of synchronous counters is that there is no cumulative
time delay because all flip-flops are triggered in parallel. Thus, the maximum operating
frequency for this counter will be significantly higher than for the corresponding ripple
counter.

Synchronous
Decade Counters
Similar to an asynchronous decade counter, a synchronous decade counter counts from 0 to 9 and then recycles to 0 again. This is
done by forcing the 1010 state back to the 0000 state. This so called truncated sequence can be constructed by the following circuit.

From the sequence on the left, we notice that:

Q0 toggles on each clock pulse.

Q1 changes on the next clock pulse each time Q0=1 and Q3=0.
Q2 changes on the next clock pulse each time Q0=Q1=1.

Q3 changes on the next clock pulse each time Q0=1, Q1=1 and Q2=1 (count 7),
or when Q0=1 and Q3=1 (count 9).

These characteristics are implemented with the AND/OR logic connected as shown in the logic diagram above.

Synchronous
Up-Down Counters
A circuit of a 3-bit synchronous up-down counter and a table of its sequence are shown below. Similar to an asynchronous up-down
counter, a synchronous up-down counter also has an up-down control input. It is used to control the direction of the counter through
a certain sequence.

An examination of the sequence table shows:

for both the UP and DOWN sequences, Q0 toggles on each clock pulse.
for the UP sequence, Q1 changes state on the next clock pulse when Q0=1.
for the DOWN sequence, Q1 changes state on the next clock pulse when Q0=0.
for the UP sequence, Q2 changes state on the next clock pulse when Q0=Q1=1.

for the DOWN sequence, Q2 changes state on the next clock pulse when Q0=Q1=0.

These characteristics are implemented with the AND, OR & NOT logic connected as shown in the logic diagram above.

Applications

Digital counters are very useful in many applications. They can be easily found in digital clocks and parallel-to-serial data
conversion (multiplexing). In this section, we will use the later as an example on how counters are being used.
A group of bits appearing simultaneously on parallel lines is called parallel data. A group of bits
appearing on a single line in a time sequence is called serial data. Parallel-to-serial conversion is
normally accomplished by the use of a counter to provide a binary sequence for the data-select
inputs of a multiplexer, as illustrated in the circuit below.

The Q outputs of the modulus-8 counter are connected to the data-select inputs of
an eight-bit multiplexer. The first byte (eight-bit group) of parallel data is applied
to the multiplexer inputs. As the counter goes through a binary sequence from 0 to
7, each bit beginning with D0, is sequentially selected and passed through the
multiplexer to the output line.
After eight clock pulses, the data byte has been converted to a serial format and
sent out on the transmission line. Then, the counter recycles back to 0 and converts
another parallel byte sequentially again by the same process.

Table of Contents
Introduction
Serial In - Serial Out Shift Registers
Serial In - Parallel Out Shift Registers
Parallel In - Serial Out Shift Registers
Parallel In - Parallel Out Shift Registers
Bidirectional Shift Registers
Shift Register Counters
Applications

Introduction
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a
chain so that the output from one flip-flop becomes the input of the next flip-flop. Most of the registers possess no characteristic
internal sequence of states. All the flip-flops are driven by a common clock, and all are set or reset simultaneously.
In this chapter, the basic types of shift registers are studied, such as Serial In - Serial Out, Serial In
- Parallel Out, Parallel In - Serial Out, Parallel In - Parallel Out, and bidirectional shift registers. A
special form of counter - the shift register counter, is also introduced.
Serial In - Serial Out
Shift Registers
A basic four-bit shift register can be constructed using four D flip-flops, as shown below. The operation of the circuit is as follows.
The register is first cleared, forcing all four outputs to zero. The input data is then applied sequentially to the D input of the first

flip-flop on the left (FF0). During each clock pulse, one bit is transmitted from left to right. Assume a data word to be 1001. The
least significant bit of the data has to be shifted through the register from FF0 to FF3.

In order to get the data out of the register, they must be shifted out serially. This can be done
destructively or non-destructively. For destructive readout, the original data is lost and at the end
of the read cycle, all flip-flops are reset to zero.

To avoid the loss of data, an arrangement for a non-destructive reading can be done by adding two AND gates, an OR gate and an
inverter to the system. The construction of this circuit is shown below.

The data is loaded to the register when the control line is HIGH (ie WRITE). The data can be shifted out of the register when the
control line is LOW (ie READ). This is shown in the animation below.

Serial In - Parallel Out

Shift Registers
For this kind of register, data bits are entered serially in the same manner as discussed in the last section. The difference is the way
in which the data bits are taken out of the register. Once the data are stored, each bit appears on its respective output line, and all
bits are available simultaneously. A construction of a four-bit serial in - parallel out register is shown below.

In the animation below, we can see how the four-bit binary number 1001 is shifted to the Q outputs of the register.

Parallel In - Serial Out

Shift Registers
A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-flops and NAND gates for entering data (ie
writing) to the register.

D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least significant bit. To write data in,
the mode control line is taken to LOW and the data is clocked in. The data can be shifted when the mode control line is HIGH as
SHIFT is active high. The register performs right shift operation on the application of a clock pulse, as shown in the animation
below.

Parallel In - Parallel Out

Shift Registers
For parallel in - parallel out shift registers, all data bits appear on the parallel outputs immediately following the simultaneous entry
of the data bits. The following circuit is a four-bit parallel in - parallel out shift register constructed by D flip-flops.

The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all
the data at the D inputs appear at the corresponding Q outputs simultaneously.

Bidirectional Shift Registers

The registers discussed so far involved only right shift operations. Each right shift operation has the effect of successively dividing
the binary number by two. If the operation is reversed (left shift), this has the effect of multiplying the number by two. With
suitable gating arrangement a serial shift register can perform both operations.
A bidirectional, or reversible, shift register is one in which the data can be shift either left or right.
A four-bit bidirectional shift register using D flip-flops is shown below.

Here a set of NAND gates are configured as OR gates to select data inputs from the right or left
adjacent bistables, as selected by the LEFT/RIGHT control line.
The animation below performs right shift four times, then left shift four times. Notice the order of
the four output bits are not the same as the order of the original four input bits. They are actually
reversed!

Shift Register Counters

Two of the most common types of shift register counters are introduced here: the Ring counter and the Johnson counter. They are
basically shift registers with the serial outputs connected back to the serial inputs in order to produce particular sequences. These
registers are classified as counters because they exhibit a specified sequence of states.
Ring Counters
A ring counter is basically a circulating shift register in which the output of the most significant
stage is fed back to the input of the least significant stage. The following is a 4-bit ring counter
constructed from D flip-flops. The output of each stage is shifted into the next stage on the
positive edge of a clock pulse. If the CLEAR signal is high, all the flip-flops except the first one FF0
are reset to 0. FF0 is preset to 1 instead.

Since the count sequence has 4 distinct states, the counter can be considered as a
mod-4 counter. Only 4 of the maximum 16 states are used, making ring counters
very inefficient in terms of state usage. But the major advantage of a ring
counter over a binary counter is that it is self-decoding. No extra decoding
circuit is needed to determine what state the counter is in.

Johnson Counters

Johnson counters are a variation of standard ring counters, with the inverted
output of the last stage fed back to the input of the first stage. They are also
known as twisted ring counters. An n-stage Johnson counter yields a count
sequence of length 2n, so it may be considered to be a mod-2n counter. The
circuit above shows a 4-bit Johnson counter. The state sequence for the counter
is given in the table as well as the animation on the left.

Again, the apparent disadvantage of this counter is that the maximum available states are not fully
utilized. Only eight of the sixteen states are being used.
Beware that for both the Ring and the Johnson counter must initially be forced into a valid state in
the count sequence because they operate on a subset of the available number of states.
Otherwise, the ideal sequence will not be followed.

Shift Register Counters

Two of the most common types of shift register counters are introduced here: the Ring counter and the Johnson counter. They are
basically shift registers with the serial outputs connected back to the serial inputs in order to produce particular sequences. These
registers are classified as counters because they exhibit a specified sequence of states.
Ring Counters
A ring counter is basically a circulating shift register in which the output of the most significant
stage is fed back to the input of the least significant stage. The following is a 4-bit ring counter
constructed from D flip-flops. The output of each stage is shifted into the next stage on the
positive edge of a clock pulse. If the CLEAR signal is high, all the flip-flops except the first one FF0
are reset to 0. FF0 is preset to 1 instead.

Since the count sequence has 4 distinct states, the counter can be considered as a
mod-4 counter. Only 4 of the maximum 16 states are used, making ring counters
very inefficient in terms of state usage. But the major advantage of a ring
counter over a binary counter is that it is self-decoding. No extra decoding
circuit is needed to determine what state the counter is in.

Johnson Counters

Johnson counters are a variation of standard ring counters, with the inverted
output of the last stage fed back to the input of the first stage. They are also
known as twisted ring counters. An n-stage Johnson counter yields a count
sequence of length 2n, so it may be considered to be a mod-2n counter. The
circuit above shows a 4-bit Johnson counter. The state sequence for the counter
is given in the table as well as the animation on the left.

Again, the apparent disadvantage of this counter is that the maximum available states are not fully
utilized. Only eight of the sixteen states are being used.
Beware that for both the Ring and the Johnson counter must initially be forced into a valid state in
the count sequence because they operate on a subset of the available number of states.
Otherwise, the ideal sequence will not be followed.
Sequential Logic Circuits
Introduction
Combinational logic refers to circuits whose output is strictly depended on the present value of the inputs. As soon as inputs are changed, the
information about the previous inputs is lost, that is, combinational logics circuits have no memory. In many applications, information regarding input
values at a certain instant of time is required at some future time. Although every digital system is likely to have combinational circuits, most systems
encountered in practice also include memory elements, which require that the system be described in terms of sequential logic. Circuits whose outputs
depends not only on the present input value but also the past input value are known as sequential logic circuits. The mathematical model of a
sequential circuit is usually referred to as a sequential machine.
A general block diagram of a sequential circuit is shown below in Figure 1.

Figure 1. Block Diagram of Sequential Circuit.

The diagram consists of combinational circuit to which memory elements are connected to form a feedback path. The memory elements are devices
capable of storing binary information within them. The combinational part of the circuit receives two sets of input signals: one is primary (coming from
the circuit environment) and secondary (coming from memory elements). The particular combination of secondary input variables at a given time is
called the present state of the circuit. The secondary input variables are also know as the state variables.
The block diagram shows that the external outputs in a sequential circuit are a function not only of external inputs but also of the present state of the
memory elements. The next state of the memory elements is also a function of external inputs and the present state. Thus a sequential circuit is
specified by a time sequence of inputs, outputs, and internal states.
Synchronous and Asynchronous Operation
Sequential circuits are divided into two main types: synchronous and asynchronous. Their classification depends on the timing of their signals.
Synchronous sequential circuits change their states and output values at discrete instants of time, which are specified by the rising and falling edge of
a free-running clock signal. The clock signal is generally some form of square wave as shown in Figure 2 below.

Figure 2. Clock Signal

From the diagram you can see that the clock period is the time between successive transitions in the same direction, that is, between two rising or two
falling edges. State transitions in synchronous sequential circuits are made to take place at times when the clock is making a transition from 0 to 1
(rising edge) or from 1 to 0 (falling edge). Between successive clock pulses there is no change in the information stored in memory.
The reciprocal of the clock period is referred to as the clock frequency. The clock width is defined as the time during which the value of the clock
signal is equal to 1. The ratio of the clock width and clock period is referred to as the duty cycle. A clock signal is said to be active high if the state
changes occur at the clock's rising edge or during the clock width. Otherwise, the clock is said to be active low. Synchronous sequential circuits are
also known as clocked sequential circuits.
The memory elements used in synchronous sequential circuits are usually flip-flops. These circuits are binary cells capable of storing one bit of
information. A flip-flop circuit has two outputs, one for the normal value and one for the complement value of the bit stored in it. Binary information can
enter a flip-flop in a variety of ways, a fact which give rise to the different types of flip-flops. For information on the different types of basic flip-flop
circuits and their logical properties, see the previous tutorial on flip-flops.
In asynchronous sequential circuits, the transition from one state to another is initiated by the change in the primary inputs; there is no external
synchronisation. The memory commonly used in asynchronous sequential circuits are time-delayed devices, usually implemented by feedback among

logic gates. Thus, asynchronous sequential circuits may be regarded as combinational circuits with feedback. Because of the feedback among logic
gates, asynchronous sequential circuits may, at times, become unstable due to transient conditions. The instability problem imposes many difficulties
on the designer. Hence, they are not as commonly used as synchronous systems.
Summary of the Types of Flip-flop Behaviour
Since memory elements in sequential circuits are usually flip-flops, it is worth summarising the behaviour of various flip-flop types before proceeding
further.
All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and in the response invoked by different value of
input signals. The four types of flip-flops are defined in Table 1.
Table 1. Flip-flop Types

FLIP-FLOP
NAME

SR

JK

FLIP-FLOP SYMBOL

CHARACTERISTIC TABLE

Q(next)

CHARACTERISTIC
EQUATION

Q(next) = S + R'Q

0
SR = 0

EXCITATION TABLE

Q(next)

Q(next)

Q(next)

Q'

Q(next)

Q(next)

Q'

Q(next) = JQ' + K'Q

Q(next) = D

Q(next) = TQ' + T'Q

Q(next)

Q(next)

Each of these flip-flops can be uniquely described by its graphical symbol, its characteristic table, its characteristic equation or excitation table. All flipflops have output signals Q and Q'.
The characteristic table in the third column of Table 1 defines the state of each flip-flop as a function of its inputs and previous state. Q refers to the
present state and Q(next) refers to the next state after the occurrence of the clock pulse. The characteristic table for the RS flip-flop shows that the
next state is equal to the present state when both inputs S and R are equal to 0. When R=1, the next clock pulse clears the flip-flop. When S=1, the flipflop output Q is set to 1. The equation mark (?) for the next state when S and R are both equal to 1 designates an indeterminate next state.
The characteristic table for the JK flip-flop is the same as that of the RS when J and K are replaced by S and R respectively, except for the
indeterminate case. When both J and K are equal to 1, the next state is equal to the complement of the present state, that is, Q(next) = Q'.
The next state of the D flip-flop is completely dependent on the input D and independent of the present state.
The next state for the T flip-flop is the same as the present state Q if T=0 and complemented if T=1.
The characteristic table is useful during the analysis of sequential circuits when the value of flip-flop inputs are known and we want to find the value of
the flip-flop output Q after the rising edge of the clock signal. As with any other truth table, we can use the map method to derive the characteristic
equation for each flip-flop, which are shown in the third column of Table 1.
During the design process we usually know the transition from present state to the next state and wish to find the flip-flop input conditions that will
cause the required transition. For this reason we will need a table that lists the required inputs for a given change of state. Such a list is called the
excitation table, which is shown in the fourth column of Table 1. There are four possible transitions from present state to the next state. The required

input conditions are derived from the information available in the characteristic table. The symbol X in the table represents a "don't care" condition, that
is, it does not matter whether the input is 1 or 0.
State Tables and State Diagrams
We have examined a general model for sequential circuits. In this model the effect of all previous inputs on the outputs is represented by a state of the
circuit. Thus, the output of the circuit at any time depends upon its current state and the input. These also determine the next state of the circuit. The
relationship that exists among the inputs, outputs, present states and next states can be specified by either the state table or the state diagram.
State Table
The state table representation of a sequential circuit consists of three sections labelled present state, next state and output. The present state
designates the state of flip-flops before the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and the
output section lists the value of the output variables during the present state.
State Diagram
In addition to graphical symbols, tables or equations, flip-flops can also be represented graphically by a state diagram. In this diagram, a state is
represented by a circle, and the transition between states is indicated by directed lines (or arcs) connecting the circles. An example of a state diagram
is shown in Figure 3 below.

Figure
3. State
Diagra
m

The binary number inside each circle identifies the state the circle represents. The directed lines are labelled with two binary numbers separated by a
slash (/). The input value that causes the state transition is labelled first. The number after the slash symbol / gives the value of the output. For
example, the directed line from state 00 to 01 is labelled 1/0, meaning that, if the sequential circuit is in a present state and the input is 1, then the next
state is 01 and the output is 0. If it is in a present state 00 and the input is 0, it will remain in that state. A directed line connecting a circle with itself
indicates that no change of state occurs. The state diagram provides exactly the same information as the state table and is obtained directly from the
state table.
Example: This example is taken from P. K. Lala, Practical Digital Logic Design and Testing, Prentice Hall, 1996, p.155.
Consider a sequential circuit shown in Figure 4. It has one input x, one output Z and two state variables Q1Q2 (thus having four possible present states
00, 01, 10, 11).

Figure 4. A
Sequential
Circuit

The behaviour of the circuit is determined by the following Boolean expressions:

Z = x*Q1
D1 = x' + Q1
D2 = x*Q2' + x'*Q1'
These equations can be used to form the state table. Suppose the present state (i.e. Q1Q2) = 00 and input x = 0. Under these conditions, we get Z = 0,
D1 = 1, and D2 = 1. Thus the next state of the circuit D1D2 = 11, and this will be the present state after the clock pulse has been applied. The output of
the circuit corresponding to the present state Q1Q2 = 00 and x = 1 is Z = 0. This data is entered into the state table as shown in Table 2.

Present State
Q1Q2
00
01
10
11

Next State
x=0
x=1
11
11
10
10

01
00
11
10

Output
x=0
0
0
0
0

x=1
0
0
1
1

Table 2. State table for the sequential circuit in Figure 4.

The state diagram for the sequential circuit in Figure 4 is shown in Figure 5.

Figure 5.
State
Diagram
of circuit
in Figure
4.

State Diagrams of Various Flip-flops

Table 3 shows the state diagrams of the four types of flip-flops.

NAME

STATE DIAGRAM

SR

JK

Table 3. State diagrams of the four types of flip-flops.

You can see from the table that all four flip-flops have the same number of states and transitions. Each flip-flop is in the set state when Q=1 and in the
reset state when Q=0. Also, each flip-flop can move from one state to another, or it can re-enter the same state. The only difference between the four
types lies in the values of input signals that cause these transitions.
A state diagram is a very convenient way to visualise the operation of a flip-flop or even of large sequential components.
Analysis of Sequential Circuits
The behaviour of a sequential circuit is determined from the inputs, the outputs and the states of its flip-flops. Both the output and the next state are a
function of the inputs and the present state.
The suggested analysis procedure of a sequential circuit is set out in Figure 6 below.

We start with the logic schematic from

which we can derive excitation equations
for each flip-flop input. Then, to obtain
next-state equations, we insert the
excitation equations into the characteristic
equations. The output equations can be
derived from the schematic, and once we
have our output and next-state equations,
we can generate the next-state and output
tables as well as state diagrams. When we
reach this stage, we use either the table or
the state diagram to develop a timing
diagram which can be verified through
simulation.

Figure 6. Analysis procedure of

sequential circuits.

Now let's look at some examples, using these procedures to analyse a sequential circuit.

Design of Sequential Circuits

The design of a synchronous sequential circuit starts from a set of specifications and culminates in a logic diagram or a list of Boolean functions from
which a logic diagram can be obtained. In contrast to a combinational logic, which is fully specified by a truth table, a sequential circuit requires a state
table for its specification. The first step in the design of sequential circuits is to obtain a state table or an equivalence representation, such as a state
diagram.
A synchronous sequential circuit is made up of flip-flops and combinational gates. The design of the circuit consists of choosing the flip-flops and then
finding the combinational structure which, together with the flip-flops, produces a circuit that fulfils the required specifications. The number of flip-flops is
determined from the number of states needed in the circuit.
The recommended steps for the design of sequential circuits are set out below.

For information on state reduction.

Design of Sequential Circuits
This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.235.
Example 1.3

We wish to design a synchronous sequential circuit whose state diagram is shown in Figure 13. The type of flip-flop to be use is J-K.

Figure 13. State

diagram

From the state diagram, we can generate the state table shown in Table 9. Note that there is no output section for this circuit. Two flip-flops are needed
to represent the four states and are designated Q0Q1. The input variable is labelled x.

Present State
Q0 Q1
00
01
10
11

Next State
x=0

x=1

00
10
10
11

01
01
11
00

Table 9. State table.

We shall now derive the excitation table and the combinational structure. The table is now arranged in a different form shown in Table 11, where the
present state and input variables are arranged in the form of a truth table. Remember, the excitable for the JK flip-flop was derive in Table 1.
Table 10. Excitation table for JK flip-flop

Output Transitions

Flip-flop inputs

Q Q(next)

JK

0
0
1
1

0
1
0
1

0 X
1 X
X 1
X 0

Table 11. Excitation table of the circuit

Present State

Next State

Input

Q0 Q1

Q0 Q1

00
00
01
01
10
10
11
11

00
01
10
01
10
11
11
00

0
1
0
1
0
1
0
1

Flip-flop Inputs
J0K0
J1K1
0X
0X
1X
0X
X0
X0
X0
X1

0X
1X
X1
X0
0X
1X
X0
X1

In the first row of Table 11, we have a transition for flip-flop Q0 from 0 in the present state to 0 in the next state. In Table 10 we find that a transition of
states from 0 to 0 requires that input J = 0 and input K = X. So 0 and X are copied in the first row under J0 and K0 respectively. Since the first row also
shows a transition for the flip-flop Q1 from 0 in the present state to 0 in the next state, 0 and X are copied in the first row under J1 and K1. This process
is continued for each row of the table and for each flip-flop, with the input conditions as specified in Table 10.
The simplified Boolean functions for the combinational circuit can now be derived. The input variables are Q0, Q1, and x; the output are the variables
J0, K0, J1 and K1. The information from the truth table is plotted on the Karnaugh maps shown in Figure 14.

Figure 14. Karnaugh Maps

The flip-flop input functions are derived:
J0 = Q1*x'
J1 = x

K0 = Q1*x
K1 = Q0'*x' + Q0*x = Q0x

Note: the symbol is exclusive-NOR.

The logic diagram is drawn in Figure 15.

Figure 15. Logic

diagram of the
sequential circuit

Design of Sequential Circuits

This example is taken from P. K. Lala, Practical Digital Logic Design and Testing, Prentice Hall, 1996, p.176.
Example 1.4

Design a sequential circuit whose state tables are specified in Table 12, using D flip-flops.

Table 12. State table of a sequential circuit.

Present State

Next State

Output

Q0 Q1

x=0

x=1

x=0

x=1

00
01
10
11

00
00
11
00

01
10
10
01

0
0
0
0

0
0
0
1

Table 13. Excitation table for a D flip-flop.

Output Transitions

Flip-flop inputs

QQ(next)

0
0
0
1
1

0
1
0
1

1
0
1

Next step is to derive the excitation table for the design circuit, which is shown in Table 14. The output of the circuit is labelled Z.

Present State

Next State

Input

Flip-flop Inputs

Output

Q0 Q1

Q0 Q1

D0

D1

00
00
01
01
10
10
11
11

00
01
00
10
11
10
00
01

0
1
0
1
0
1
0
1

0
0
0
1
1
1
0
0

0
1
0
0
1
0
0
1

0
0
0
0
0
0
0
1

Table 14. Excitation table

Now plot the flip-flop inputs and output functions on the Karnaugh map to derive the Boolean expressions, which is shown in Figure 16.

Figure 16. Karnaugh maps

The simplified Boolean expressions are:
D0 = Q0*Q1' + Q0'*Q1*x
D1 = Q0'*Q1'*x + Q0*Q1*x + Q0*Q1'*x'
Z = Q0*Q1*x
Finally, draw the logic diagram.

Figure 17. Logic diagram of the sequential circuit.

Design of Sequential Circuits
This example is taken from P. K. Lala, Practical Digital Logic Design and Testing, Prentice Hall, 1996, p.176.
Example 1.4

Design a sequential circuit whose state tables are specified in Table 12, using D flip-flops.

Table 12. State table of a sequential circuit.

Present State

Next State

Output

Q0 Q1

x=0

x=1

x=0

x=1

00
01
10
11

00
00
11
00

01
10
10
01

0
0
0
0

0
0
0
1

Table 13. Excitation table for a D flip-flop.

Output Transitions

Flip-flop inputs

QQ(next)

D
0

0
0
1
1

0
1
0
1

1
0
1

Next step is to derive the excitation table for the design circuit, which is shown in Table 14. The output of the circuit is labelled Z.

Present State

Next State

Input

Flip-flop Inputs

Output

Q0 Q1

Q0 Q1

D0

D1

00
00
01
01
10
10
11
11

00
01
00
10
11
10
00
01

0
1
0
1
0
1
0
1

0
0
0
1
1
1
0
0

0
1
0
0
1
0
0
1

0
0
0
0
0
0
0
1

Table 14. Excitation table

Now plot the flip-flop inputs and output functions on the Karnaugh map to derive the Boolean expressions, which is shown in Figure 16.

Figure 16. Karnaugh maps

The simplified Boolean expressions are:
D0 = Q0*Q1' + Q0'*Q1*x
D1 = Q0'*Q1'*x + Q0*Q1*x + Q0*Q1'*x'
Z = Q0*Q1*x
Finally, draw the logic diagram.

Figure 17. Logic diagram of the sequential circuit.

Design of Counters
This example is taken from T. L. Floyd, Digital Fundamentals, Fourth Edition, Macmillan Publishing, 1990, p.395.
Example 1.5 A counter is first described by a state diagram, which is shows the sequence of states through which the counter advances when it is
clocked. Figure 18 shows a state diagram of a 3-bit binary counter.

Figure 18. State diagram of a

3-bit binary counter.

The circuit has no inputs other than the clock pulse and no outputs other than its internal state (outputs are taken off each flip-flop in the counter). The
next state of the counter depends entirely on its present state, and the state transition occurs every time the clock pulse occurs. Figure 19 shows the
sequences of count after each clock pulse.

Once the sequential circuit is defined by the state diagram, the next step is to obtain the next-state table, which is derived from the state diagram in
Figure 18 and is shown in Table 15.
Table 15. State table

Present State

Next State

Q2 Q1 Q0

Q2 Q1 Q0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0

Since there are eight states, the number of flip-flops required would be three. Now we want to implement the counter design using JK flip-flops.

Next step is to develop an excitation table from the state table, which is shown in Table 16.
Table 16. Excitation table

Flip-flop inputs

Output State Transitions

Present State

Next State

Q2 Q1 Q0

Q2 Q1 Q0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0

J2 K2

J1 K1

J0 K0

0X
0X
0X
1X
X0
X0
X0
X1

0X
1X
X0
X1
0X
1X
X0
X1

1X
X1
1X
X1
1X
X1
1X
X1

Now transfer the JK states of the flip-flop inputs from the excitation table to Karnaugh maps to derive a simplified Boolean expression for each flip-flop
input. This is shown in Figure 20.

Figure 20.
Karnaugh
maps

The 1s in the Karnaugh maps of Figure 20 are grouped with "don't cares" and the following expressions for the J and K inputs of each flip-flop are
obtained:
J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q1*Q0
The final step is to implement the combinational logic from the equations and connect the flip-flops to form the sequential circuit. The complete logic of
a 3-bit binary counter is shown in Figure 21.

Figure 21. Logic

diagram of a 3bit binary
counter.

Design of Counters
This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.243.
Example 1.6
22.

Design a counter specified by the state diagram in Example 1.5 using T flip-flops. The state diagram is shown here again in Figure

Figure 22. State diagram of a

3-bit binary counter.

The state table will be the same as in Example 1.5.

Now derive the excitation table from the state table, which is shown in Table 17.
Table 17. Excitation table.

Flip-flop inputs

Output State Transitions

Present State

Next State
T2 T1 T0

Q2 Q1 Q0
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Q2 Q1 Q0
0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0

0
0
0
1
0
0
0
1

0
1
0
1
0
1
0
1

1
1
1
1
1
1
1
1

Next step is to transfer the flip-flop input functions to Karnaugh maps to derive a simplified Boolean expressions, which is shown in Figure 23.

Figure 23.
Karnaugh
maps

The following expressions are obtained:

T0 = 1;

T1 = Q0;

T2 = Q1*Q0

Finally, draw the logic diagram of the circuit from the expressions obtained. The complete logic diagram of the counter is shown in Figure 24.

Figure 24. Logic diagram of

3-bit binary counter.

To see the timing and state transitions of the counter, click on this image.