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IEEE P1801 The Unified Power Format for Low Power Designs UPF Introduction Dennis Brophy Vice-Chairman,
IEEE P1801
The Unified Power Format for Low Power Designs
UPF Introduction
Dennis Brophy
Vice-Chairman, Accellera
Agenda – 13:00-13:05 Introduction • Dennis Brophy, Vice-Chairman – Accellera – 13:05-13:30 Architecting a low
Agenda
– 13:00-13:05
Introduction
• Dennis Brophy, Vice-Chairman – Accellera
– 13:05-13:30
Architecting a low power design with UPF
• Larry Vivolo, Director Low Power Solutions – Synopsys
– 13:30-14:00
Synthesizing and implementing the low power design
• Arvind Narayanan, Product Director – Magma Design
Automation
– 14:00-14:20
Functional verification of a low power design
• Stephen Bailey, Chair – IEEE P1801 WG
– 14:20-14:30
UPF Experience & Conclusion
• Yatin Trivedi, Magma Design Automation
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UPF Update - DATE 2008 - Munich, Germany
What is Accellera’s Mission – Drive the worldwide development and use of standards required by
What is Accellera’s Mission
– Drive the worldwide development and use of
standards required by systems,
semiconductor and design tool companies
that enhance a language-based design
automation process.
– The Unified Power Format is closely
associated with the design and verification
languages sponsored by Accellera.
3
UPF Update - DATE 2008 - Munich, Germany
Accellera Members Officers: Members: Chairman Shrenik Mehta Sun Microsystems • Aldec • Nokia • ARM
Accellera Members
Officers:
Members:
Chairman
Shrenik Mehta
Sun Microsystems
• Aldec
• Nokia
• ARM Ltd.
• Novas
• Azuro
• OneSpin Solutions
• Cadence Design Systems
Vice-Chairman
Dennis Brophy
Mentor Graphics
• Qualcomm Inc.
• Certess
• Rockwell Collins
• Cisco
• Silvaco
• Denali Software Inc.
• SpringSoft, Inc.
Secretary
Karen Bartelson
Synopsys
• Freescale Semiconductor
• ST Microelectronics
• IBM
• Infineon Technologies
• Sun Microsystems
• Intel Corporation
• Synopsys
Treasurer
Stan Krolikoski
Cadence
• Jasper Design Automation
• Texas Instruments
• Magma Design Automation
• Xilinx
• Mentor Graphics
… and over 4,000 Designers Forum members
BOLD: Accellera Board Member
4 UPF Update - DATE 2008 - Munich, Germany
Industry Need • Power has become the dominate factor in the design of today’s electronic
Industry Need
• Power has become the dominate factor in the design of
today’s electronic systems
– Explosion in battery operated systems
– Many (most) non-portable designs are also constrained by
power consumption requirements
• Heat generation and dissipation
• Practical power supply & management
• Current state is a hodge-podge of commercial and ad
hoc solutions
– SAIF, GAF, etc.
– Specification of power aware design characteristics
• Often done late at gate-level and ad hoc
– Need to verify correctness of power-aware functionality
– Done sooner and with higher correlation to design intent
5
UPF Update - DATE 2008 - Munich, Germany
Action Initiated • DAC 2006: – TI and Nokia organized a meeting on the topic
Action Initiated
• DAC 2006:
– TI and Nokia organized a meeting on the topic of an
open standard for low power design flows
– The 4 top EDA vendors attended
• Plus Atrenta
– Broad, significant user representation including
• Texas Instruments
• Nokia
• ARM
• ST Microelctronics
• Philips (NXP)
• Sun Microsystems
– Shrenik Mehta represented Accellera
6
UPF Update - DATE 2008 - Munich, Germany
UPF Timeline Proposed Week Of Milestone 11 Sep 06 Accellera TSC formation Initial TSC Meeting
UPF Timeline Proposed
Week Of
Milestone
11
Sep 06
Accellera TSC formation
Initial TSC Meeting
18
Sep 06
Design Objectives Document; Weekly
meetings start
5 Oct 06
Si2 / Accellera Workshop on Low
Power
30
Oct 06
First drafts available for review
30
Nov 06
Submission to Accellera Board for
Approval
31
Jan 07
Hand-off to IEEE and/or other suitable
standards organizations
7
UPF Update - DATE 2008 - Munich, Germany
Actual UPF Timeline Week Of Milestone 28 Aug 06 Accellera TSC formation 18 Sep 06
Actual UPF Timeline
Week Of
Milestone
28
Aug 06
Accellera TSC formation
18
Sep 06
Frequent telecon and face-to-face
meetings commence
25
Sep 06
Design Objectives Document
05
Oct 06
Accellera/Si2 Sponsored Workshop
23
Oct 06
All donations accepted
27
Dec 06
First draft available for review
8
UPF Update - DATE 2008 - Munich, Germany
Actual UPF Timeline (2) Week Of Milestone 19 Jan 07 Final draft available for review
Actual UPF Timeline (2)
Week Of
Milestone
19
Jan 07
Final draft available for review
23
Jan 07
Final draft completion
23
Jan 07
Accellera TSC approval
24
Jan 07
Submission to Accellera Board for
Approval
22
Feb 07
Accellera Board approval
May 07
Transfer to IEEE working group
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UPF Update - DATE 2008 - Munich, Germany
Accellera Moves UPF to IEEE • Accellera policy is to transfer its standards to IEEE
Accellera Moves UPF to IEEE
• Accellera policy is to transfer its standards
to IEEE
– UPF is in the IEEE stage of standardization
– IEEE P1801 was formed in 2007
• Accellera supports IEEE/IEC dual logo
process
10
UPF Update - DATE 2008 - Munich, Germany
Agenda – 13:00-13:05 Introduction • Dennis Brophy, Vice-Chairman – Accellera – 13:05-13:30 Architecting a low
Agenda
– 13:00-13:05
Introduction
• Dennis Brophy, Vice-Chairman – Accellera
– 13:05-13:30
Architecting a low power design with UPF
• Larry Vivolo, Director Low Power Solutions – Synopsys
– 13:30-14:00
Synthesizing and implementing the low power design
• Arvind Narayanan, Product Director – Magma Design
Automation
– 14:00-14:20
Functional verification of a low power design
• Stephen Bailey, Chair – IEEE P1801 WG
– 14:20-14:30
UPF Experience & Conclusion
• Yatin Trivedi, Magma Design Automation
11
UPF Update - DATE 2008 - Munich, Germany
IEEE P1801 The Unified Power Format for Low Power Designs Architecting a low power design
IEEE P1801
The Unified Power Format for Low Power Designs
Architecting a low power design with UPF
Larry Vivolo
Synopsys
12
UPF Update - DATE 2008 - Munich, Germany
Agenda • The Power Challenge • Techniques for Power Management • Building a UPF Low-Power
Agenda
• The Power Challenge
• Techniques for Power Management
• Building a UPF Low-Power Flow
• Benefits of the UPF Flow
13
UPF Update - DATE 2008 - Munich, Germany
Everyone Knows… Low Power is a Problem for Portable Devices It’s all about battery life
Everyone Knows… Low Power is a
Problem for Portable Devices
It’s all about
battery life
14
UPF Update - DATE 2008 - Munich, Germany
Low Power Challenge Not Limited to Hand-held Devices System Packaging & Cooling Facilities Computing 1
Low Power Challenge
Not Limited to Hand-held Devices
System
Packaging & Cooling
Facilities
Computing
1
0.9
0.8
0.7
0.6
0.5
0.4
Graphics
0.3
0.2
0.1
0
0
20
40
60
80
Temperature
Reliability
Networking
Cost
15
UPF Update - DATE 2008 - Munich, Germany
Reliability
Design Techniques for Low Power Constant Variable Throughput/Latency Throughput/Latency Design Time Non-Active
Design Techniques for Low Power
Constant
Variable
Throughput/Latency
Throughput/Latency
Design Time
Non-Active Modules
Run Time
Dynamic &
Short
Circuit
Logic
Re-Structuring,
Logic Sizing
Reduced V DD
Multi-V DD
Clock Gating
Dynamic or
Adaptive
Frequency &
Voltage Scaling
Leakage
Stack Effect
+ Multi-V TH
Sleep Transistors
Multi-V DD
Variable V TH
Variable V TH
Source: J. Rabaey, UCB 2005
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UPF Update - DATE 2008 - Munich, Germany
How to Automate these Techniques ? • Overlay power intent on top of the design
How to Automate these Techniques ?
Overlay power intent on top of the design
Power Domain 1
Power Domain 3
Power Domain 2
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UPF Update - DATE 2008 - Munich, Germany
PS_2
PS_1
PS_3
Each Step in Flow Requires Power Intent Verify retention plus power up/down cycles RTL Verif
Each Step in Flow Requires
Power Intent
Verify retention plus power up/down cycles
RTL Verif
Add low power elements wherever needed and optimize
for multi-voltage, multi-vth operation, plus test
Synthesis
Verify RTL vs gates, plus low power rules
Pre-Verif
Implement optimal power grid, floorplan & switches,
P&R with power grid & layout intent/constraints
Layout
Verify final design vs. RTL, validate low power
structures
Post-Verif
Signoff on power grid integrity, timing, power
Signoff
Finished
GDSII
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UPF Update - DATE 2008 - Munich, Germany
UPF + RTL Provide a Complete Low Power Design Specification • Power Domains UPF UPF
UPF + RTL Provide a Complete
Low Power Design Specification
• Power Domains
UPF UPF
RTL RTL
• Power Distribution Network
– Switches and Supply Nets
Synthesis
• Power State
UPF UPF
Netlist Netlist
• Level Shifting
• Isolation
P&R
• Retention
UPF UPF
• Switching Activity
GDSII GDSII
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UPF Update - DATE 2008 - Munich, Germany
Simulation, Logical Equivalence Checking, …
Unified Power Format UPF Benefits • Productivity RTL Verif – Same intent used throughout entire
Unified Power Format
UPF Benefits
• Productivity
RTL Verif
– Same intent used throughout entire
low power flow
Synthesis
– Interoperability and productivity with
mixed EDA flows
Pre-Verif
• High Quality Results
Layout
– Consistent intent throughout flow =
better checking and convergence
Post-Verif
– IEEE P1801 approach enables
successive refinement
Signoff
Finished
• Simple IP Reuse
GDSII
– Supports IP specification and use
– No changes needed to golden HDL
20
UPF Update - DATE 2008 - Munich, Germany
UPF Benefits • Open standard / Interoperability – Accellera open standards development • Multiple donations
UPF Benefits
• Open standard / Interoperability
– Accellera open standards development
• Multiple donations
• All members participated on equal basis
– IEEE P1801
• UPF copyright assigned to IEEE with the right to
create derivative works
• All members have an equal vote
• No member has veto control over UPF
21
UPF Update - DATE 2008 - Munich, Germany
IEEE P1801 The Unified Power Format for Low Power Designs Synthesizing and Implementing Low Power
IEEE P1801
The Unified Power Format for Low Power Designs
Synthesizing and Implementing Low Power Designs
Arvind Narayanan
Magma Design Automation
Power Aware Design Implementation Dynamic Power Reduction Leakage Power Reduction BACK BIAS MVDD Low Power
Power Aware Design Implementation
Dynamic Power Reduction
Leakage Power Reduction
BACK BIAS
MVDD
Low Power CTS
MTCMOS
Vdb
Stand-by
MTCMOS
1.08v
Vdd
Constant
Domain
Active
LS
Bias
Lines
IC
Active
Always-ON Buffers
Clock Gate
Enable
Vss
Register
Control
Vsb
Stand-by
DVFS
MULTI-VT
Low VT
Nom VT
High VT
Dynamic
Vdd
Voltage Supply Dynamic Voltage
Circuit Supply Circuit
Vdd
RTL Synthesis
Physical Synthesis
Ref
TalusTalus PowerPower
ProPro
&&
RTL Synthesis
Physical Synthesis
CTS
Vss
CTS
Gnd
Place & Route
Place & Route
QuartzQuartz RailRail
Power Analysis & Distribution
Power Grid
MTCMOS
Analysis Power & IR Drop
Thermal Analysis
Rail EM
Transient
Synthesis
Analysis
23
UPF Update - DATE 2008 - Munich, Germany
Advanced Low Power Techniques for Mobile Devices ASIC Imaging & 2D/3D Video Domain 3 ARM11
Advanced Low Power Techniques for Mobile
Devices
ASIC
Imaging &
2D/3D
Video
Domain 3
ARM11
Graphics
TMS320C55x
Accelerator
+ VFP
Accelerato
DSP
(IVA)
RAM
r
Domain 3
L3 Interconnect
ASIC/Clocks
LCD
I/F
Domain 2
Camer
Memory
Internal
Video
a I/F
Controller
SRAM
Out
RAM
Domain 3
*
* TI OMAP2
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UPF Update - DATE 2008 - Munich, Germany
Security
L4 Interconnect
Peripherals
DSP
Domain 1
Design Implementation using Flow Unified Power Format • Domain Definition Talus Design Talus Power Pro
Design Implementation using Flow
Unified Power Format
• Domain Definition
Talus Design
Talus Power Pro
– Power domains
Synthesis
– Supply rails
• Domain Relationship
Power state tables
Talus Vortex
Talus Power Pro
Layout
• Special Cells
– Retention
– Isolation
Quartz Rail
– Level shifters
– Switches
Signoff
25
UPF Update - DATE 2008 - Munich, Germany
Defining Domains and Electrical Conditions Logical Electrical Physical UPF Commands 0.8 1.0 v Domain1 v
Defining Domains and Electrical
Conditions
Logical Electrical Physical
UPF Commands
0.8
1.0
v
Domain1
v
create_power_domain
constant
add_domain_element
LS
connect_supply_net
PM
ctrl
logic
create_supply_net
IS
Diagram
from Andrew
O
create_supply_port
get_supply_net
LS
merge_power_domains
set_domain_supply_net
Domain2
Constant
0.8
v
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UPF Update - DATE 2008 - Munich, Germany
Domain0 switched
Level Shifters in MVDD flows Level shifter considerations: VDD 1.1v VDD1 – Pick a power
Level Shifters in MVDD flows
Level shifter considerations:
VDD 1.1v
VDD1
– Pick a power domain or a set
of elements
0.9v
– Select input ports, output
ports, or both
VDD2
1.5v
– Tolerate a voltage difference
threshold
– UP shift or down SHIFT rule
VDD 1.3v
VDD1
1.1v S
– Location (self, parent, sibling,
fanout, auto)
– Insert or not insert
VDD2
1.1v C
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UPF Update - DATE 2008 - Munich, Germany
Level Shifter insertion using UPF UPF Commands set_level_shifter 1.2v map_level_shifter Constant User Defined
Level Shifter insertion using UPF
UPF Commands
set_level_shifter
1.2v
map_level_shifter
Constant
User Defined
Regions
• Automatic rule based insertion
Isolation
Cell
0.9v
Switched
1.08v
• Length dependant and IR drop
dependent Insertion
Constant
Supply Type
• Electrical Rule Checks to identify
domain relationships
• Well spacing rules honored
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UPF Update - DATE 2008 - Munich, Germany
Level Shifter Routing Topologies • Fishbone style – Each Level Shifter has its own secondary
Level Shifter Routing Topologies
• Fishbone style
– Each Level Shifter has its own secondary
tap
– Minimizes IR drop on secondary supply
• Non-Fishbone Style
– User can specify number of Level Shifter
to share a secondary tap
– Eliminates routing congestion
Minimal pins share a common
‘trunk’ and route directly to the
closest power net.
Level Shifter Types
GND
GND
A
A
VDD
VDDS
VDDS
Y
Y
VDD
GND
VDDS
VDD
VDDS
A
A
VDD
LS connected by one trunk when not
routing in the ‘fishbone’ style.
Y
Y
GND
GND
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UPF Update - DATE 2008 - Munich, Germany
Isolation Cells for Shut Down Domains UPF Commands 1.0v set_isolation set_isolation_control map_isolation_cell PM
Isolation Cells for Shut Down Domains
UPF Commands
1.0v
set_isolation
set_isolation_control
map_isolation_cell
PM ctrl
logic
• Automatic placement close
to domain boundary
ISOLATION
• Options for clamp “0” or “1”
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UPF Update - DATE 2008 - Munich, Germany
Domain0 switched
Retention Flops in Shut Down Domains UPF Commands 1.0v set_retention set_retention_control map_retention_cell PM
Retention Flops in Shut Down Domains
UPF Commands
1.0v
set_retention
set_retention_control
map_retention_cell
PM ctrl
logic
• Maintains state of domains
that are powered down
ISOLATION
RETENTION
• Automatic placement and
power connectivity
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UPF Update - DATE 2008 - Munich, Germany
Domain0 switched
Switch Cell inference using UPF UPF Commands 1.2v 200Mhz Switched VDD create_power_switch SW1 -domain pdA
Switch Cell inference using UPF
UPF Commands
1.2v
200Mhz
Switched VDD
create_power_switch SW1 -domain pdA
-input_supply_port {inp PR}
-output_supply_port {outp RET}
1.4v
200Mhz
set_domain_supply_net pdA
-primary_power_net PR
-primary_ground_net VSS
Constant VDD
Ln1
Lp1
Ln3
Lp3
Ln2
Distributed MTCMOS
Fine Grain
Global
Standard cell specific
Grid based insertion
Lp2
PR
RET
spAOn
SW1
SW1
Module A
pdA
Logic
32
UPF Update - DATE 2008 - Munich, Germany
MTCMOSMTCMOS
1.6v
200Mhz
Switched VDD
Enable Line Stitching • Automatic enable line stitching MTCMOS 1.08v Domain Constant – Enable line
Enable Line Stitching
• Automatic enable line stitching
MTCMOS
1.08v
Domain
Constant
– Enable line treated as high fan-out net
(special buffers needed)
– Single and dual enable controls
supported
– Daisy chain support for switches with
built-in buffers
– Incremental enable line stitching
supported
Enable
Control
Always-ON
Daisy Chain Modes
Buffers
o
switch
switch
switch
switch
switch
switch
switch
switch
o
switch
switch
switch
switch
switch
switch
switch
switch
o
o
o
o
o
o
o
u
o
o
o
o
o
o
o
o
in
u
in
in
u
in
u
u
in
u
in
in
u
in
u
u
in
u
in
in
u
in
u
in
in
u
u
in t
u
in
u
u
switch
t
switch
t
switch
t
switch
t
switch
t
switch
t
switch
switch
t
o
t
switch
t
switch
o
t
switch
t
switch
o
o
t
switch
t
switch
t
switch
t
switch
t
o
o
o
o
o
o
o
o
o
o
o
o
in
u
in
in
u
in
u
u
in
u
in
in
u
in
u
u
in
u
in
in
in
u
in
u
in
u
u
in
u
in
u
u
switch
t
switch
t
switch
t
switch
t
switch
t
switch
t
o
switch
t
switch
t
o
switch
t
switch
t
switch
t
switch
t
switch
t
t
switch
t
o
o
o
o
o
o
switch
switch
t
o
o
o
o
o
o
o
o
in
in
in
u
u
u
in
u
in
in
in
u
in
u
u
u
in
in
in
u
in
in
u
in
u
u
in
in
u
u
u
u
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay
controlled
enable
33
UPF Update - DATE 2008 - Munich, Germany
Power State Table • A power state table defines the legal combinations of states for
Power State Table
• A power state table defines the legal combinations of
states for different domains
• create_pst command creates a PST, using a specific
order of supply nets during operation of the design
• Each row defines a valid combination of supply
states
• Power states enable optimization and verification
– Infer or verify level shifters and isolation gates
UPF Commands
create_pst
add_pst_state
34
UPF Update - DATE 2008 - Munich, Germany
Power Integrity Sign-Off • Power/IR drop sign-off solution to ensure power network integrity RTL RTL
Power Integrity Sign-Off
• Power/IR drop sign-off solution to ensure power network integrity
RTL RTL
• Accuracy
Power
– Built-in spice engine for sign-off accuracy
– Static & transient power & IR drop analysis
Spice
IR
• Integration
Engine
Drop
– Concurrent optimization and analysis for optimal QoR
Quartz
– IR drop induced delay
Rail
• Predictability
Rail
Thermal
– RTL-to-GDSII power sign-off accuracy with early predictability
EM
IR
Drop
Delay
Support for SAIF from UPF
GDSII GDSII
Power Grid
MTCMOS
Analysis Power & IR Drop
Rail EM
Transient
Synthesis
Thermal Analysis
Analysis
35
UPF Update - DATE 2008 - Munich, Germany
IEEE P1801 The Unified Power Format for Low Power Designs Verification of Low Power Designs
IEEE P1801
The Unified Power Format for Low Power Designs
Verification of Low Power Designs
Stephen Bailey
Mentor Graphics
Agenda • UPF-Based PA Design Flow – System-level power specification – Reusable IP block power
Agenda
• UPF-Based PA Design Flow
– System-level power specification
– Reusable IP block power specification
– RTL power design
– Implementation flow
– Gate-level power verification
• UPF: The Industry Standard for Low
Power Design
• Conclusions
37
UPF Update - DATE 2008 - Munich, Germany
Agenda • UPF-Based PA Design Flow – System-level power specification – Reusable IP block power
Agenda
• UPF-Based PA Design Flow
– System-level power specification
– Reusable IP block power specification
– RTL power design
– Implementation flow
– Gate-level power verification
• UPF: The Industry Standard for Low
Power Design
• Conclusions
38
UPF Update - DATE 2008 - Munich, Germany
System Power View of Example Design -- Interleaver Power Domain View Logic Hierarchy View •
System Power View of Example
Design -- Interleaver
Power Domain View
Logic Hierarchy
View
• Simple power
architecture
PD_Interleaver
PD_rx
TestBench
• Simple for
education
purposes
in2wire
pktcntr
interleaver
in2wire
out2wire
pktcntr
FIFO
• Power
domains:
PD_tx
fifo
RAM
out2wire
PD_tx
– PD_tx
ram
PD_rx
– PD_rx
39
UPF Update - DATE 2008 - Munich, Germany
Defining the System Power States PD PD_tx_vdd PD_tx_vss PD_rx_vdd PD_rx_vss Supply State Duplex On On
Defining the System Power
States
PD
PD_tx_vdd
PD_tx_vss
PD_rx_vdd
PD_rx_vss
Supply
State
Duplex
On
On
On
On
Transmit
On
On
Off
On
Receive
Off
On
On
On
Sleep
Off
On
Off
On
40
UPF Update - DATE 2008 - Munich, Germany
Interleaver Power State Specification PD_tx_vdd PD_tx_vss PD_rx_vdd PD_rx_vss create_pst \ interleaver_pst
Interleaver Power State
Specification
PD_tx_vdd
PD_tx_vss
PD_rx_vdd
PD_rx_vss
create_pst \
interleaver_pst
PD_tx_vdd
vss
PD_rx_vdd
vss
Duplex
On
On
On
On
add_pst_state
Duplex
PD_tx_vddon
vsson
PD_rx_vddon
vsson
Transmit
On
On
Off
On
add_pst_state
Transmit
PD_tx_vddon
vsson
PD_rx_vddoff
vsson
Receive
Off
On
On
On
add_pst_state
Receive
PD_tx_vddoff
vsson
PD_rx_vddon
vsson
Sleep
Off
On
Off
On
add_pst_state
Sleep
PD_tx_vddoff
vsson
PD_rx_vddoff
vsson
41
UPF Update - DATE 2008 - Munich, Germany
Exploiting Power State Data • Required for implementation QoR – Ensure electrically correct implementation –
Exploiting Power State Data
• Required for implementation QoR
– Ensure electrically correct implementation
– Optimize away unneeded power logic
• No level shifters if source/sink always at same voltage
• No isolation if source/sink off relative to each other
• Can be exploited in verification
– Checks for missing level shifters and isolation
– Coverage, e.g., The PMB’s FSM
– Assertions to flag entry into undefined power state
– …
42
UPF Update - DATE 2008 - Munich, Germany
Agenda • UPF-Based PA Design Flow – System-level power specification – Reusable IP block power
Agenda
• UPF-Based PA Design Flow
– System-level power specification
– Reusable IP block power specification
– RTL power design
– Implementation flow
– Gate-level power verification
• UPF: The Industry Standard for Low
Power Design
• Conclusions
43
UPF Update - DATE 2008 - Munich, Germany
Reusable IP Power Specification Interleaver Contains Reusable IP Block Logic Hierarchy View • In2wire and
Reusable IP Power Specification
Interleaver Contains Reusable IP Block
Logic Hierarchy
View
• In2wire and out2wire blocks
are instances of the same
module
TestBench
• Rdyacpt is the reusable IP
interleaver
module
in2wire
out2wire
pktcntr
FIFO
RAM
rdyacpt #(8) in2wire (
.upstream_rdy(di_rdy),
.upstream_acpt(di_acpt),
.upstream_data(di_data),
.downstream_rdy(in_rdy),
rdyacpt #(8) out2wire (
.upstream_rdy(out_rdy),
.upstream_acpt(out_acpt),
.upstream_data(do_reg),
.downstream_rdy(do_rdy),
.downstream_acpt(do_acpt),
.downstream_data(do_data),
.reset_n(reset_n),
.clk(clk) );
.downstream_acpt(in_acpt),
.downstream_data(input_down_data),
.reset_n(reset_n),
.clk(clk) );
44
UPF Update - DATE 2008 - Munich, Germany
What to Specify for IP to Keep RTL & UPF Reusable • Only specify constraints
What to Specify for IP to Keep
RTL & UPF Reusable
• Only specify constraints for IP usage in a low
power design context:
– Power Domains:
Finest granularity of power domains for the IP
– Retention:
What state must be saved on power down; restored
on power up
– Isolation:
Required logic levels under PSO conditions to ensure
correct functionality
45
UPF Update - DATE 2008 - Munich, Germany
Finest Granularity of Power Domains • Sets of logic that can be shutdown or run
Finest Granularity of Power
Domains
• Sets of logic that can be shutdown or run at
different voltage levels inside the domain
• For rdyacpt:
– Simple logic all on at same time and all operating at
same voltage level
– Could specify no power domain and let it be
subsumed into the parent instance’s power domain
– But, that would not allow us to specify isolation and
retention strategies
# Assumes the caller of the UPF file containing this sets the scope
# to the rdyacpt instance (in2wire or out2wire)
create_power_domain pd_rdyacpt –include_scope
46
UPF Update - DATE 2008 - Munich, Germany
Specify IP State Requiring Retention • Rdyacpt requires state of all registers to be retention
Specify IP State Requiring
Retention
• Rdyacpt requires state of all registers to be
retention registers
– Likely scenario for most IP blocks
– If register values aren’t saved, they need to be
reset on power up
set_retention rdyacpt_ret –domain pd_rdyacpt
# Default is strategy applies to all elements of the domain
# Defer retention logic and implementation specifics to IP
# integrator
• Note: Example utilizes changes in command structure approved by
IEEE WG specifically for use in IP situations such as this.
47
UPF Update - DATE 2008 - Munich, Germany
Specify Isolation Values for IP • For inputs: – Safe values when the source domain
Specify Isolation Values for IP
• For inputs:
– Safe values when the source domain is shutdown and the IP’s
domain is on
• For outputs:
– Safe values for outputs (inactive) where relevant
– Otherwise defer to sink domain to define
RTL code:
always @(posedge clk or negedge reset_n) …
set_isolation rdyacpt_clk_iso –domain pd_rdyacpt
-elements {clk}
-clamp_value 0
set_isolation rdyacpt_rst_iso –domain pd_rdyacpt
-elements {reset_n}
-clamp_value 1
# Other inputs do not trigger activity; no iso required for them
• Note: Example utilizes changes in command structure approved by
IEEE WG specifically for use in IP situations such as this.
48
UPF Update - DATE 2008 - Munich, Germany
IP Integrator Will: • Integrate IP into system’s power architecture – Power: • All supply
IP Integrator Will:
• Integrate IP into system’s power architecture
– Power:
• All supply nets needed by the IP will be created by the IP
integrator
• Supplies associated with the domain as required
– Logic:
• Refine retention strategies to include save/restore logic
control signals
• Refine isolation strategies to include isolation enable
signals
• Add any implementation details required
– Map retention cells
– Add level shifting strategies
49
UPF Update - DATE 2008 - Munich, Germany
Agenda • UPF-Based PA Design Flow – System-level power specification – Reusable IP block power
Agenda
• UPF-Based PA Design Flow
– System-level power specification
– Reusable IP block power specification
– RTL power design
– Implementation flow
– Gate-level power verification
• UPF: The Industry Standard for Low
Power Design
• Conclusions
50
UPF Update - DATE 2008 - Munich, Germany
Quick Review • We have already defined: – The system power states – IP low
Quick Review
• We have already defined:
– The system power states
– IP low power design requirements
• Before we can do an RTL power aware
simulation:
– Need to define chip-level power domains
– Chip supply network
– Chip retention and isolation strategies
• In sufficient detail to simulate low power behavior
– May define level shifting strategies
• Required before synthesis
• May defer to later RTL sign-off verification stage
51
UPF Update - DATE 2008 - Munich, Germany
Chip Power Domain Definition Power Domain View • Power domains: PD_Interleaver – PD_Interleaver – PD_tx
Chip Power Domain Definition
Power Domain View
• Power domains:
PD_Interleaver
– PD_Interleaver
– PD_tx
PD_rx
– PD_rx
in2wire
pktcntr
set_scope .
create_power_domain PD_Interleaver
-include_scope
create_power_domain PD_rx
-elements {in2wire pkt_counter}
create_power_domain PD_tx
-elements {out2wire fifo}
PD_tx
fifo
out2wire
ram
52
UPF Update - DATE 2008 - Munich, Germany
Create the Supply Network vdd_ vss_ pad pad • Common ground for chip PD_Interleaver •
Create the Supply Network
vdd_
vss_
pad
pad
• Common ground for chip
PD_Interleaver
• Switched VDD for PD_rx and
PD_tx
PD_rx
in2wire
pktcntr
• Retention & isolation
supplies
create_supply_port vss_pad –direction in
create_supply_port vdd_pad –direction in
create_supply_net vss
connect_supply_net vss –ports {vss_pad}
create_supply_net vdd
connect_supply_net vdd –ports {vdd_pad}
create_supply_net PD_rx_vdd
create_supply_net PD_tx_vdd
PD_tx
fifo
out2wire
ram
53
UPF Update - DATE 2008 - Munich, Germany
Create the Power Switches for the Chip vdd_ vss_ pad pad • Switch PD_rx primary
Create the Power Switches
for the Chip
vdd_
vss_
pad
pad
• Switch PD_rx primary supply
PD_Interleaver
rx_iso
• Switch PD_tx primary supply
_en
PD_rx
create_power_switch rx_prim_pwr
-output_supply_port {rx_vdd_out PD_rx_vdd}
-input_supply_port {rx_vdd_in vdd}
-control_port {rx_en rx_iso_en}
-on_state {PD_rx_vddon rx_vdd_in {~rx_iso_en}}
in2wire
pktcntr
create_power_switch tx_prim_pwr
-output_supply_port {tx_vdd_out PD_tx_vdd}
-input_supply_port {tx_vdd_in vdd}
-control_port {tx_en tx_iso_en}
-on_state {PD_tx_vddon tx_vdd_in {~tx_iso_en}}
PD_tx
tx_iso
fifo
_en
out2wire
ram
54
UPF Update - DATE 2008 - Munich, Germany
Relate the Supplies to the Domains vdd_ vss_ pad pad • Switch PD_rx primary supply
Relate the Supplies to the
Domains
vdd_
vss_
pad
pad
• Switch PD_rx primary supply
PD_Interleaver
rx_iso
• Switch PD_tx primary supply
_en
PD_rx
create_power_domain PD_Interleaver
-primary_power_net vdd
-primary_ground_net vss
create_power_domain PD_rx
-primary_power_net PD_rx_vdd
-primary_ground_net vss
-default_iso_power_net vdd
-default_ret_power_net vdd
create_power_domain PD_tx
-primary_power_net PD_tx_vdd
-primary_ground_net vss
-default_iso_power_net vdd
-default_ret_power_net vdd
in2wire
pktcntr
PD_tx
tx_iso
fifo
_en
out2wire
ram
• Uses new IEEE command structure
55
UPF Update - DATE 2008 - Munich, Germany
Logic Control of Isolation & Retention vdd_ vss_ • Control signals enabling PD_rx and PD_tx
Logic Control of Isolation &
Retention
vdd_
vss_
• Control signals enabling PD_rx and
PD_tx isolation
pad
pad
PD_Interleaver
rx_iso
_en
• Control signals for save/restore of
PD_rx & PD_tx retention registers
PD_rx
in2wire
pktcntr
set_retention PD_rx_ret –domain PD_rx
-save_signal
{rx_sleep posedge}
-restore_signal {rx_sleep negedge}
set_isolation PD_rx_iso –domain PD_rx
-isolation_signal {rx_iso_en posedge}
rx_
sleep
PD_tx
set_retention PD_tx_ret –domain PD_tx
tx_iso_en
fifo
-save_signal
{tx_sleep posedge}
-restore_signal {tx_sleep negedge}
set_isolation PD_tx_iso –domain PD_tx
-isolation_signal {tx_iso_en posedge}
out2wire
ram
tx_
sleep
• Uses new IEEE command structure
56
UPF Update - DATE 2008 - Munich, Germany
Don’t Forget Logic Configuration of IP Block! • Both instances of rdyacpt’s domains require supply
Don’t Forget Logic Configuration
of IP Block!
• Both instances of rdyacpt’s domains
require supply associations
• IEEE WG is reviewing
easier methods for
accomplishing this level
of configuration
set_scope in2wire
load_upf rdyacpt.upf
create_power_domain PD_rdyacpt
-primary_power_net .PD_rx_vdd
-primary_ground_net .vss
-default_iso_power_net .vdd
-default_ret_power_net .vdd
set_scope .out2wire
load_upf rdyacpt.upf
create_power_domain PD_rdyacpt
-primary_power_net .PD_tx_vdd
-primary_ground_net .vss
-default_iso_power_net .vdd
-default_ret_power_net .vdd
57
UPF Update - DATE 2008 - Munich, Germany
IP Block Retention & Isolation Logic Configuration • Specify the logic control signals for isolation
IP Block Retention & Isolation
Logic Configuration
• Specify the logic control signals for isolation and
retention of both instances of rdyacpt
set_scope .in2wire
set_retention rdyacpt_ret –domain pd_rdyacpt
-save_signal
{rx_sleep posedge}
-restore_signal {rx_sleep negedge}
set_isolation rdyacpt_clk_iso –domain pd_rdyacpt
-isolation_signal {rx_iso_en posedge}
set_isolation rdyact_rst_iso –domain pd_rdyacpt
-isolation_signal {rx_iso_en posedge}
set_scope .out2wire
set_retention rdyacpt_ret –domain pd_rdyacpt
-save_signal
{tx_sleep posedge}
-restore_signal {tx_sleep negedge}
set_isolation rdyacpt_clk_iso –domain pd_rdyacpt
-isolation_signal {tx_iso_en posedge}
set_isolation rdyact_rst_iso –domain pd_rdyacpt
-isolation_signal {tx_iso_en posedge}
58
UPF Update - DATE 2008 - Munich, Germany
Do We Have Enough for RTL Simulation? • Yes, … But – Retention functionality is
Do We Have Enough for RTL
Simulation?
Yes, …
But
– Retention functionality is generic
– If you know your implementation technology
• Should map to a retention simulation model
• Ensures accurate verification of save & restore
protocols
• Relative to other register control signals
Example:
map_retention_cell PD_rx_ret –domain PD_rx
-lib_model_name CFRFF
59
UPF Update - DATE 2008 - Munich, Germany
Do We Have Enough for RTL Simulation? • Yes, … But – Could specify level
Do We Have Enough for RTL
Simulation?
Yes, …
But
– Could specify level shifting strategies
– If multi-voltages employed and operating
voltages are specified
– Necessary prior to RTL implementation!
Example:
set_level_shifter PD_rx_lss –domain PD_rx
-threshold 0.2
-applies_to inputs
-rule low_to_high
60
UPF Update - DATE 2008 - Munich, Germany
UPF Simulation Semantics • General supply connectivity concepts – All logic elements have a set
UPF Simulation Semantics
• General supply connectivity concepts
– All logic elements have a set of supply nets that
deliver power to that element
• At a minimum, power and ground supplies
• UPF provides automated connection semantics
for specific supply types:
– Primary supplies
• Automatically connected to primary power, ground, etc. of the
logic extent of the domain
– Isolation supplies
• Automatically connected to isolation cells created in UPF
– Retention supplies
• Automatically connected to retention portion of retention
registers created in UPF
61
UPF Update - DATE 2008 - Munich, Germany
UPF Power State Semantics • ON = Normal Functional Behavior – All supplies are ON
UPF Power State Semantics
• ON = Normal Functional Behavior
– All supplies are ON
– Normal behavior of the logic
• OFF = Power Shutdown Behavior
– At least one supply is OFF
– Functionality is disabled
– Signals driven by functionality are corrupted
• BIAS = Corrupt on Change Behavior
– Not an ON state with slower, characterized performance
• That would simply be ON with different voltage level(s) of supplies
– “Retention” mode with uncharacterized performance
– Un-characterized performance simulated by corrupting signals
when they change
– New in IEEE version
62
UPF Update - DATE 2008 - Munich, Germany
Agenda • UPF-Based PA Design Flow – System-level power specification – Reusable IP block power
Agenda
• UPF-Based PA Design Flow
– System-level power specification
– Reusable IP block power specification
– RTL power design
– Implementation flow
– Gate-level power verification
• UPF: The Industry Standard for Low
Power Design
• Conclusions
63
UPF Update - DATE 2008 - Munich, Germany
Gate-Level Verification • Options – Simulation: • PG connected netlist • Functional netlist + UPF
Gate-Level Verification
• Options
– Simulation:
• PG connected netlist
• Functional netlist + UPF
– Logic Equivalency Checking
64
UPF Update - DATE 2008 - Munich, Germany
Gate-Level PG Connected Netlist Simulation • If: – Your technology gate library is power-aware •
Gate-Level PG Connected Netlist
Simulation
If:
– Your technology gate library is power-aware
• Has power, ground, bias, etc. pins
• Functionality modeled power-aware
– Behavior cognizant of PSO, bias modes, etc.
• Implementation tools fully connect the supply network to the
cell instances
• Then:
– Nothing more to do as power-aware simulation
semantics are automatic
– Exception: Timing (bias modes)
• Likely addressed by simulating each state separately
65
UPF Update - DATE 2008 - Munich, Germany
Gate-Level Functional Netlist + UPF Simulation • Technology library is NOT modeled power-aware – No
Gate-Level Functional Netlist +
UPF Simulation
• Technology library is NOT modeled power-aware
– No PG pins on cells
– EXCEPTION: Retention registers must model “balloon latch”
retention capability
• Implementation tools must output
– Gate-level functional netlist
– SDF timing
– UPF that contains the supply network specification for the gate-
level design
• How power is supplied to each element in the design
– UPF would not include what is part of netlist
• No retention, isolation or level shifting specification
• These cells should already be in the netlist
66
UPF Update - DATE 2008 - Munich, Germany
Logic Equivalency Checking • Enhanced to perform power equivalency checking – Match low power functionality
Logic Equivalency Checking
• Enhanced to perform power equivalency
checking
– Match low power functionality specified in
UPF to the gate level netlist:
• Physical switches exist where required as per the
UPF abstract supply switching specification
• Isolation cells with appropriate functionality on
connections between domains
• Registers with retention functionality that matches
the save/restore semantics implied or specified
• Each element is supplied according to UPF
specification
67
UPF Update - DATE 2008 - Munich, Germany
IEEE P1801 The Unified Power Format for Low Power Designs UPF Usage Experience Yatin Trivedi
IEEE P1801
The Unified Power Format for Low Power Designs
UPF Usage Experience
Yatin Trivedi
Magma Design Automation
UPF Experience • Multiple Perspectives – Suppliers • Build tools & technology • Deliver training
UPF Experience
• Multiple Perspectives
– Suppliers
• Build tools & technology
• Deliver training & consulting
– Consumers
• Design & Verification engineers
69
UPF Update - DATE 2008 - Munich, Germany
UPF: Participating Companies UPF Participating Companies Technology donations to Accellera UPF TSC • Nokia •
UPF: Participating Companies
UPF Participating Companies
Technology donations to Accellera
UPF TSC
• Nokia
• AMD
• Mentor Graphics
• Nordic Semi
• ArchPro
• External power configuration file for verification
• Novas
• ARM
• Magma
• NXP
• Atrenta
• Power Management commands
• Qualcomm
• Azuro
• Vast
• Si2
• System level modeling methodology and
format
• STARC
• ChipVision
• STM
• FreeScale
• Synopsys
• Synchronous DA
• IBM
• RTL constructs (Verilog and VHDL)
• Synopsys
• Infineon
• Power Management commands
• TI
• Intel
• Switching activity format – SAIF
• Toshiba
• LCDM Eng
• Texas Instruments
• VaST
• LSI Logic
• Retention cell semantics
• Virage Logic
• Magma
• Atrenta, Synchronous DA
• Xilinx
• Mentor
Accellera: Consumers Suppliers
IEEE: Consumers Suppliers
70
UPF Update - DATE 2008 - Munich, Germany
Low Power Solutions a Year Later David Peterman of TI receives UPF 1.0 on behalf
Low Power Solutions a Year Later
David Peterman of TI receives UPF 1.0 on behalf of User community
from Accellera Chairman Shrenik Mehta
71
UPF Update - DATE 2008 - Munich, Germany
UPF 1.0 Industry Endorsement & Support • Infineon: The quick development and release of the
UPF 1.0 Industry
Endorsement & Support
• Infineon:
The quick development and release of the UPF 1.0 standard is based on our close partnership
relations with EDA suppliers who share the same vision and attitude in making things happen.
We are convinced that UPF will support us in achieving zero-defect quality and our productivity
objectives, which both are key for Infineon's World class Automotive Product Portfolio.
Hartmut Hiller, Senior Director Design Methodology Automotive, Industrial & Multimarket
• Nokia:
Nokia is committed to use UPF standard in SoC production flow. Finding a Power Management
Flow for SoC design is everyone’s interest.
Mika Naula, Senior System Architect, Nokia
• Synopsys:
Applauds Accellera for approving the UPF standard for low power design and verification. We
plan to deliver our UPF 1.0-based implementation and verification solution during 2007. In
response to customer demand for a standard that enables consistent and interoperable end-
user low power flows and methodologies, Synopsys - together with Magma Design Automation,
Mentor Graphics, leading end-customers and IP companies - has made strong contributions to
UPF 1.0 based on our proven technologies. UPF 1.0 is ready for industry use.
Rich Goldman, Vice President, Synopsys, Strategic Market Development
72
UPF Update - DATE 2008 - Munich, Germany
UPF 1.0 Industry Endorsement & Support • Magma: The speed at which the UPF standard
UPF 1.0 Industry
Endorsement & Support
• Magma:
The speed at which the UPF standard has been developed and approved
demonstrates the power of one open, inclusive and cooperative industry-wide effort.
Users will realize significant improvements in productivity and quality of results by
having a single, portable file and format with which they can specify, modify and
maintain design data. Accellera, Magma, Mentor, Synopsys and all the companies
that donated technology and expertise should be commended.
Kam Kittrell, General Manager, Design Implementation Business Unit, Magma Design
Automation
• Mentor:
Designers want a single format that is simple to use, extensible, and capable of
describing complex power behavior. The Unified Power Format (UPF) 1.0 standard
achieves this by being open and comprehensive enabling support from leading EDA
vendors and customers for industry-wide adoption. Mentor is committed to
Accellera's UPF 1.0 standard as we are a leading contributor of our proven
technology to this open standard for low power design and verification
Robert Hum, Vice President & General Manager, Mentor Graphics Design Verification
& Test Division
73
UPF Update - DATE 2008 - Munich, Germany
UPF EDA Support – Digital Design Other 34% UPF 66% Based on Q4 05 through
UPF EDA Support – Digital Design
Other
34%
UPF
66%
Based on Q4 05 through Q3 06 EDAC MSS data plus other publicly available market data
74
UPF Update - DATE 2008 - Munich, Germany
UPF EDA Support – Digital Simulation 154.7 28.9 29.34 Other 34% UPF 66% Based on
UPF EDA Support – Digital Simulation
154.7 28.9
29.34
Other
34%
UPF
66%
Based on 2007 John Cooley DeepChip DevCon Survey “Mindshare” – 818 Respondents
75
UPF Update - DATE 2008 - Munich, Germany
Full Catalog of UPF Products 76 UPF Update - DATE 2008 - Munich, Germany
Full Catalog of UPF Products
76
UPF Update - DATE 2008 - Munich, Germany
UPF Tool Flow UPF UPF HDL/ HDL/ RTL RTL Synthesis UPF UPF Verilog Verilog (Netlist)
UPF Tool Flow
UPF UPF
HDL/ HDL/
RTL RTL
Synthesis
UPF UPF
Verilog Verilog
(Netlist) (Netlist)
P&R
UPF UPF
Verilog Verilog
(Netlist) (Netlist)
77
UPF Update - DATE 2008 - Munich, Germany
Simulation, Logical Equivalence Checking, …
78 UPF Update - DATE 2008 - Munich, Germany
78
UPF Update - DATE 2008 - Munich, Germany
SpyGlass Power SpyGlass Power Power Reduction and Planning Power Reduction and Planning upf@atrenta.com Intelligent
SpyGlass Power
SpyGlass Power
Power Reduction and Planning
Power Reduction and Planning
upf@atrenta.com
Intelligent power reduction and domain planning at RTL
Intelligent power reduction and domain planning at RTL
UPF
UPF
Power Estimation
Power Estimation
Library data
Library data
Timing-aware power estimation at RTL, gates, layout
Timing-aware power estimation at RTL, gates, layout
Supplies
Supplies
Scope
Scope
Power Domain Sequencing
Power Domain Sequencing
Domains
Domains
Signals
Signals
Formally prove power up/down sequencing
Formally prove power up/down sequencing
Power & Voltage Domain Verification
Power & Voltage Domain Verification
Verify and fix level shifter, isolation logic, SRPG, MTCMOS
Verify and fix level shifter, isolation logic, SRPG, MTCMOS
RTL, gates, layout
RTL, gates, layout
79
UPF Update - DATE 2008 - Munich, Germany
MPSim UPF Specification Simulate power off corruption Simulate retention and save/restore of states Simulate
MPSim
UPF Specification
Simulate power off corruption
Simulate retention and
save/restore of states
Simulate isolation and clamping
RTL
Test bench
Designer
Trace complete power network and
switches
Visualize power switch states
Visualize the states of powered off
blocks throughout simulation
Annotate powered off signals
ProtoMeter
ProtoMeter ProtoMeter
Designer Designer
Coverage Coverage
Debug Debug
Automate power verification
combinations
Verify all possible power
combinations
Power verification closure
upf@axiom-da.com
80
UPF Update - DATE 2008 - Munich, Germany
Gate level netlist Physical Synthesis Placed gates (UPF Q4-07) PowerCentric™ Low Power Clock Implementation
Gate level
netlist
Physical
Synthesis
Placed gates
(UPF Q4-07)
PowerCentric™
Low Power Clock
Implementation
upf@azuro.com
Placed gates
(Balanced clocks)
Routing
GDSII
81
UPF Update - DATE 2008 - Munich, Germany
upf@magma-da.com 82 UPF Update - DATE 2008 - Munich, Germany
upf@magma-da.com
82
UPF Update - DATE 2008 - Munich, Germany
upf@mentor.com 83 UPF Update - DATE 2008 - Munich, Germany Olympus-SoC
upf@mentor.com
83
UPF Update - DATE 2008 - Munich, Germany
Olympus-SoC
Predictable Success Innovator DesignWare IP UPF UPF RTL RTL upf@synopsys.com Design Compiler Ultra Power Compiler
Predictable Success
Innovator
DesignWare IP
UPF UPF
RTL RTL
upf@synopsys.com
Design Compiler Ultra
Power Compiler
DFT Compiler/DFT MAX
UPF UPF
Netlist Netlist
IC Compiler
TetraMax
UPF UPF
GDSII GDSII
84
UPF Update - DATE 2008 - Munich, Germany
VCS , Formality, Leda
PrimeTime (SI, PX)
PrimeRail
upf@viragelogic.com ValueValue AddedAdded IPIP ASAPASAP LogicLogic SpecialtySpecialty I/OsI/Os MetalMetal
upf@viragelogic.com
ValueValue AddedAdded IPIP
ASAPASAP LogicLogic
SpecialtySpecialty I/OsI/Os
MetalMetal ProgrammableProgrammable
High-Speed
High-Density
STARSTAR MemoryMemory SystemSystem
Star Memories
BIST & Repair IP
SSTL-2
HSTL-2
PCI and PCI-X
USB1.1
StandardStandard CellsCells
High-Speed
Ultra-High-Density
Ultra-Low-Power
ECO
ASAPASAP MemoryMemory
High-Speed
Ultra-Low-Power
NOVeANOVeA Non Volatile Memory
*all included in
Base I/O package
IPrima Foundation
High-Density Logic
n
High-Density Memory
85
Base I/O
UPF Update - DATE 2008 - Munich, Germany
Low Power Methodology Manual Contact: Alex.Greene@springer.com 86 UPF Update - DATE 2008 - Munich, Germany
Low Power Methodology Manual
Contact: Alex.Greene@springer.com
86
UPF Update - DATE 2008 - Munich, Germany
Conclusion • User community is actively guiding UPF – All leading users enthusiastically participate –
Conclusion
• User community is actively guiding UPF
– All leading users enthusiastically participate
– Concepts are production proven
• EDA community is strongly behind UPF
– Supported by 8 out of 9 leading vendors
– Interoperability is the key to success
• IEEE standardization On Track
– World-wide adoption assured
– Broad education effort to follow
87
UPF Update - DATE 2008 - Munich, Germany
Questions & Answers
Questions & Answers