Digital System Design Using FPGA

Cheat Sheet for FPGA Configuration

BY: NITIN SINGH

In this Cheat Sheet the use of XILINX 14.2

to Write, Simulate, Synthesize and
Implement a Digital Design using VHDL is
explained. The FPGA configuration using
Digilents Adept is also explained. The
whole process is explained by implementing
a Full Adder on FPGA.

Creating New Project

(i) Select New Project under File Tab.

(ii) Specify Project Name, Location and Type.

(iii) Select the target device and description language.

(iv) Project summary.

(v) Created project will appear on left side under Hierarchy section.

Creating VHDL Source File

(i) Right Click on Target Devices Name and select New Source.

(ii) Select VHDL Module and specify files name. Also check the Add to Project option.

(iii) Specify the Ports of the module to create an Entity.

(iv) Summary of the source file created.

(v) A VHDL source file, based on the user defined specifications, will be created.

(vi) The functionality of the defined Module/Entity can be described after begin key word,
using any suitable method. The code in black box defines the functionality of Full Adder.

(vii) Select Simulation option as indicated by the arrow.

(viii) Checking Syntax error: Under Isim Simulator select Behavioral Check Syntax.

Creating Test Bench File

(i) Right Click on the VHDL source file and select New Source.

(ii) Select VHDL Test Bench as file type and write the file name. Check Add to project option.

(iii) Select the file name for which test bench is to be created.

(iv) A summary file based on the specifications given will be generated.

(v) A Test Bench file consisting of some VHDL code will be generated: This file will appear on
left side with the name UUT (Unit Under Test).

(vi) The Test Bench file will contain a section Clock process definition, if in the defined module
clock signal is not required then delete this section.

(vii) The input ports can be assigned desired values using assignment statements. These
statements are to be added after the comment - - insert stimulus here.

(viii) After creating Test Bench file double click on Simulate Behavioral Model (as indicate by
the arrow)

(ix) A simulation window will appear with some green lines, to view the signal properly, select
Zoom to full view (as indicated by the arrow).

(x) On selecting Zoom to full view the input and output waveforms will appear. The input and
output values corresponding to the selected region of the waveform will appear on left side of
the waveform.

Creating Constraint File (PORT MAPPING)

(i) Right click on source file and select New Source.

(ii) Select the Implement Constraint File as source type and specify the file name.

(iii) Summary of the created file will appear.

(iv) A blank Constraint file will be generated.

(v) Write the desired port mapping in the file, as shown in following figure.

SPARTAN-6
XC6SLX45 FPGA

(vi) After Creating constraint file double click on Synthesize-XST, Implement Design and
Generating Programming File, One by One. Generating Programming File option generates a
file with .bit extension, which will be used to program the FPGA.

FPGA Configuration Using ADEPT

(i) Digilents Adept software is used to implement the design on FPGA. Double click on Adept
and following window will appear.

(ii) Connecting FPGA to a Desktop/Laptop.

(iii) Now connect the FPGA. Under Connect option, on top right, name of the device will
appear. On selecting the device following window will appear.

(iv) Click on Browse and select .bit file which is to be implemented on FPGA.

(v) Click on Program option and wait until the programming process is over.

(vi) After completion following window appears.

Testing Full Adder On FPGA

CARRY SUM

c=0 b=0 a=0

CARRY SUM

c=0 b=0 a=1

CARRY SUM

c=0 b=1 a=1

CARRY SUM

c=1 b=1 a=1