Flip-Flops

1. Introduction
As informaes armazenadas em circuitos sobre a histria prvia das entradas
so chamadas armazenamento ou elementos de memria. Um elemento primitivo
de armazenamento pode ser construdo de um nmero pequeno de portas
conectando as sadas de volta como tambm as entradas. Esses circuitos so
clulas binrias capazes de armazenar um nico bit de informao. Eles tem duas
sadas, um para valores normais e outra para valores complementares de bit
armazenados nele. Elementos da memria primitive realmente se inserem em duas
grandes classes: latches e flip-flop.
Se uma latch tem somente entradas de dados, ela chamdad de unlocked
latch (ou somente latch). As latches sensveis de nvel tem uma entrada de
habilitao adicional, as vezes chamada de clock. Level-sensitive latches
continuously sample their inputs when they are enabled. Any change in the level of
the input is propagated through to the output. When the enable signal is
unasserted, the last value of the inputs is determines the state held by the latch.
Flip-flops differ from latches in that their output change only with repeat to the
clock, whereas latches change output when their inputs change. Flip-flops are
characterized on the basis of the clock transition that cause the output change :
there are positive edge-triggered, negative edge-triggered, and master/slave flipflops.
A positive edge-triggered flip-flop samples its inputs on the low-to-high clock
transition. A negative edge-triggered flip-flop works in a similar fashion, with the
input sampled on the high-to-low clock transition.
A master-slave flip-flop is constructed from two stage separate flip-flops. The
first stage ( first flip-flop) samples the inputs on the rising edge of a clock signal.
The second stage transfer them to the output on the falling edge of the clock
signal.
These circuits have two additional control inputs. These are Preset and Clear,
which force the output of the flip-flop or latch to the logic-1 or logic-0 state,
respectively, independent of the flip-flop or latch inputs [2].
S-R Latch:

A S-R ( Set-Reset) latch is the simplest possible memory element.

It is constructed by feeding the outputs of two NOR gates back to the other
NOR gates input.
The inputs R and S are referred to as the Reset and Set inputs, respectively.
To understand the operation of the S-R latch consider the following scenarios :
S=1 and R=0: The output of the bottom NOR gate is equal to zero,
Q 0 .
Hence both inputs to the top NOR gate are equal to zero, thus, Q 1 .
Hence, the input combination S=1 and R=0 leads to the latch being set to
Q 1.
S=0 and R=1: Similar to the arguments above, the outputs become
Q 1 and Q 0 .
We say that the latch is reset.
13

S=0 and R=0: Assume the latch is set ( Q 0 and Q 1 ), then the
output of the top NOR gate remains at Q 1 and the bottom NOR gate
stays at Q 0 .
Similary, when the latch is in a reset state ( Q 1 and Q 0 ), it will
remain there with this input combination.
Therefore, with inputs S=0 and R=0, the latch remains in its state.
S=1 and R=1: This input combination must be avoided
The logic diagram and graphic symbol are shown in Figure.4.1.
The following truth table can be summarized the operation of the S-R
latch.
R

Q '

S
(a) Logic Diagram
S
0
0
1
1

Q'

(b)Graphic Symbol

R
0
1
0
1

Q
Q
0
1
-

Q'
Q'
1
0
-

Comment
Hold State
Reset
Set
Forbidden

(c) Truth table

Figure.4.1 S-R latch with NOR gates.

A S-R latch can also be constructed from NAND gates. The

graphic symbol, logic diagram, and truth table of the latch are
shown in Figure.4.2.
S

Q '

(a) Logic Diagram

S
1
0
1

R
1
1
0

Q
Q
1
0

Q'

(b)Graphic Symbol
Q'
Q'
0
1

14

Comment
Hold State
Set
Reset

Forbidden

(c) Truth table

Figure.4.2 S-R latch with NAND gates.
Level Sensitive (Clock) S-R Latch:
The operation of the S-R latch can be modified by providing an additional
control input that determines when the state of the circuit is to be changed. The logic
diagram, graphic symbol, and thruth table of level sensitive S-R latch are shown in
Figure.4.3 [1].

Q '

Q'

(a) Logic Diagram

S
0
0
1
1
x

R
0
1
0
1
x

(b)Graphic Symbol
C
1
1
1
1
0

Q
Q
0
1
Q

Q'
Q'
1
0
Q'

Comment
Hold State
Reset
Set
Forbidden
Hold State

(c) Truth table

Figure.4.3 Level Sensitive S-R latch with NAND gates.
Level Sensitive (Clock) D (Delay) Latch :
One way to eliminate the undesirable condition of the indeterminate state in
the S-R latch is to ensure that inputs S and R are never equal to 1 at the state time.
This is done level sensitive D latch shown in Figure.4.4. The latch has only two
inputs: D and C. The D input connect directly to the S input and its complement is
applied to the R input. The D input is sampled when C is equal to 1. If D is equal to
1, the Q output goes to 1. If D is equal to 0, the Q output goes to 0. If C is equal to
0, the Q output remains in its previous state [1].

D
Q

Q '

Q'

C
15

(a) Logic Diagram

(b)Graphic Symbol

C
1
1
0

D
0
1
x

Q
0
1
Q

Q'
1
0
Q'

(c) Truth table

Figure.4.4 Level Sensitive D latch with NAND gates.
Level Sensitive (Clock) J-K Latch:
A level sensitive J-K latch shown in Figure.4.5 is a refinement of the S-R latch
in that the indeterminate state of the S-R type is defined in the J-K type. Inputs J and
K behave like inputs S and R to set and clear the latch, respectively. The input
marked J is for set and the input marked K is for reset. When the both inputs J and K
are equal to 1, the latch switches to its complement state, that is , if Q=1, it switches
to Q=0, and vice versa. If the C is equal to 0, The output of the latch remains in its
previous state [1].

C
Q '

J
(a) Logic Diagram
C
1
1
1
1
0

J
0
0
1
1
x

Q'

(b)Graphic Symbol
K
0
1
0
1
x

Q
Q
0
1
Q'
Q

Q'
Q'
1
0'
Q
Q'

(c) Truth table

16

Comment
Hold
Reset
Set
Toggle
Hold

Figure.4.5 Level Sensitive J-K latch.

D Flip-Flop:

Positive-Edge Triggered:

CLK

Q'

Q'

Q'

(a) Truth table

CLK

Q'

(b) Graphic Symbol

Figure.4.6. Positive edge-triggered D flip-flop.

Negative-Edge Triggered:
CLK

Q'

Q'

17

CLK

Q'

Q'

(a) Truth table

(b) Graphic Symbol

Figure.4.7. Positive edge-triggered D flip-flop.

J-K Flip-Flop:
Positive-Edge Triggered:
CLK

Q'

Q'

CLK

0
1

Q'

x
x

x
x

Q
Q

Q'
Q'

(a) Truth table

Q'

(b) Graphic Symbol

Figure.4.8. Positive edge-triggered J-K flip-flop.

Negative-Edge Triggered:
CLK

Q'

Q'

CLK
1

18

Q'

0
1

Q'

x
x

x
x

Q
Q

Q'
Q'

(a) Truth table

(b) Graphic Symbol

Figure.4.9. Negative edge-triggered J-K flip-flop.

T Flip-Flop:
The T flip-flop is a single-input version of the J-K flip-flop. As shown in
Figure.4.10, the T flip-flop is obtained from the J-k flip-flop when both inputs are tied
together. The designation T comes from the ability of the flip-flop to toggle, or
complement, its state. While input T is 1, The flip-flop complements its output when
the clock pulse occurs. While T is 0, The output of the flip-flop remains in its
previous state [1].
CLK

0
1

Q'

Q'

Q'

x
x

Q
Q

Q'
Q'

T
CLK

J
CLK
K

(a) Truth table

Q'

(b) Graphic Symbol

Figure.4.10. Negative Edge-Triggered T flip-flop.

19