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DATA SHEET
For a complete data sheet, please also download:
74HC/HCT191
Presettable synchronous 4-bit
binary up/down counter
Product specification December 1990
File under Integrated Circuits, IC06
Philips Semiconductors Product specification
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Philips Semiconductors Product specification
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
tPHL/ tPLH propagation delay CP to Qn CL = 15 pF; VCC = 5 V 22 22 ns
fmax maximum clock frequency 36 36 MHz
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 31 33 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC −1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
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Philips Semiconductors Product specification
PIN DESCRIPTION
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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Philips Semiconductors Product specification
FUNCTION TABLE
INPUTS OUTPUTS
OPERATING MODE
PL U/D CE CP Dn Qn
L X X X L L
parallel load
L X X X H H
count up H L I ↑ X count up
count down H H I ↑ X count down
hold (do nothing) H X H X X no change
Notes
1. H = HIGH voltage level
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
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Philips Semiconductors Product specification
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Philips Semiconductors Product specification
Sequence
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Philips Semiconductors Product specification
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Philips Semiconductors Product specification
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Philips Semiconductors Product specification
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Philips Semiconductors Product specification
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Philips Semiconductors Product specification
AC WAVEFORMS
Fig.10 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width and the
maximum clock pulse frequency.
Fig.11 Waveforms showing the clock and count enable inputs (CP, CE) to ripple clock output (RC) propagation
delays.
Fig.12 Waveforms showing the input (Dn) to output (Qn) propagation delays.
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Philips Semiconductors Product specification
Fig.13 Waveforms showing the input (PL) to output (Qn) propagation delays.
Fig.14 Waveforms showing the up/down count input (U/D) to terminal count and ripple clock output (TC, RC)
propagation delays.
Fig.15 Waveforms showing the parallel load input (PL) pulse width, removal time to clock (CP) and the output
(Qn) transition times.
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Philips Semiconductors Product specification
Fig.16 Waveforms showing the set-up and hold times from the parallel load input (PL) to the data input (Dn).
Fig.17 Waveforms showing the set-up and hold times from the count enable and up/down inputs (CE, U/D) to the
clock (CP).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
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