2014 International Conference on Computational Science and Computational Intelligence

A Neural Network-Based Design Automation of

a Second Generation Current Conveyor

Nihan KAHRAMAN

Tuba KIYAN

Electronics and Telecommunication Engineering

Yildiz Technical University
Istanbul, Turkey
nicoskun@yildiz.edu.tr

Electronics and Telecommunication Engineering

Yildiz Technical University
Istanbul, Turkey
tkiyan@yildiz.edu.tr

I y
V
x
I z

Abstract An artificial neural network approach for the

automated design of a positive type second generation current
conveyor is presented in this paper. A multi-layer perceptron
structure is successfully employed to estimate the
corresponding transistor dimensions for a given set of desired
performance criteria of the circuit. Data generated by a circuit
simulation program (SPICE) is used to train the artificial
neural network. The excellent agreement between the desired
specifications and the actual results from SPICE simulation
results approves that neural networks are powerful tools for
automated analog circuit sizing.

INTRODUCTION

Analog circuits such as amplifiers, filters, oscillators

either can be designed in voltage mode or current mode [13]. Since current mode circuits have the potential
advantages such as wider bandwidth, simpler circuitry,
lower power consumption, and wider dynamic range, they
are preferred to their voltage mode counterparts.
Artificial neural networks (ANN) and evolutionary
algorithms are employed as aids in circuit design. In the
literature, there is some work that optimizes current
conveyor performance by using some optimization
algorithms. In [4], a steepest descent algorithm is used to
adjust the transistor sizes to obtain an optimum performance
for a filter that is designed using CCII+. In [5], bacterial
foraging optimization algorithm is used for finding the
transistor dimensions in order to increase the performance
of a CCII+. In [6], a heuristic methodology is used to
optimize an ultra low voltage rail to rail CCII.
This paper aims to estimate the transistor dimensions for
a given set of specifications. An ANN is employed to attain
the sizes of all the transistors employed in the second
generation current conveyor.

rE

0 V y
0 I x
0 V z

(1)

III. DESIGN METHODOLOGY

The aim is to estimate the transistor sizes for the CCII+
for a given set of specifications by employing artificial
neural networks. In order to accomplish this, Levenberg
Marquart algorithm and multilayer perceptron (MLP)
structure is used. MLP is a feed-forward artificial neural
network model that maps sets of input data onto a set of
appropriate outputs. It is trained with the error backpropagation learning algorithm. The system has two hidden
and one output layer. Logarithmic sigmoid in hidden layers
and linear function in output layer is used as an activation
function. The first and second hidden layer has 20 and 10
neurons, respectively. The number of output neurons is 6.
The learning rate for Levenberg Marquardt is 0.6 and
momentum constant is 0.1.
MLP maps sets of input data onto a set of appropriate
transistor dimension space. The desired performance criteria
such as current and voltage ranges for a linear operation,
bandwidth of the current and voltage follower and input
resistances of each terminals, are given to the artificial
network as inputs and corresponding transistor sizes are
obtained as outputs of the system. The circuit is simulated
with the obtained transistor dimensions and the results are
evaluated and presented in Section IV.

II. SECOND GENERATION CURRENT CONVEYORS

CCII is a four-terminal active element. The terminal
equations are defined in Equation 1 for a non-ideal current
conveyor.
978-1-4799-3010-4/14 $31.00 2014 IEEE
DOI 10.1109/CSCI.2014.150

0
0

A positive type second generation current conveyor (Fig.

1) is designed by using TSMC 0.25m design parameters.
Positive and negative supply voltages are taken as +2.5V
and -2.5V, respectively. CMOS CCII+ is simulated by using
SPICE. Considering the circuit specifications, the transistor
dimensions are adjusted .
The linearity between Iz and Ix is maintained, only when
Ix is larger than -100 A and smaller than 100 A.
Moreover, Vx follows Vy for -0.8 V < Vy < 0.8 V. According
to frequency domain simulation results, the bandwidth of
iz/ix current gain is 150 MHz and that of vx/vy voltage gain is
9 GHz.

Keywords- Computer aided design (CAD); neural networks;

positive second generation current conveyor (CCII+); multilayer
perceptron (MLP).

I.

0
D

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SPICE simulations, which consists of design specifications

as inputs to the MLP and transistor sizes as outputs. MLP
maps sets of input data onto a set of appropriate transistor
dimension space
A test vector is applied in order to verify the system. It is
shown that the system produces the accurate transistor sizes
for a given set of performance requirements which makes it
suitable for computer aided design (CAD) applications.

Figure 1. CMOS CCII+

IV. ANN BASED CIRCUIT SIZING RESULTS

A pattern which has the iputs given in Table I is used to
test the designed ANN. These inputs are the performance
requirements that the circuit is expected to meet. The trained
ANN produces the transistor sizes as outputs as shown in
Table II. To verify these results, we implemented SPICE
simulations using the W/L that are obtained by ANN. The
simulation results for this particular test pattern are shown in
Figure 2 and Figure 3. It is observed that SPICE simulation
results are consistent with the desired specifications.

Figure 2. The frequency response of vx/vy voltage gain

TABLE I. T HE INPUTS FOR THE ANN

Specifications

Current range for a linear

current follower (Iz=Ix)
Voltage range for a linear
voltage follower (Vy=Vx)
Bandwidth of the Vx/Vy

-100 A < Ix < 100 A

-0.4 V < Vx < 0.6 V

10.07 GHz

Bandwidth of the Iz/Ix

167 MHz

Figure 3. The frequency response of iz/ix current gain

Impedance of terminal X

5.33 K:

REFERENCES

Impedance of terminal Y

3.8 T:

[1]

Impedance of terminal Z

132 G:

[2]
[3]

TABLE II. The Output of the ANN

Transistor
T1
T2
T3
T4

W
[m]
0.8965
0.8965
2.0827
2.0827

L
[m]
0.2591
0.2591
0.2473
0.2473

Transistor
T5
T6
T7
T8

W
[m]
2.0827
2.0827
1.3282
1.3282

[4]

L
[m]
0.2473
0.2473
25.0474
25.0474

[5]

[6]

V. CONCLUSION
In this work, we successfully demonstrated how CMOS
CCII+ can be automatically designed for changing
performance requirements which is achieved by employing
a MLP structure for this task. It has two hidden and one
output layer. First and second hidden layers have twenty and
ten neurons, respectively and output layer has six neurons.
A set of training vector and test vector is produced using

314
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