8051 Memory Map

7F

General Purpose RAM

30
2F

7F

7E

7D

7C

7B

7A

79

78

2E

77

76

75

74

73

72

71

70

2D

6F

6E

6D

6C

6B

6A

69

68

2C

67

66

65

64

63

62

61

60

2B

5F

5E

5D

5C

5B

5A

59

58

2A

57

56

55

54

53

52

51

50

29

4F

4E

4D

4C

4B

4A

49

48

28

47

46

45

44

43

42

41

40

27

3F

3E

3D

3C

3B

3A

39

38

26

37

36

35

34

33

32

31

30

25

2F

2E

2D

2C

2B

2A

29

28

24

27

26

25

24

23

22

21

20

23

1F

1E

1D

1C

1B

1A

19

18

22

17

16

15

14

13

12

11

10

21

0F

0E

0D

0C

0B

0A

09

08

20

07

06

05

04

03

02

01

00

1F
Register Bank 3
18
17
Register Bank 2
10
0F
Register Bank 1
08
07
Default Register Bank (Bank 0)
00

The Special Function Register (SFR)

F0

F7

F6

F5

F4

F3

F2

F1

F0

B Register

E0

E7

E6

E5

E4

E3

E2

E1

E0

ACC

Accumulator

D0

D7

D6

D5

D4

D3

D2

D1

D0

PSW

Program Status Word

B8

BF

BE

BD

BC

BB

BA

B9

B8

IP

Interrupt Priority Control

B0

B7

B6

B5

B4

B3

B2

B1

B0

P3

Port 3

A8

AF

AE

AD

AC

AB

AA

A9

A8

IE

Interrupt Enable Control

A0

A7

A6

A5

A4

A3

A2

A1

A0

P2

Port 2

SBUF

Serial Data Buffer

99
98

9F

9E

9D

9C

9B

9A

99

98

SCON

Serial Control

90

97

96

95

94

93

92

91

90

P1

Port 1

8D

TH1

Timer/Counter 1 high byte

8C

TH0

Timer/Counter 0 high byte

8B

TL1

Timer/Counter 1 low byte

8A

TL0

Timer/Counter 0 low byte

89

TMOD

Timer/Counter Mode Control

TCON

Timer/Counter Control

87

PCON

Power Control

83

DPH

Data Pointer high byte

82

DPL

Data Pointer low byte

81

SP

Stack Pointer

P0

Port 0

88

80

8F

87

8E

86

8D

85

8C

84

8B

83

8A

82

89

81

88

80

PSW Program Status Word

Bit

Symbol

Specification

PSW.7

CY

Carry Flag

PSW.6

AC

Auxiliary Carry Flag

PSW.5

F0

Flag 0 available to user for general purpose

PSW.4

RS1

Register Bank select bit 1

PSW.3

RS0

Register Bank select bit 0

PSW.2

OV

Overflow Flag

PSW.1

User definable flag

PSW.0

Parity Flag. Set/cleared by hardware to each instruction cycle to

indicate an odd/even number of one bits in the Accumulator

PSW.4

PSW.3

Register Bank

Address of Register Bank

00H to 07H

08H to 0FH

10H to 17H

18H to 1FH

PCON Power Control

Bit

Symbol

Specification

PCON.7

SMOD

Double baud rate bit. If Timer 1 is used to generate baud rate and
SMOD = 1, the baud rate is doubled when the serial port is used in
modes 1, 2 or 3.

PCON.6

Not implemented.

PCON.5

Not implemented.

PCON.4

Not implemented.

PCON.3

GF1

General-purpose flag bit

PCON.2

GF0

General purpose flag bit

PCON.1

PD

Power Down bit. Setting this bit activates the Power Down operation
in the 8051BH (CHMOS).

PCON.0

IDL

Idle Mode bit. Setting this bit activates Idle Mode operation in the
8051BH (CHMOS).

IE Interrupt Enable Register

Bit

Symbol

Specification

IE.7

EA

IE.6

IE.5

ET2

Enable/disable Timer 2 overflow or capture interrupt. (8052 only)

IE.4

ES

Enable/disable serial port interrupt.

IE.3

ET1

Enable/disable Timer 1 overflow interrupt.

IE.2

EX1

Enable/disable external interrupt 1.

IE.1

ET0

Enable/disable Timer 0 overflow interrupt.

IE.0

EX0

Enable/disable external interrupt 0

Disable all interrupts. If cleared, interrupt will be acknowledged. If

set, each interrupt source is individually enabled or disabled by
setting or clearing its enable bit
Not implemented.

Interrupt Vector Table

Interrupt Source

Vector Address

Interrupts

RST

0000H

System reset

IE0

0003H

External Interrupt 0

TF0

000BH

Timer 0

IE1

0013H

External Interrupt 1

TF1

001BH

Timer 1

RI & TI

0023H

Serial Port

TF2 & EXF2 (8052only)

002BH

Timer 2

IP Interrupt Priority Register

Bit

Symbol

Specification

IP.7

Not implemented.

IP.6

Not implemented.

IP.5

PT2

Defines the Timer 2 interrupt priority level. (8052 only)

IP.4

PS

Defines the serial port interrupt priority level.

IP.3

PT1

Defines the Timer 1 interrupt priority level.

IP.2

PX1

Defines External interrupt priority level.

IP.1

PT0

Defines the Timer 0 interrupt priority level.

IP.0

PX0

Defines External interrupt priority level.

TCON Timer/Counter Control Register

Bit

Symbol

Specification

TCON.7

TF1

Timer 1 overflow flag. Set on overflow. Clear as processor vector.

TCON.6

TR1

Timer 1 run control bit. Set/clear to turn ON/OFF.

TCON.5

TF0

Timer 0 overflow flag. Set on overflow. Clear as processor vector.

TCON.4

TR0

Timer 0 run control bit. Set/clear to turn ON/OFF.

TCON.3

IE1

External Interrupt 1 edge flag. Set on detect. Clear on processed.

TCON.2

IT1

Interrupt 1 type control bit. Set/Clear for edge/level-0 trigger.

TCON.1

IE0

External Interrupt 0 edge flag. Set on detect. Clear on processed.

TCON.0

IT0

Interrupt 0 type control bit. Set/Clear for edge/level-0 trigger.

TMOD Timer/Counter Mode Control Register

Bit

Symbol

Specification

TMOD.7

T1Gate

Gate bit. Set, timer only runs while INT-bar is high.

TMOD.6

T1C/T-bar

Timer/Counter select. Set for counter. Clear for timer

TMOD.5

T1M1

Mode selector bit

TMOD.4

T1M0

Mode selector bit

TMOD.3

T0Gate

Gate bit. Set, timer only runs while INT-bar is high.

TMOD.2

T0C/T-bar

Timer/Counter select. Set for counter. Clear for timer

TMOD.1

T0M1

Mode selector bit

TMOD.0

T0M0

Mode selector bit

M1

M0

Mode

Operation

13-bit timer. (MCS-48 compatible)

16-bit timer/counter.

8-bit auto-reload timer/counter.

1
1
3
Split timer.
Split timer: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an
8-bit timer and controlled by Timer 1 control bits. (Timer 1) timer/counter 1 stopped.

SCON Serial Port Control Register

Bit

Symbol

SCON.7

SM0

Serial Port mode select

SCON.6

SM1

Serial Port mode select

SCON.5

SM2

Enable the multiprocessor communications features in modes 2&3.

SCON.4

REN

Receiver enable set/clear to enable/disable.

SCON.3

TB8

Transmitter bit 8 the 9th bit transmitted in 9-bit UART.

SCON.2

RB8

Receiver bit 8 the 9th bit received in 9-bit UART.

SCON.1

TI

Transmit interrupt flag set when entire byte has been transmitted.

RI

Receive interrupt flag set when entire byte has been received.

SCON.0
Multiprocessor feature:

Specification

In mode 2 or 3, if SM2 is set, RI will be activated if received the 9th bit.

In mode 1, if SM2 is set, RI will not active if a valid stop bit was not received.
In mode 0, SM2 should be cleared.

SM0

SM1

Mode

Description

Shift register

Fosc/12

8-bit UART

Variable

9-bit UART

Fosc/64 or Fosc/32

9-bit UART

Variable

Alternative Function of Port 3

Bit

Symbol

Specification

P3.7

RD

External Data Memory read strobe.

P3.6

WR

External Data Memory write strobe.

P3.5

T1

Timer/Counter 1 external input.

P3.4

T0

Timer/Counter 0 external input.

P3.3

INT1

External interrupt 1.

P3.2

INT0

External interrupt 0.

P3.1

TXD

Serial output port.

P3.0

RXD

Serial input port.

Baud Rate