THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

ECNG 3016
ADVANCED DIGITAL ELECTRONICS
http://myelearning.sta.uwi.edu/course/view.php?id=686
Semester II 2010

1.

GENERAL INFORMATION
Lab #:
Name of the Lab:

Practical 4
Further State Machine and VHDL Work

Lab Weighting:

0%

Delivery mode:

Lecture

Online
 Lab

Other

Venue for the Lab:

Microprocessor Laboratory

Lab Dependencies2

The theoretical background to this lab is provided in ECNG 3016

Theoretical content link: given at top of page
Pre-Requisites ECNG 2004
To undertake this lab, students should be able to:
1. Use of Xilinx ISE in the implementation of digital system
2. VHDL for synthesis and simulation

Recommended prior
knowledge and
skills3:
Course Staff

Position/Role

Estimated total study

hours1:

Cathy Radix

Lecturer

E-mail

Cathy.Radix@sta.uwi.tt

Azim Abdool

Instructor

azim.abdool@sta.uwi.tt

Phone

x3157

x2636

Office

Office
Hours
Rm
321, Mon/Tue
Blk 1
11am 2pm
Rm 341/ Mon/
RTSG, Blk 1 Thu
11am12pm

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

2.

LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to:
1. Create VHDL testbenches using the ISim simulator in Xilinx ISE to test simple
VHDL circuits

2. Devise a block diagram depicting dataflow for a simple description of a

digital system
3. Design and implement a VHDL specified system to meet constraints of a
dataflow diagram including the usage of a state machine.

3.

Cognitive Level
Ap
Sy
Ap, Sy

PRE-LAB

Due Date:
Submission
Procedure:
Estimated time to
completion:

NA
-

3.1. Pre-Lab Exercise

For this laboratory exercise we will be using the given 4x4 keypads. These keypads work on a process of
connecting two pins together when a key is pressed. Download and bring a copy of the keypad datasheet to
the lab. A method of figuring out which key is pressed is to assign some pins as input and others as output.
This way by continually scanning those connected to the FPGA as outputs (i.e. the FPGAs inputs), and
outputting a sequential masked value on the ones connected as inputs (the FPGAs outputs) then the inputs
to the FPGA can be read and the exact key that is pressed can be ascertained.
Consider the following components:
1. a state machine decoder which will scan the keypad for a pressed key and toggle a one-hot output
(16 bits) based on which key is pressed
2. a debounce module which would create a cleaned one shot clock pulse of each of the the one-hot
outputs
3. a synchronizer module which would synch each of the one-hot outputs of the debounce module to
that of the system clock

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

4. an encoder module which would take the one hot outputs of the debounce module and latch a BCD
code representing the key that was pressed
5. a shift-left register which takes as its inputs a BCD code and when given a control signal will shift in
the BCD code on the least significant byte on a 4 byte parallel output
6. a time multiplexing display module which would take a 4 byte BCD input and output the result on
the 4 7-segment displays
7. a frequency divider capable of providing the system clock, a debounce clock and a time multiplexing
clock frequencies

Draw a diagram illustrating a simple digital system which would utilize the above components to take a key
pressed on the keypad and display it on the four 7-segment displays , and each successive key pressed shift
it in on the least significant end of the display. Be sure that you include on the diagram the port names
(entity interface description), the names you intend to assign to any nets (intermediate signals) and the bus
widths of each module.

You will be given the frequency divider, time multiplexing display, debounce and synchronizer modules.

Practical 4: Further Work with VHDL and State Machines

4.

IN-LAB

Allotted Completion
Time:
Required lab
Equipment:

3 hours
1 Computer
1 Spartan 3 Toolkit
1 keypad + 40-pin ribbon cable circuit(completely wired)

4.1. In-Lab Procedure

Read and analyze the implementation of the given modules. How do they work? Are they as you expect?
Do they meet the constraints of the block diagram that you have drawn?

Write a VHDL module to implement the shift left register. The entity description for a typical shift left
register that has parallel data input and parallel data output has a clock, reset, clock_enable (which
enables the module), a data input (of some width shorter than the output width) and data_output.
The code that you create should follow the following algorithm:

shift_left_register (clock)
if there is a rising edge of the clock
if reset is asserted
clear the output data lines
elsif clock_enable is asserted
output<width-1 to 0>  output<width-inputwidth-1 to inputwidth> concat input
end if
end if
end shift_left_register

Draw a state diagram to illustrate the functionality of the state machine which will be used to scan the
keypad and convert the key pressed to a one-hot representation.

Show and explain your block diagram to your lecturer/TA/demonstrator/student assistant including the
interconnections that you have made, the entity descriptions and behaviour that you expect.

Once they have verified your design, create each of the modules designed in the prelab according to
your block diagram. Be sure to utilize appropriate techniques for each module (eg. creating state

Practical 4: Further Work with VHDL and State Machines

diagrams to describe state behaviour; describing behavioural sequential architectures using algorithms
etc). You can utilize the language templates to assist in the creation.

Simulate and test each of your implemented components using the ISim Simulator.

Create an appropriate user constraints file which would map the implemented system to outputs on the
Spartan 3 development board.

Test your system on the Spartan 3 development board.

Practical 4: Further Work with VHDL and State Machines

Proceed to post-lab exercise.

Practical 4: Further Work with VHDL and State Machines

5.

POST-LAB

A signed plagiarism declaration form must be submitted with your assignment.

Due Date:
Submission
Procedure:
Deliverables:

NA
-

End of Practical 4: Further Work

with VHDL and State Machines