Vivekananda College of Engineering & Technology

[Sponsored by Vivekananda Vidyavardhaka Sangha, Puttur ]

Affiliated to Visvesvaraya Technological University

Approved by AICTE New Delhi & Govt of Karnataka
COURSE LABORATORY MANUAL

TCP03
Rev 1.0
ECE
20/06/2015

1. EXPERIMENT NO:
Date Planned
Date Conducted
Marks
2(a)
10/08/15 04/08/15 30/7/15
2. TITLE: REALIZATION OF HALF/FULL ADDER USING LOGIC GATES.
3. LEARNING OBJECTIVES:
To realize the adder circuits using basic gates and universal gates
To realize full adder using two half adders.
4. AIM:
Realization of half/full adder using logic gates.
5. MATERIAL / EQUIPMENT REQUIRED:
IC 7486, IC 7408, IC 7404, IC 7432, IC 7400, IC7402, IC7411, IC7410, IC7420, IC7427.
Patch Cords & IC Trainer Kit.
6. THEORY :
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and
B, is called a half-adder. Addition will result in two output bits; one of which is the sum bit,
S, and the other is the carry bit, C. The Boolean functions describing the half-adder are:
S =A B,
C = A.B
Full-Adder: The half-adder does not take the carry bit from its previous stage into account.
This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that
adds two data bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean
functions describing the full-adder are:
S = (x y) Cin
C = xy + Cin (x y)
7. PROCEDURE :
Verify the gates.
Make the connections as per the circuit diagram.
Switch on VCC and apply various combinations of input according to truth table.
Note down the output readings for half/full adder sum and the carry bit for different
combinations of inputs.
8.BLOCK DIAGRAM :

i)

HALF ADDER
Using basic and Ex-or gates:

Nehru Nagar, Puttur - 574 203, DK, Karnataka State INDIA.

Phone:+91-8251-235955, 234555 Fax: 236444,

Web: www.vcetputtur.ac.in,

E-Mail: aemc@vcetputtur.ac.in

Vivekananda College of Engineering & Technology

[Sponsored by Vivekananda Vidyavardhaka Sangha, Puttur ]

Affiliated to Visvesvaraya Technological University

Approved by AICTE New Delhi & Govt of Karnataka
COURSE LABORATORY MANUAL

ii)

iii)

TCP03
Rev 1.0
ECE
20/06/2015

Using basic gates:

Using Nand gates:

iv) Using Nor gates

Nehru Nagar, Puttur - 574 203, DK, Karnataka State INDIA.

Phone:+91-8251-235955, 234555 Fax: 236444,

Web: www.vcetputtur.ac.in,

E-Mail: aemc@vcetputtur.ac.in

Vivekananda College of Engineering & Technology

[Sponsored by Vivekananda Vidyavardhaka Sangha, Puttur ]

Affiliated to Visvesvaraya Technological University

Approved by AICTE New Delhi & Govt of Karnataka
COURSE LABORATORY MANUAL

TCP03
Rev 1.0
ECE
20/06/2015

FULL ADDER

i) Using basic gates:

ii)Using Nand gates:

iii)Using Nor gates:

Nehru Nagar, Puttur - 574 203, DK, Karnataka State INDIA.

Phone:+91-8251-235955, 234555 Fax: 236444,

Web: www.vcetputtur.ac.in,

E-Mail: aemc@vcetputtur.ac.in

Vivekananda College of Engineering & Technology

[Sponsored by Vivekananda Vidyavardhaka Sangha, Puttur ]

Affiliated to Visvesvaraya Technological University

Approved by AICTE New Delhi & Govt of Karnataka
COURSE LABORATORY MANUAL

TCP03
Rev 1.0
ECE
20/06/2015

iv) Using 2 half adders:

9. TRUTH TABLE:

Full Adder

Half adder
A
B

10.FORMULA :
Half Adder

Full Adder

s=A B A B
C=AB

S= A B C A B C A B C ABC
COUT=AB+BC+AC

Nehru Nagar, Puttur - 574 203, DK, Karnataka State INDIA.

Phone:+91-8251-235955, 234555 Fax: 236444,

Web: www.vcetputtur.ac.in,

E-Mail: aemc@vcetputtur.ac.in

Vivekananda College of Engineering & Technology

[Sponsored by Vivekananda Vidyavardhaka Sangha, Puttur ]

Affiliated to Visvesvaraya Technological University

Approved by AICTE New Delhi & Govt of Karnataka
COURSE LABORATORY MANUAL

TCP03
Rev 1.0
ECE
20/06/2015

11. GRAPHS / OUTPUTS:

12. RESULTS & ANALYSIS:
The truth table of half adder and full adder circuits is verified.
13. OUTCOMES & CONCLUSIONS:
The half adder and full adder are realized using logic gates and outputs are verified.
14. APPLICATION AREAS:
The ALU (arithmetic logic circuitry) of a computer uses half adder to compute the binary
addition operation on two bits.
Half adder is used to make full adder as a full adder requires 3 inputs, the third input being
an input carry i.e. we will be able to cascade the carry bit from one adder to the other.
Ripple carry adder is possible to create a logical circuit using multiple full adders to add Nbit numbers. Each full adder inputs a C(in), which is the C(out) of the previous adder. This
kind of adder is called RIPPLE CARRY ADDER, since each carry bit "ripples" to the next
full adder. Note that the first full adder (and only the first) may be replaced by a half adder.
Full adder reduces circuit complexity.
15. REMARKS:
FACULTY SIGNATURE

Nehru Nagar, Puttur - 574 203, DK, Karnataka State INDIA.

Phone:+91-8251-235955, 234555 Fax: 236444,

Web: www.vcetputtur.ac.in,

E-Mail: aemc@vcetputtur.ac.in