CMOS Logic Circuits

Dr S. C. Wong

CMOS Logic Circuits

CMOS logic circuits are particularly simple from a

conceptual point of view, although their manufacture
is less economical than that of purely n-MOS or pMOS circuits.
Commercial SSI CMOS circuits include most of the
basic gate and flip-flop functions found in TTL.

the CMOS 74Cxx series is pin-for-pin equivalent to the TTL

74Lxx series.

MSI CMOS circuits include A/D converters,

decoders, multiplexers, and memories.

Review of MOSFET characteristics (1)

Review of MOSFET characteristics (2)

Review of MOSFET characteristics (3)

Review of MOSFET characteristics (4)

Review of MOSFET characteristics (5)

Review of MOSFET characteristics (6)

Simple CMOS inverter (1)

The n-channel and pchannel MOSFETs are both

enhancement-mode
devices.
When the input voltage is
near earth or the supply rail,
one MOSFET is turned on,
while the other is cut off
(having insufficient gatesource voltage to form an
inversion-layer channel).

Simple CMOS inverter (2)

When the input voltage is VCC,
the p-channel MOSFET is
turned off, while the n-channel
MOSFET is turned on.
Advantages (under static
conditions):
Negligible power is consumed
when the logic levels are
constant.
The inputs of subsequent
circuits do not load the output
significantly, because dc
current flow is blocked by the
insulating layer under each
gate electrode.

Physical layout of CMOS inverter

Gate protection

Precautions are needed to

protect MOS devices from
static charges, which are
accumulated on the wellinsulated gate electrode.
All inputs should be
terminated in such a way
that there is a current
discharge path back to the
earth rail. If some gate
inputs are tied to the supply
rail, the supply rail itself
must be provided with a
leakage path to the earth
rail.

CMOS NOR gate (1)

CMOS NOR gate (2)

CMOS NOR gate (3)

CMOS NOR gate (4)

CMOS NAND gate

CMOS logic gate

Switching characteristics and power

dissipation
In general, CMOS circuits are slow compared
with TTL circuits. The main advantage of
CMOS is its low power consumption in
applications where switching transitions occur
infrequently.

Power dissipation
Three causes of power dissipation:
1. Supply current flowing when a gate is in steady
state.

2.

3.

Due to leakage current, is negligible in most applications.

Loss of stored energy (in circuit and device

capacitances) when a change of state occurs.
Supply current pulses (flowing through an nchannel and p-channel path to earth) during a
logical transition.
Note that the power losses (2) and (3) are
proportional to the frequency of switching.

Idealized analysis (1)

Idealized analysis (2)

Idealized analysis (3)

Idealized analysis (4)

Idealized analysis (5)

Noise margins (1)

The high and low output levels of CMOS are

very close to the supply rail and earth. Under
specified conditions, the manufacturer
typically guaranteed that the output voltages
(VOL and VOH) will be within 0.1 V of these
rails.
For 74Cxx series, the dc noise margins are
specified as 1 V each for high- and low-level.

Noise margins (2)

Summary
You should be able to:
Explain the principle of operation of CMOS gates.
Deduce the logical functions performed by gate
circuits.
Devise circuit arrangements for simple CMOS gate
functions.
Account in semi-quantitative terms for the effect of
capacitive loading and power supply variation on
switching speed and power consumption of CMOS
gates.