International Journal of Electrical, Electronics and Data Communication, ISSN: 2320-2084

Volume-3, Issue-5, May-2015

FPGA BASED DIGITAL IC TESTER

1

SANDHYA SINGH TRIPALIYA, 2P.P. BANSOD

1

Student, E&I Department, SGSITS Indore

HOD, Biomedical Engineering Department, SGSITS Indore
Email: stripaliya@yahoo.com, ppbansod43@gmail.com

Abstract This paper describes the implementation of testing of CMOS digital integrated circuits for both functional and
delay fault testing using reconfigurable field programmable gate array, XC3S500E. This FPGA is interfaced with LCD and
hex keypad, has created a very comfortable environment for CMOS digital integrated circuits testing. Tester has generated
and applied test vectors for functional and delay fault testing for particular CMOS ICs and check responses with according to
particular Gate response. After that, it can declare that CMOS ICs have any functional and delay fault or not. This
reconfigurable FPGA based digital IC tester has many advantages over conventional IC testing using automatic test
equipments.
Keywords DUT, FPGA, ATEs.

I. INTRODUCTION
Testing of Digital integrated Circuits using automatic
test equipment [1] is very costly. Instead using
reconfigurable FPGA, can save money as well as by
small change in coding (Verilog or VHDL etc.), it
can be reconfigured for different ICs testing.
Here FPGA based digital IC tester is designed using
verilog hardware description language and this code
is downloaded on XC3S500E which is built on
SPARTAN 3E board.

Fig. 1 List of ICs

The whole assembly i.e. FPGA digital IC tester

consists SPARTAN 3E board, a DUT board, a power
supply circuitry, a hex keypad. In SPARTAN 3E
board, This FPGA based digital IC tester has used
XC3S500E, 16*2 LCD, FX2 connector pin etc.
This digital IC tester sends test vectors to DUT
(Device under test) i.e. CMOS Digital Integrated
Circuits like AND, OR, XOR, XNOR, NAND, NOR
gate ICs and responses of these ICs are captured
and stored into the RAM of SPARTAN 3E board.
Now FPGA compares these captured responses to the
exact responses and declares about functional and
delay fault of IC.

Fig. 2 Block diagram of proposed system

In verilog coding, test program for particular IC test

vectors will be generated and applied to DUT [2, 3].
For functional and delay fault testing [6], different
test vectors are generated and applied to DUT one by
one. For functional testing simply generate test
vectors one by one but for delay testing, there is need
to generate test vector pairs. If responses of DUT are
as expected responses then no fault will be in that
digital CMOS IC otherwise it has.

II. CONCEPT OF FPGA BASED DIGITAL IC

TESTER
This paper proposes a design and implementation of
FPGA [4,5] based Digital IC tester. This uses EDA
tool, verilog code program to configure FPGA
XC3S500E-FG320. Now this FPGA will be able to
test DUTs (CMOS IC-14 pin IC) in terms of
functional and delay fault. In this system, FPGA will
be interfaced with hex keypad. On keypad we can
type IC No., it will be displayed on LCD. According
to the list of IC (fig. 1), select line will be generated
and particular test program will run for functional and
delay fault. Result will be displayed on LCD. The
block diagram for proposed system is shown in fig.2

III. DESIGN STEPS OF FPGA BASED DIGITAL

IC TESTER
The FPGA based development board provides an
inexpensive and reconfigurable on which to design
and implement digital circuits of all kinds [2].The
Xilinx chip XC3S500E Spartan 3E FPGA has 230

FPGA Based Digital IC Tester

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International Journal of Electrical, Electronics and Data Communication, ISSN: 2320-2084

user I/Os, 50MHz clock and 500k gates. The block

diagram in fig.3, which illustrates the whole system.
Fig.4 table shows the list of CMOS Gate ICs which
can be tested on this development board and its input
and output pins and respective test select logic have
been shown.

Volume-3, Issue-5, May-2015

In this verilog coding, mainly three modules have

been made, first for keypad interfacing and respective
display will be in LCD and respective select lines as
per IC will be generated and it will be connected to
module 2 and module 3, second module for
functional testing and third module for delay testing.
The output pins of these three modules will be
multiplexed by MUX (fig.6). All these modules have
been combined, as per mux select lines module 1,
module2 and module3 output line have been available
at the output for LCD display and for DUT board.
Now this can generate and apply test vectors from
these output line to DUT. At a time one type of
testing will be done either functional or delay testing,
this can be achieved by one switch available at input
port of Spartan 3E board. The test vectors for
functional testing are differ from delay testing
thatswhy we are using separate module for testing of
ICs.

Fig. 3 Block diagram of FPGA based development board

Fig.4 shows list of tested ICs and respected pin

numbers.
IV. PROGRAMMING OF FPGA USING
VERILOG
The flow chart of basic programming of FPGA [3]
using verilog code for IC testing is shown in fig.5.
Fig. 6 Modules of verilog program.

When select pins of MUX f0=0, f1=0, then module 1

output lines will be available at output. This module
1, basically displays the IC number on LCD, which
we have typed on keypad, and three select lines for
particular test programs will be generated these will
be connected on module 2 and module 3. When
switch fw=0, then module 2 will be activated and for
interfacing its output lines with LCD and DUT, we
have to give inputs to MUX f0=0, f1=1. This module
2 works for functional testing of CMOS digital IC.
Continuous test vector are applied to DUT and DUT
responses are stored in FPGA RAM
and by
comparing it by actual responses we can judge about
its functional fault and this will be displayed on LCD
at
When fw=1, then module 3 will be activated and for
interfacing its output lines with LCD and DUT, we
have to give inputs to MUX f0=1, f1=0. This module
3 works for delay testing of CMOS digital IC.
Continuous test vector pairs are applied to DUT and
DUT responses are stored in FPGA RAM and by
comparing it by actual responses we can judge about
its delay fault and respective result will be displayed
on LCD.

Fig.5 Flow chart of IC testing

FPGA Based Digital IC Tester

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International Journal of Electrical, Electronics and Data Communication, ISSN: 2320-2084

Volume-3, Issue-5, May-2015

V. SIMULATION RESULTS
The results are from QuestaSim. Using 50 MHz clock
of Spartan 3E board, this tester can measure
functional fault and delay fault. For functional
testing, there is setting in coding that if expected
output of DUT comes within 240 ns range then it can
be captured as without functional fault otherwise
having functional fault. For delay testing if expected
output comes within 100 ns range then it will
considered without delay fault otherwise having delay
fault. These settings of timing can be varied for
different digital ICs.

Fig.10 Simulation result of module 2, functional testing of

CMOS IC CD4081B

Fig.7 shows the simulation results of functional and delay

testing of CMOS IC CD4081B.

Fig.11 Simulation result of module 3, Delay testing of CMOS

IC CD4081B

Fig.8 Simulation result of module 1, using hex keypad

CD4081B has been typed

Fig. 12 Simulation result of combined modules of CMOS IC

CD4081B

CONCLUSION
In this paper it has been described, how FPGA can
be used for functional as well as delay fault of CMOS
digital IC. Test vectors for functional and delay
testing is generated separately. This kind of testing is
very cheap, reconfigurable, time to market feature of
FPGA and useful for both type of testing (functional
and delay fault) and can be explored for other kinds
of fault. This work can be extended for different type
of digital circuits also. Extra user friendly features
can be added in future.

Fig.9 Simulation result of module 2, functional testing of

CMOS IC CD4072B.

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Volume-3, Issue-5, May-2015

[3] A reconfigurable digital IC tester implemented using the

ARM integrator rapid Prototyping System. Fang pang;
Brandon, T.;Cockburn, B; Hume, M. Electrical and
Computer Engineering, 2004,IEEE
[4] The roles on FPGAs in reprogrammable systems, S.
Hauch, in Proceedings of The IEEE, vol. 86, no. 4, April
1998.
[5] A reprogrammable gate array and applications, S.
Trimberger, in Proceedings of The IEEE, vol. 81, no. 7, July
1993.
[6] On delay fault testing in logic circuits, C. J. Lin, S. M.
Reddy IEEE Trans. on Computer-Aided Design, Vol. CAD6, pp. 694-703, September 1987.

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[2] Implementation of FPGA for decision making in portable
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