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Saturday,April14,2012

HierarchicalDesignFlowpart2

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Wehavediscussedinthelastpost(HierarchicalDesignFlow:Part1)thattheimportantstepintheHierarchicalflowis
theSettingblocklevelconstraintsandtheseareof2typesPhysicalConstraintsandTimingConstraints.Related
to Physical Constraints, basic idea is already mentioned in the last post. Now we will discuss the basics of timing
constraints.

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Timing Constraint for Block is equivalent to the Timing Budgeting or say Block timing Budget allocation for
examplethedelayattheinputport/outputportandall.
TimingBudgeting:

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Timing budgeting is an important step in achieving timing closure in a physically hierarchical design. The timing
budgetingdeterminesthecorrespondingtimingboundaryconstraintsforeachblockinadesign.Ifthetimingboundary
constraintsforeachblockaremetwhentheyareimplemented,thetopleveltimingconstraintsaresatisfied.
Tounderstanditclearlyagainconsiderthescenarioofyourhouse.Youwanttoplaceyour
Drawingroomclosetomainentrance(reasonbeingyoudontwantthatanynewpersontravelallthroughthe
bedroomkitchenandthenfinallysitindrawingroom),
TraveltimebetweenKitchenandDiningroomshouldbeaslessaspossible.
Bathroomshouldbeasclosetoyourbedroom(sothatyoushouldnotspendmuchtimebeforegoingtooffice
justintoandfrobetweenbedroomandbathroom.
So,allthesearetimingconstraintsduringthefinalizingoflayoutofyourhouse.ThinkwhatwillhappenifKitchenisin
3rdfloorandDiningroomisingroundfloor.

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Similarly, in the chip designing, while you divide the design into small blocks, you have to take care about timing
between blocks I/O to other blocks I/O, blocks I/O to chip I/O. If a data is required by a blockA for doing some
processingandthisdataisgeneratedbyblockB,soBlockAshouldknowwhenitwillreceivethedatafromtheBlock
B.SinceatthetopleveltheseblocksareBlackBox,soduringtimingbudgetingwehavetodefinetheconstraintat
input of Block A that it will receive the data after X time (this X we have to estimate correctly on the basic of
experienceandknowledgeoftheblock,usuallyweconstraintwithX+xamountwherexisthemarginwearekeeping
incaseofwrongestimation).
HahahahaConfusingIknowYouhavereadaboveparagraph23timestounderstandwhatIamsaying.EvenI
havedoneseveraltimesaftercomposingthis.Butitsokayforthetimebeing.
ThemainpointwhichIamtryingtoclarifyyouisifyouhaveameetingwithyourclientintheeveningat6:00PM
butyoudontknowthetrafficconditiononroad.Soyouwillestimatethetravelingtimeandaddsomemarginwhich
cantakecarethetrafficconditionandall.Similarlywhenyouareprovidingsometimingconstrainttoblock,youadd
somemarginjusttomakesurethatyouwillnotfaceanyprobleminfuture.
Evenifyouarenotclear,justreadnextfewparagraphsandIamsureyouwillgettheclearpicture.

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The blocklevel timing constraints are in the form of one or more logical timing constraint points at the input and
outputportsofblocklevelcircuits.Eachlogicaltimingconstraintpoints
Specifiesaclocksourceusedtoclockdatathroughtheport,
Adelayparameterspecifyingdatapropagationdelaybackwardfromaninputportandforwardfromanoutput
port,
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Andanytimingexceptionassociatedwiththedatapath.
Using the logical timing constraint point, the circuit design system performs independent timing analysis and
optimizationofeachblocklevelcircuit.
Letmeexplainthistimingbudgetingconceptinotherwayalso.
Letussupposethatyouhaveadesignandasperthespecification,dateshouldreachfromportx1tox2within3sec.
Nowintheflatdesignyoucanmeetthistimingveryeasilybecauseyouareawareaboutthenoofcells,typesofcells
andwirelengthbetweenthex1andx2also.Soitsveryeasytoestimatethedelaybetweenx1andx2.

"TimingPaths":Static
TimingAnalysis(STA)
basic(Part1)

2016

Delay"WireLoad
Model":StaticTiming
Analysis(STA)basic
(Part4c)

2013

Delay"Interconnect
DelayModels":Static
TimingAnalysis(STA)
basic(Part4b)

2015
2014

2012

"SetupandHoldTime"
:StaticTimingAnalysis
(STA)basic(Part3a)
"SetupandHoldTime
Violation":Static
TimingAnalysis(STA)
basic(Part3b)
"ExamplesOfSetup
andHoldtime":Static
TimingAnalysis(STA)
basic(Part3c)

Nowcompareitwiththehierarchicaldesign.Youhavefiguredoutthatthereare3blocksinbetweenx1andx2.Now
theblockownersaredifferent,soyouwanttomakesurethateveryonegetsproperinformationbeforedesigningtheir
ownblock.Likehowmuchmaximumdelayshouldbethereforb1/b2/b3(likewegetthespecificationfromx1tox2at
thetoplevel).Soitsourjobtoprovidetheproperspecificationtotheblockowner.IfIwillmissthis,itwillbeanear
toimpossibletasktointegrateitatthetoplevelwithoutanyiteration.So,dividingthisavailable3sectimeintothese3
blocksisknownasTimeBudgetinginthisexample(OnthebigdesignalsothedefinitionissimilarDistributethe
topleveltimingconstrainteffectivelytotheblocklevelisknownasTimeBudgeting.)
Now,randomlyyouhaveassignedthe1secdelaytoeachblock.Butthecelldelay(cellspresentinsidetheblockb1)of
blockb1itselfisexceeding1sec(ifyouwilladdthenetdelayafterlayoutitwillbemuchmorethan1sec),sosuch
type of timing budgeting is known as UnderBudgetedTiming. Similarly, if the cell delay of block b2 is very less
(lets assume 0.2sec), then estimating the 0.8sec for the net delay may be too much.And in such cases this type of
timingbudgetingisknownasOverbudgetedTiming.Soitsveryimportanttoestimatethetimingveryaccurately.

2011
2010
2008

"TimeBorrowing":
StaticTimingAnalysis
(STA)basic(Part2)
EffectofWireLength
OntheSlew:Static
TimingAnalysis(STA)
Basic(Part7a)
EffectofThreshold
voltage:StaticTiming
Analysis(STA)Basic
(Part7c)

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Nowletsassumethatyouhaveestimatedthedelay(timingbudgeting)correctlyforeachblock(e.g1.5sec,0.5sec,1
sec).There is a processing in block b2 on the data which is coming from the block b1, so for that, block b2 should
knowthatwhenitisgoingtoreceivethedata(afterhowmuchtimewithreferencetosystemclockitwillreceivethe
data). Since both the blocks are handling by different person and they are closing their blocks independently, so we
havetodefinefewconstraintsattheinputandoutputportsofeachblockintermsoftimingandall.Theseconstraints
canbewithrespecttoclockordataorboth.
For example, we can define one constraint at the input of block b2 that for all calculation within the block, it can
assumethatdatahasadelayof1.5sec(inPTitwillbelikeset_input_delay).Sothiswillbetheconstraintforthis
blockwithrespecttothisparticulardataandatthisparticularport.
Similarlogicisappliedtoallthehierarchicaldesign.Andsimilartypeoftimingconstraintyouhavetodefineforallthe
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subblocks.MostlytheseconstraintsareintheformofSDC(SynopsysdelayConstraint).Atabareminimum,adesign
willhaveclockconstraints,andinputandoutputdelayconstraints.Asadesigngetsmorecomplicated,youmaytendto
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addexceptionconstraints.However,thefewertheexceptionsthebetterintermsoftoolruntime.Anywaysthedetails
aboutthetimingconstraintsareinthedifferentpost.

Content

WhatshouldberequiredtodoanefficienttimingBudgeting:
AllCellsandblocksshouldbefloorplanned.SothatatleastyoucanfigureoutthelocationoftheI/Opins.If
youcangetagloballyrouteddesign,thenitiswonderful.
TimingConstraintfortoplevelshouldbeavailable.
Ifyouareusinganyhardblock,thetimingconstraints/specificationshouldbeproperlyknown.
Challengesinthetimingbudgeting:
Chiplevelconstraintsmustbemappedcorrectlytoblocklevelconstraints.
For allocating the timing budgeting to all the subblocks, we have to predict reasonable delay for global
interconnects.Whichisdifficultbeforethedesignisphysicallyconstructed.
Becauseofnotabletopredictaccuratedelayofglobalnest,lotsofiterationsarerequiredtoclosethetimingin
thedesign.
Ifyouoverbudgetedanyblock,youarewastingthetimingslack.
Ifyouunderbudgeted,youwillgetnegativeslackmeanstimingviolation.Itmaybepossiblethatunderbudget
of one block is because of overbudgetting the other block. Because at the end timing should be as per
specificationofchip.
Unfortunately,thedelaybudgetingproblemwillonlybecomemoredifficultasmorewiresbecomeglobalwires
whosepintopindelaysarestronglydependentontheiractualimplementationbydetailedroutingtools.
Oncetimingbudgetingisdone,eachandeveryblockactlikeasmallchip/design.Onceeveryblockisdone,theseare
integratedatthetoplevelandthenthetimingoftoplevelisverified.Fortimingverificationatthetoplevelweonly
needthetiminginformationcorrespondingtoeachblock,sowecanignoreotherdetails(whichcancreateaproblemin
termsofhugememoryandruntime).Forthispurpose,weusethetimingmodelscorrespondingtoeachsubblocks.A
timing model contains information about the timing characteristics, but not the logical functionality, of sub
module/blocks.
After generating a timing model of a block, we use that model in place of the original netlist for timing analysis at
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higherlevelsofhierarchy.Thistechniquemakeswholechipanalysisrunmuchfaster.
Another use of timing models is to protect intellectual property. If you supply a chip submodule to a customer for
integrationintothecustomerslargerchip,youcanprovidethetimingmodelwithouttheoriginalnetlist.Thismethod
allowsthecustomertoperformaccuratetiminganalysiswiththesubmodule,withouthavingaccesstothenetlist.
Therearedifferenttypesoftimingmodelswhichwewilldiscussinseparatepost.ButmostpopularareQTM(Quick
TimeModel),ETM(ExtractedTimingModel),ILM(Interfacelogicmodel)andLibertyModel.
Nowinthelast,asyouknowthatthereisnothing100%perfect,HierarchicalFlowalsohavesomelimitations.
LimitationinHierarchicalDesign:
Whenyouplacetheblockintoplevel,theycanactasroutingobstructionandduetowhichitmaybethatyou
havetoroutethewiremorethanyourestimationanditwillcreatetimingviolation.
Netsthatinterconnecttheblockshavetoberoutedthroughchannelsbetweenblocks.Theseroutestendtobe
longandcancausetimingandsignalintegrityproblems.
RoutingCongestioninsomeplaceandsomeplaceisnotutilizedproperly.Soitmayhappenthathierarchical
designrequiresmorechipareathatflatdesign.
TimingofblockI/Ocantbechangedduringtopleveloptimization.soblocksmustbeoptimizedwithagood
I/Obudget.
PredictionofI/Obudgetshouldbeveryaccurate,elsetheremaybealotofiterationsbetweenI/Obudgeting
andclosingthetimingofblock.

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Anonymous November7,2012at3:44PM
Great!
Learnalotfromyourarticles!
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Greatwork..Thanksalotfortheinformation.

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Anonymous April10,2015at7:34PM
Thanksalotforvaluableinformation.....
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KarthikL February24,2016at4:43PM
canyouexplainhowtogenerateclockwhiledoingpracticalwithencountertool?
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KarthikL February24,2016at4:57PM
canyouexplainhowtogenerateclockwhiledoingpracticalwithencountertool?
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