APLAC®

Overview
APLAC high-frequency circuit simulation technology brings the benefits of
harmonic balance (HB) analysis to the design of complex, extremely nonlinear
circuits. Finely tuned and consistently enhanced for more than 15 years, it is
no wonder APLAC technology is used extensively for IC design at Nokia and
many device manufacturers throughout the world. In fact, APLAC has aided
in the design of more than 30 percent of all mobile phone RFICs. This unique
implementation of harmonic balance and transient analysis gives you extremely
fast and exceptionally accurate results using far less computer memory than
traditional microwave harmonic balance techniques.

Features at a glance Circuit Simulation

 Seamless integration within Microwave Office® and Analog Office® design Technology for
environments Highly Nonlinear and
 Harmonic balance simulators for highly nonlinear and complex designs Complex Designs
•  transient-assisted harmonic balance (TAHB)
•  multi-rate harmonic balance (MRHB™)
  Time-domain simulations including frequency-dependent components
  Linear and nonlinear noise analysis We strongly believe APLAC offers one

  Dynamic oscillator analysis of the most advanced analog design

platforms available, and plays a crucial
 Comprehensive set of convergence aids for DC, AC, HB, and transient
role in helping us live up to our ‘right first
simulations
time’ design philosophy.
 Verilog-A model support as well as IBIS model for I/O driver circuits
Erkki kuisma, Fellow
 APLAC modeling language supports user-defined linear and nonlinear models
Nokia
as well as measurements
  Fully exploits the power of multi-core PCs

QPSK receiver analyzed using

APLAC’s MRHB.
 APLAC

What is APLac?
Multi-Domain Analysis APLAC’s multi-domain analysis enables the
simulation of any RF or analog circuit with a selection of analysis
methods, including DC operation point, linear frequency-domain,
time-domain, HB, phase noise, linear/nonlinear noise, and accurate
yield predictions. Each circuit can be analyzed in multiple ways simply
by altering the analysis definitions. Optimization, tuning, and a Monte
Carlo statistical feature (for design yield) are available with every
method. Leveraging AWR’s Unified Data Model™, APLAC HB and
time-domain can be driven from the same schematic, with the same
sources and the same models.

High-Capacity Harmonic Balance and Time-domain Simulators

APLAC’s HB algorithm has been developed to minimize memory
requirements and simulation time while maintaining a high degree of
APLAC oscillator analysis utilizes optimization to find
accuracy. APLAC technology embodies multiple HB engines, including oscillation frequency. Both HB and transient simulation
an enhanced HB method, a transient-assisted HB method (TAHB), results are studied.
and a multi-rate HB method (MRHB). The enhanced HB method
enables simulation of larger circuits faster than traditional microwave
HB techniques. TAHB is for digital divider circuits and accurate
nonlinear phase noise measurements for analog and RF applications.
MRHB is a reformulation of the basic HB technique. It identifies the
harmonic needs of the individual nonlinear components or signal
paths and reduces the harmonic solution matrix accordingly. The
overall effect is several orders of magnitude reduction in memory
requirements by solving only the required harmonics for each
component or signal path.

The APLAC time-domain simulator complements the AWR solver

family with a microwave-compatible transient engine, which provides
several capabilities essential in high-frequency design:
 Fully compatible with all AWR-developed Microwave Office and
Analog Office advanced, distributed RF-elements
 Support for GaAs MESFET transistor models
APLAC usage is fully transparent to the user. Choose
 Scattering parameters accurately simulated in time-domain
the APLAC simulator from the simulator list and run
  PLL macromodel for synthesizer simulations the simulation.
 IBIS model support – that can be combined with advanced board
models – for high-speed digital design

summary
The APLAC engine delivers accurate results in less time for highly
nonlinear and large-scale designs, resulting in increased productivity
and shorter design cycles.

AWR, 1960 East Grand Avenue, Suite 430, El Segundo, CA 90245, USA
Tel: +1 (310) 726-3000 Fax: +1 (310) 726-3005 www.awrcorp.com
Copyright © 2010 AWR Corporation. All rights reserved. AWR and the AWR logo, Microwave Office, Analog
Office and APLAC are registered trademarks and Unified Data Model is trademark of AWR Corporation.

DS-AP-2010.5.7