UNITV: EMBEDDED SYSTEM DESIGN-CASE STUDIES

POWERPC PROCESSOR ARCHITECTURAL ISSUES

PowerPC is a microprocessor architecture that was developed jointly by

Apple,IBM and Motorola alliance,known as AIM.

The Power PC employs reduced instruction-set computing(RISC).
The three developing companies have made the PowerPC architecture an

open standard.
Originally intended for personal computers,PowerPC CPUs have since been

popular as embedded and high-performance processors.

PowerPC is largely based on IBMs earlier POWER instruction set

architecture,and retains a high level of compatibility with it.

The result of these various requirements was the PowerPC (Performance
Computing) specification. The differences between the earlier POWER
instruction set and PowerPC is outlined in Appendix E of the manual for

PowerPC ISA version 2.02

Motorola exited the chip manufacturing business by spinning off its
semiconductor business as an independent company called Freescale
Semiconductor. Around the same time, IBM exited the 32-bit embedded
processor market by selling its line of PowerPC products to Applied Micro
Circuits Corporation (AMCC) and focusing on 64-bit chip designs.

44.1:POWERPC 601 ARCHITECTURE

Fig 44.1: PowerPC 601 architecture

44.2:IMPLEMENTATIONS
Four implementations of the PowerPC architecture were initially announced:

PowerPC 601 - Original PowerPC microprocessor.

PowerPC 603-Low-cost,least powerful and consumes the least amount of

power.
PowerPC 604-Faster,higher performance.
PowerPC 620-The first 64-bit implementation of the PowerPC architecture.
The PowerPC 601 is a high-performance super-scalar processor implementing

3 independent execution

units and 2 register files.

Execution(pipeline processing)units:

Integer unit(IU)or fixed point unit(FXU)

Floating point unit(FPU)
Branch processing unit(BPU)

44.3:DESIGN FEATURES

PowerPC 601
Basic architecture

Load/store

Instruction length

32 bit

Byte/halfword load and store

Yes

Condition codes

Yes

Conditional moves

No

# of Integer registers

32

Integer register size

32/64 bit

# of Floating point registers

32

Floating point register size

64 bit

Floating point format

IEEE 32 bit, 64 bit

Virtual address

52-80 bit

32/64 bit mode bit

Yes

Segmentation

Yes

Page Size

4 Kbytes

Instruction/data cache size

32 Kbytes

Clock speed

50-100 MHz
Table 44.3: Design features of PowerPC 601

44.4:PIPELINE STRUCTURE

Fetch: Up to eight instructions are fetched into an instruction buffer

Dispatch: Instructions are dispatched to either the FXU or FPU

Decode: Instructions are decoded, with the source registers being read, Instructions to
the FXU are decoded together in the dispatch stage.
Execute: This stage exists in the BPU as well as the FXU, where integer instructions
execute and cache lookup and address processing also occur
Execute1: FPU multiplication
Execute2 :FPU addition
Cache :Floating-point operands are sent to the FPU and the integer operands are sent
to the FXU.
Write: Register file write.
44.5:INSTRUCTION QUEUE AND DISPATCH LOGIC

It is fed by eight- word bus from the cache.

During each cycle,the dispatch logic considers the bottom four entries of the
instruction queue
and dispatches upto three instructions.

44.6:BRANCH PROCESSING UNIT

Fig 44.6: Branch processing unit of PowerPC 601

44.7:FLOATING-POINT EXECUTION UNIT

Supports IEEE-754 FP data types for both single and double-precision

floating- point arithmetic operations.

Fig 44.7:Floating point execution unit of PowerPC 601

44.8:CACHE UNIT AND MEMORY MANAGEMENT UNIT

32 Kbytes
8-way associative
Unified(instruction and data)
Capable of performing a complete read-modify-write every cycle.
Performs the virtual to real address translation for load and store instructions.
Acts as a backup for instruction fetch address translations.
Provides support for segment oriented,page oriented and block oriented
translations.

44.9:SEQUENCER UNIT

It is an embedded support processor that assists the core CPU in handling

many of the algorithmic functions of the PowerPC architecture.

It contains:
1K entry microcode ROS(Read-Only-Storage)
8-single word general purpose registers
32 word private RAM
Control logic required to execute the robust 18 bit instruction set.

44.10:COP UNIT

The Common On-chip Processor is the master control logic for the build-in

self-test,debug and test features of the 601 chip.

It contains a linear feedback shift register(LFSR),a multiple input signature

register(MISR) and the control logic required to sequence BIST operations.

It provides the capability to stop and start the internal clocks and to dump the
state of all registers,RAMs and register files on the chip.

POWERPC 601