Beruflich Dokumente
Kultur Dokumente
I.
iL
+ vC LS
iC
LR
CR
L5
L7
C5
C7
INTRODUCTION
Vdc
II.
The active power filter designed consists of a threephase PWM voltage source inverter, which is connected in
series with the ac source impedance and load, through
three single phase transformers (figure 1). A small rate
passive filter to suppress switching ripples is connected
between the transformers and the inverter.
The passive LC filter connected in parallel to the load
is tuned to eliminate the fifth and seventh harmonics. For
the fundamental harmonic, the passive filter also must
supply the reactive power of the load.
In order to avoid the presence of harmonics at the
source current, the active filter is controlled to present zero
impedance at the fundamental frequency and a high
impedance at the frequencies of the load harmonics. To
achieve high impedance at the frequencies of the load
harmonics, the output voltage of the series active filter
must be proportional to the source current harmonics, that
is,
VCH
1086
Vdc
k I SH
i ref
iL
va
vb
v
c
1 1
1
2
1 a
3
1 a
1 0
a vaf1
a 2 0
P
v
v2
Where:
k i i ref k v v ref
vc
1
T
u i dt
T
0'
v : norm of v, defined by v
1
T
v
T
0'
III.
v dt .
v a1
v
a2
1 1
1
1 a
3
2
1 a
1 va
a 2 vb
a v c
10
-10
va1 sent dt
va1 cost dt
Va1f 2
cosM
2
Va1f 2
senM
2
SIMULATION RESULTS
0.2
0.22
0.24
0.26
Time (s)
Figure 2. Load current
0.28
10
0
-10
-20
0.2
0.22
0.24
0.26
0.28
Time (s)
vaf1
1087
0.3
Inverse
Transformation
va1
Fundamental
harmonic
Fortescue
Transformation
rms
va1
vref
KV
Vn
vc
vf
Ki
ia
p(t)
iref
500
10
0
5
0
-5
-10
0.2
-500
0.2
0.22
0.24
0.26
0.28
0.3
0.22
0.24
0.26
Time (s)
0.28
0.3
Figure 7. Voltage in the load side when source voltages have a 25% of
unbalanced factor
Time (s)
Figure 5. Source current when active filter is connected
500
500
0
-500
0.2
0.22
0.24
0.26
0.28
0.3
-500
0.2
Time (s)
0.22
0.24
Time (s)
0.26
0.28
0.3
Figure 8.Voltage in the source side with voltages distorted by 5th harmonic
1088
500
x
x
x
-500
0.2
0.22
0.24
0.26
Time (s)
0.28
0.3
Figure 9.Voltage in the load side when source voltages are distorted
ACKNOWLEDGMENT
C. Suply voltages with symetrical sag
The tests for immunity in presence of sags are
established in IEC 61000. The sag can be of 0.70 or 0.40
p.u. and five cycles long. Figure 10 shows the waveform in
the source side, which presents a sag of 0.40 p.u.
500
REFERENCES
[1]
0
[2]
500 0
0.25
0.35
Time (s)
0.3
0.4
0.45
[3]
0.
[4]
[5]
500
[6]
[7]
[8]
-500
0
0.25
0.3
0.35
Time (s)
0.4
0.5
0.45
[9]
Figure 11. Load source when the source voltage present a sag of
0.40 p.u.
IV.
CONCLUSIONS
1089