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2.Scan:
What is the significance of scan-compression/EDT during ATPG?
To decrease the TDV and TAT
What is the reason for increase in pattern count for compressed mode?
Because the chain lenght is small,more number of chains exist.More number of control bits to
identify faults in EDT.
The actual compression achieved will be less than the specified compression factor.
Why?
Because of extra cycles(initialization cycles) in EDT.
Deciding factors of scan design?
Number of channels on tester, memory available on channel and number of scan pins.
How scan chains are handled from a 3rd party IP in the chip?
By using "add subchain command"
Use of LOCKUP latch?
a) When two clock domains exist , b) When one domain with different edges trigger the flops
,
c) When clock skew is more than half cycle of hold time.
Difference between LOS and LOC?
Look for the basic differences in the guide.Other difference is that in LOS,there is a chance of
testing unrequired functional paths because of last shift is done when SE=1.
Scan considerations required for At-speed test?
a) OCC that supports and generate 2 pulses for capture cycle.
b) Free running functional clocks.
How to avoid hold issues when scan chain is stitched from +ve edge to ve edge flop?
3.MBIST:
Type of faults in memory to be detected?
SAF, AF, Couplinf faults,Bridging faults.
How does a stuck @ fault is tested in memory cell location?
In memories, for example 8x1 RAM, write all 0's in 8 locations,then read 0's from bottom.
If it does not read 0 in that location we can say it is stuck at 1 and there is a failure.
Why BIST is preferred than a logic scan test?Why memories are not considered while in
ATPG?
What is the criterion for clock controllability for Memories during BIST?
Memory clock should be top clock, controller clock and memory clock should be same.
4.ATPG:
How to improve fault coverage or how do you analyze the fault coverage in the initial
runs?
By checking controllability and observability in the design and clearin the DRC's.
What is the timing fixes that we need to do first (shift or capture)?
Shift. If there is any failure in capture we can mask but if shift sims fail we can do nothing.
How a transition fault is detected in ATPG? Explain how launch and capture of a fault is
done and detected?
Initialization
Launch
Capture
Why does an IDDQ pattern take lot of time for test, though pattern count is very small?
5.SIMUALTIONS:
What kind of simulations do we generally need to do?
Chain serial and serial capture.
Why do zero-delay/Unit delay simulations fail though timing simulations are passing?
Simulator issues.
Problems generally encountered during ATPG simulations?
Hold issues.