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ABSTRACT
This paper presents the new technology that extends
todays JTAGs capability from DC domain to both AC
and DC domains. New concept, AC_EXTEST is
introduced to support AC interconnection test and to have
backward compatibility with EXTEST. It leverages
existing application software available within boundaryscan test industry to promote this technology to
manufacturing floor with minimal impact.
Introduction
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30
Device 2 or
Connector
STD 1149.1
capable
Interoperable with Broader Supply Base: ACJTAG should use simple and clear protocol so that
many different devices from different vendors can
support AC-JTAG. At the same time, legacy devices
should work with devices equipped with AC-JTAG.
STD 1149.1
incapable
STD 1149.1
incapable
Definitions
Objectives
System Overview
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Application Link
1149.1
Logical Link
Physical Link
1149.1
101010...
101010...
010101...
010101...
4.1
AC Pattern Generation
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Proceedings of the International Test Conference 2001 (ITC01)
0-7803-7171-2/01 $17.00 2001 IEEE
4.2
AC Pattern Sample
4.2.1
4.2.2
AC EXTEST1
5.1
Initiate
AC_EXTEST Instructio n
Execute
AC_EXTEST Instructio n
Reload
Net Test Data
Transfer
AC_EXTEST Instructio n
Results
Instruction
Evaluate
AC_EXTEST Results
AC Scan Cell
DC Scan Cell
Passing through
RTI
Bypassing
RTI
AC_EXTEST
AC_EXTEST
EXTEST
EXTEST
EXTEST
EXTEST
EXTEST
EXTEST
End
5.2
a)
Both the system output pins and the system input pins
are interconnected and are under the AC_EXTEST
instruction. The test shall work properly regardless of
AC coupling between the interconnections.
b) If there is no AC coupling between two devices, the
system output pin under the EXTEST instruction shall
operate with the system the input pin under the
AC_EXTEST instruction.
c) The system output pins under the AC_EXTEST
instruction shall operate as the EXTEST instruction if
the TAP controller is not in the Run-Test/Idle
controller state.
Link to EXTEST
AC_EXTEST
instruction
should
provide
interoperability with the following test combination of the
conditions:
To next cell
Data from
system logic
From last cell
ShiftDR
AC_Test
AC_Pattern_Clock
or ClockDR
To system pin
0
1
0
1
ck Q
To next cell
0
1
0
1
ck
0
1
D
AC_Sync
ck
0
1
0
1
D
ck
Data to
system
logic
ck
AC_Test_Ran
From last cell
ShiftDR
ClockDR
UpdateDR
DC_Mode
AC_Test_Marker
UpdateDR
AC_Test
DC_Mode
TCK
0
1
Run-Test / Idle
AC Pattern A
=1
AC Pattern A =
0
AC_Sync A
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Proceedings of the International Test Conference 2001 (ITC01)
0-7803-7171-2/01 $17.00 2001 IEEE
6.1
7.1
LVDS Connection
SET
CLR
DATA
Transmit
SET
QB
CLR
3.5mA
S ET
gnd vdd
SE T
CLR
fault injections
Signal before
CAP
Fault Coverage
Signal after
CAP
DATA Receive
gnd vdd
Rt
100Ohm
350mV
CLR
LVDS Line
Receiver
3.5mA
gnd vdd
Recovered
Signal
7.2
AC Coupled Capacitance
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Fault Type
1
2
3
4
5
Open
Open
Open
Open
Short
Short
Short
Short
9
10
11
12
13
14
15
16
Stuck-0
Stuck-1
Stuck-0
Stuck-1
Stuck-0
Stuck-1
Stuck-0
Stuck-1
and
AC
Yes
Yes
Yes
Yes
Yes
Coverage
AC + DC
Yes
Yes
Yes
Yes
Yes
and
Yes
Yes
and
No
Yes
and
No
Yes
Yes/No
Yes/No
Yes
Yes/No
Yes/No
Yes/No
Yes
Yes/No
Yes/No
Yes/No
Yes
Yes/No
Yes/No
Yes/No
Yes
Yes/No
Signal
Positive before CAP
Positive after CAP
Negative before CAP
Negative after CAP
Positive before CAP
Negative after CAP
Positive after CAP
Negative before CAP
Positive before CAP
Positive after CAP
Negative before CAP
Negative after CAP
Positive before CAP
Positive before CAP
Positive after CAP
Positive after CAP
Negative before CAP
Negative before CAP
Negative after CAP
Negative after CAP
Comments
Table 2: Fault injection and coverage for LVDS AC coupled differential lines
7.3
Fault Coverage
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Proceedings of the International Test Conference 2001 (ITC01)
0-7803-7171-2/01 $17.00 2001 IEEE
Acknowledgements
References
Conclusion