Beruflich Dokumente
Kultur Dokumente
MC68HC705P6A
Rev. 2.1
9/2005
freescale.com
This document contains certain information on a new product.Specifications and information herein are subject to change without notice.
Blank
MC68HC705P6A
Advance Information Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com/
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
Revision
Level
November,
2001
N/A
2.0
92
September,
2005
2.1
Description
Page
Number(s)
Throughout
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc., 2005. All rights reserved.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
Revision History
Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter 3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 4 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter 5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 6 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Chapter 7 Serial Input/Output Port (SIOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Chapter 8 Capture/Compare Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Chapter 9 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Chapter 10 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Chapter 11 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Chapter 12 Central Processor Unit (CPU) Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Chapter 13 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chapter 14 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Chapter 15 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Chapter 16 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
List of Chapters
Freescale Semiconductor
Table of Contents
Chapter 1
General Description
1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2.1
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2.2
Ceramic Resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2.3
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.3
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.4
PA0PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.5
PB5/SDO, PB6/SDI, and PB7/SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.6
PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH . . . . . . . . . . . . . . . .
1.3.7
PD5 and PD7/TCAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.8
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.9
IRQ/VPP (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
15
15
15
16
16
16
16
16
16
16
16
17
17
Chapter 2
Memory
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootloader Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Computer Operating Properly (COP) Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
19
19
19
19
24
25
Chapter 3
Operating Modes
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1.2
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2
WAIT Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
27
28
28
28
30
30
30
Table of Contents
Chapter 4
Resets
4.1
4.2
4.3
4.3.1
4.3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
31
32
Chapter 5
Interrupts
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Interrupt Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1
Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3.1
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3.2
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3.3
Output Compare Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3.4
Timer Overflow Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
35
35
35
35
35
35
36
36
Chapter 6
Input/Output Ports
6.1
6.2
6.3
6.4
6.5
6.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Port Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
37
38
38
39
39
Chapter 7
Serial Input/Output Port (SIOP)
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.3.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIOP Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIOP Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
42
42
42
42
43
43
44
44
Freescale Semiconductor
Table of Contents
Chapter 8
Capture/Compare Timer
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.4
8.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer During Wait/Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
46
46
46
46
47
48
49
49
50
50
51
51
Chapter 9
Analog Subsystem
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.4
9.4.1
9.4.2
9.4.3
9.5
9.6
9.7
9.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Voltage (VREFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Conversion Data Register (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Subsystem Operation during Halt/Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Subsystem Operation during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
53
53
53
53
53
53
54
54
54
54
55
56
56
Chapter 10
EPROM
10.1
10.2
10.3
10.4
10.5
10.6
10.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM Programming Register (EPROG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming from an External Memory Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
57
57
57
57
59
59
Table of Contents
Chapter 11
Mask Option Register (MOR)
11.1
11.2
11.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
MOR Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Chapter 12
Central Processor Unit (CPU) Core
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
67
67
68
68
68
68
Chapter 13
Instruction Set
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
13.2.8
13.3
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.4
13.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
71
71
71
71
72
72
72
72
72
73
73
74
75
76
76
77
82
Chapter 14
Electrical Specifications
14.1
14.2
14.3
14.4
14.5
14.6
14.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3-Volt DC Electrical Charactertistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
85
85
85
86
87
88
Freescale Semiconductor
Table of Contents
Chapter 15
Mechanical Specifications
15.1
15.2
15.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Plastic Dual In-Line Package (Case 710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Small Outline Integrated Circuit Package (Case 751F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Chapter 16
Ordering Information
16.1
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11
Table of Contents
Freescale Semiconductor
Chapter 1
General Description
1.1 Introduction
The MC68HC705P6A is an EPROM version of the MC68HC05P6 microcontroller. It is a low-cost
combination of an M68HC05 Family microprocessor with a 4-channel, 8-bit analog-to-digital (A/D)
converter, a 16-bit timer with output compare and input capture, a serial communications port (SIOP), and
a computer operating properly (COP) watchdog timer. The M68HC05 CPU core contains 176 bytes of
RAM, 4672 bytes of user EPROM, 239 bytes of bootloader ROM, and 21 input/output (I/O) pins (20
bidirectional, 1 input-only). This device is available in either a 28-pin plastic dual in-line (PDIP) or a 28-pin
small outline integrated circuit (SOIC) package.
A functional block diagram of the MC68HC705P6A is shown in Figure 1-1.
1.2 Features
Features of the MC68HC705P6A include:
Low cost
M68HC05 core
28-pin SOIC, PDIP, or windowed DIP package
4672 bytes of user EPROM (including 48 bytes of page zero EPROM and 16 bytes of user vectors)
13
General Description
INTERNAL
CPU CLOCK
COP
CPU CONTROL
ALU
RESET
M68HC05 CPU
IRQ/VPP
OSC
16-BIT TIMER
1 INPUT CAPTURE
1 OUTPUT COMPARE
PORT D LOGIC
OSC 1
OSC 2
PD7/TCAP
TCMP
PD5
ACCUM
PROGRAM COUNTER
COND CODE REG
1 1 1H I NZC
PC7/VREFH
PC6/AD0
MUX
A/ D CONVERTER
0 0 0 0 0 0 0 0 1 1 STK PNTR
PORT C
INDEX REG
CPU REGISTERS
PC5/AD1
PC4/AD2
PC3/AD3
PC2
PC1
PC0
PB5/SDO
PB6/SDI
PB7/SCK
PORT B AND
SIOP
REGISTERS
AND LOGIC
PA6
PA5
PORT A
PA7
PA4
PA3
PA2
PA1
PA0
VDD
VSS
Freescale Semiconductor
OSC1
MCU
OSC2
OSC1
MCU
OSC2
4.7 M
UNCONNECTED
EXTERNAL CLOCK
37 pF
(a)
37 pF
Crystal or Ceramic
Resonator Connections
(b)
15
General Description
1.3.2.1 Crystal
The circuit in Figure 1-2(a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. Follow
the crystal manufacturers recommendations, as the crystal parameters determine the external
component values required to provide maximum stability and reliable startup. The load capacitance
values used in the oscillator circuit design should include all stray capacitances. Mount the crystal and
components as close as possible to the pins for startup stabilization and to minimize output distortion.
1.3.2.2 Ceramic Resonator
In cost-sensitive applications, use a ceramic resonator in place of a crystal. Use the circuit in Figure 1-2(a)
for a ceramic resonator and follow the resonator manufacturers recommendations, as the resonator
parameters determine the external component values required for maximum stability and reliable starting.
The load capacitance values used in the oscillator circuit design should include all stray capacitances.
Mount the resonator and components as close as possible to the pins for startup stabilization and to
minimize output distortion.
1.3.2.3 External Clock
An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the
OSC2 input not connected, as shown in Figure 1-2(b).
1.3.3 RESET
Driving this input low will reset the MCU to a known startup state. The RESET pin contains an internal
Schmitt trigger to improve its noise immunity. Refer to Chapter 4 Resets.
1.3.4 PA0PA7
These eight I/O pins comprise port A. The state of any pin is software programmable and all port A lines
are configured as inputs during power-on or reset. Port A has mask-option register enabled interrupt
capability with internal pullup devices selectable for any pin. Refer to Chapter 6 Input/Output Ports.
Freescale Semiconductor
1.3.8 TCMP
This pin is the output from the 16-bit timers output compare function. It is low after reset. Refer to
Chapter 8 Capture/Compare Timer.
17
General Description
Freescale Semiconductor
Chapter 2
Memory
2.1 Introduction
The MC68HC705P6A utilizes 13 address lines to access an internal memory space covering 8 Kbytes.
This memory space is divided into I/O, RAM, ROM, and EPROM areas.
2.5 RAM
The user RAM consists of 176 bytes (including the stack) at locations $0050 through $00FF. The stack
begins at address $00FF. The stack pointer can access 64 bytes of RAM from $00FF to $00C0.
NOTE
Using the stack area for data storage or temporary work locations requires
care to prevent it from being overwritten due to stacking from an interrupt
or subroutine call.
2.6 EPROM/ROM
There are 4608 bytes of user EPROM at locations $0100 through $12FF, plus 48 bytes in user page zero
locations $0020 through $004F, and 16 additional bytes for user vectors at locations $1FF0 through
$1FFF. The bootloader ROM and vectors are at locations $1F01 through $1FEF.
19
Memory
$0000
$001F
$0020
$004F
$0050
$00BF
$00C0
$00FF
$0100
I/O
32 BYTES
USER EPROM
48 BYTES
INTERNAL RAM
176 BYTES
STACK
64 BYTES
0000
0031
0032
0079
0080
4863
4864
$1FEF
$1FF0
$1FFF
$001F
0255
0256
UNIMPLEMENTED
3071 BYTES
$1EFE
$1EFF
$1F00
$1F01
I/O REGISTERS
SEE Figure 2-2
0191
0192
USER EPROM
4608 BYTES
$12FF
$1300
$0000
7934
7935
7936
7937
$1FF0
UNUSED
$1FF1
UNUSED
$1FF2
UNUSED
$1FF3
UNUSED
$1FF4
UNUSED
$1FF5
UNUSED
$1FF6
UNUSED
$1FF7
$1FF8
$1FF9
8175
8176
$1FFA
$1FFB
8191
$1FFC
$1FFD
$1FFE
$1FFF
Note 1. Writing zero to bit 0 of $1FF0 clears the COP watchdog timer. Reading $1FF0 returns user EPROM data.
Freescale Semiconductor
EPROM/ROM
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
UNIMPLEMENTED
$0008
UMIMPLEMENTED
$0009
$000A
$000B
$000C
RESERVED
$000D
UNIMPLEMENTED
$000E
UNIMPLEMENTED
$000F
UNIMPLEMENTED
$0010
UNIMPLEMENTED
$0011
$0012
$0013
$0015
$0016
$0017
$0017
TIMER MSB
$0018
TIMER LSB
$0019
$001A
$001B
$001C
$001D
$001E
RESERVED
$001F
21
Memory
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
Register Name
Port A Data Register
(PORTA)
See page 37.
Port B Data Register
(PORTB)
See page 38.
Port C Data Register
(PORTC)
See page 38.
Port D Data Register
(PORTD)
See page 39.
Port A Data Direction
Register (DDRA)
See page 37.
Port B Data Direction
Register (DDRB)
See page 38.
Port C Data Direction
Register (DDRC)
See page 38.
$0007
$0008
Unimplemented
$0009
Unimplemented
$000A
$000B
$000C
Read:
Write:
Bit 7
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PC2
PC1
PC0
Reset:
Read:
Write:
Unaffected by reset
PB7
PB6
PB5
Reset:
Read:
Write:
PC7
PC6
PC5
PC4
PC3
Unaffected by reset
PD7
Write:
PD5
Reset:
Read:
Unaffected by reset
Reset:
Read:
Unaffected by reset
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB7
DDRB6
DDRB5
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
Reset:
Read:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Write:
Write:
SPE
DDRD5
0
MSTR
Reset:
Read:
SPIF
DCOL
SDR7
SDR6
SDR5
SDR4
SDR3
SSDR2
SDR1
SDR0
Write:
Reset:
Read:
Write:
Reset:
Unaffected by reset
= Unimplemented
= Reserved
U = Undetermined
Freescale Semiconductor
EPROM/ROM
Addr.
Register Name
$000D
$000E
Unimplemented
$000F
Unimplemented
$0010
Unimplemented
$0011
Unimplemented
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
Bit 7
Bit 0
ICIE
OCIE
TOIE
IEDG
OLVL
Reset:
Read:
ICF
OCF
TOF
Read:
Write:
Write:
Reset:
Read:
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
ICRL2
ICRL1
ICRL0
OCRH2
OCRH1
OCRH0
OCRL2
OCRL1
OCRL0
Write:
Reset:
Read:
Unaffected by reset
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
Write:
Reset:
Read:
Write:
Unaffected by reset
OCRH7
OCRH6
OCRH5
Reset:
Read:
OCRH4
OCRH3
Unaffected by reset
OCRL7
OCRL6
OCRL5
TRH7
TRH6
TRH5
TRH4
TRH3
TRH2
TRH1
TRH0
Reset:
Read:
TRL7
TRL6
TRL5
TRL4
TRL3
TRL2
TRL1
TRL0
Reset:
Read:
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
= Reserved
Write:
Reset:
Read:
OCRL4
OCRL3
Unaffected by reset
Write:
Write:
Write:
Reset:
= Unimplemented
U = Undetermined
23
Memory
Addr.
$001B
$001C
$001D
Register Name
Alternate Timer
Register LSB (ATRL)
See page 49.
$001F
Bit 0
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
Reset:
Read:
Reset:
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
CH2
CH1
CH0
Write:
$001E
6
ACRL6
Write:
EPROM Programming
Register (EPROG)
See page 58.
Bit 7
ACRL7
Read:
ELAT
EPGM
Write:
Reset:
Unaffected by reset
Read:
CC
Write:
Reset:
ADRC
ADON
= Reserved
= Unimplemented
U = Undetermined
Bit 7
Bit 0
PA7PU
PA6PU
PA5PU
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
Bit 7
Bit 0
SWAIT
SPR1
SPR0
LSBF
LEVEL
COP
SECURE
0
= Unimplemented
Freescale Semiconductor
Bit 7
Bit 0
Read:
Write:
Reset:
COPR
0
= Unimplemented
25
Memory
Freescale Semiconductor
Chapter 3
Operating Modes
3.1 Introduction
The MC68HC705P6A has two modes of operation that affect the pinout and architecture of the MCU:
user mode and bootloader mode. The user mode is normally used for the application and the bootloader
mode is used for programming the EPROM. The conditions required to enter each mode are shown in
Table 3-1. The mode of operation is determined by the voltages on the IRQ/VPP and PD7/TCAP pins on
the rising edge of the external RESET pin.
Table 3-1. Operating Mode Conditions After Reset
RESET Pin
IRQ/VPP
PD7/TCAP
Mode
VSS to VDD
VSS to VDD
Single chip
VPP
VDD
Bootloader
The mode of operation is also determined whenever the internal computer operating properly (COP)
watchdog timer resets the MCU. When the COP timer expires, the voltage applied to the IRQ/VPP pin
controls the mode of operation while the voltage applied to PD7/TCAP is ignored. The voltage applied to
PD7/TCAP during the last rising edge on RESET is stored in a latch and used to determine the mode of
operation when the COP watchdog timer resets the MCU.
27
Operating Modes
RESET
28
VDD
IRQ/VPP
27
OSC1
PA7
26
OSC2
PA6
25
PD7/TCAP
PA5
24
TCMP
PA4
23
PD5
PA3
22
PC0
PA2
21
PC1
PA1
20
PC2
PA0
10
19
PC3/AD3
SDO/PB5
11
18
PC4/AD2
SDI/PB6
12
17
PC5/AD1
SCK/PB7
13
16
PC6/AD0
VSS
14
15
PC7/VREFH
Freescale Semiconductor
Low-Power Modes
STOP
MOR
SWAIT
BIT SET?
HALT
WAIT
N
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
RESET STARTUP DELAY
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
EXTERNAL
RESET?
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
EXTERNAL
RESET?
IRQ
EXTERNAL
INTERRUPT?
N
IRQ
EXTERNAL
INTERRUPT?
N
N
Y
TIMER
INTERNAL
INTERRUPT?
END
OF STABILIZATION
DELAY?
COP
INTERNAL
RESET?
RESTART
INTERNAL PROCESSOR CLOCK
2.
TIMER
INTERNAL
INTERRUPT?
N
1.
IRQ
EXTERNAL
INTERRUPT?
N
N
Y
EXTERNAL
RESET?
COP
INTERNAL
RESET?
N
29
Operating Modes
Freescale Semiconductor
Chapter 4
Resets
4.1 Introduction
The MCU can be reset from three sources: one external input and two internal reset conditions. The
RESET pin is a Schmitt trigger input as shown in Figure 4-1. The CPU and all peripheral modules will be
reset by the RST signal which is the logical OR of internal reset functions and is clocked by PH1.
RESET
VDD
OSC
DATA
ADDRESS
POWER-ON
RESET
(POR)
COP
WATCHDOG
(COPR)
D
RST
RES
DFF
TO CPU AND
PERIPHERALS
PH1
31
Resets
The POR will generate the RST signal and reset the MCU. If any other reset function is active at the end
of this 4064 internal clock cycle delay, the RST signal will remain active until the other reset condition(s)
end.
$1FF0
Bit 7
Bit 0
0
COPR
Write:
= Unimplemented
Freescale Semiconductor
Chapter 5
Interrupts
5.1 Introduction
The MCU can be interrupted six different ways:
1. Non-maskable software interrupt instruction (SWI)
2. External asynchronous interrupt (IRQ)
3. Input capture interrupt (TIMER)
4. Output compare interrupt (TIMER)
5. Timer overflow interrupt (TIMER)
6. Port A interrupt (if selected via mask option register)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I
bit) to prevent additional interrupts. Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current instruction is completed.
When the current instruction is completed, the processor checks all pending hardware interrupts. If
interrupts are not masked (I bit in the condition code register is clear) and the corresponding interrupt
enable bit is set, the processor proceeds with interrupt processing. Otherwise, the next instruction is
fetched and executed. The SWI is executed the same as any other instruction, regardless of the I-bit state.
When an interrupt is to be processed, the CPU puts the register contents on the stack, sets the I bit in the
CCR, and fetches the address of the corresponding interrupt service routine from the vector table at
locations $1FF8 through $1FFF. If more than one interrupt is pending when the interrupt vector is fetched,
the interrupt with the highest vector location shown in Table 5-1 will be serviced first.
Table 5-1. Vector Addresses for Interrupts and Reset
Register
Flag
Name
N/A
N/A
Interrupts
Reset
CPU
Interrupt
Vector
Address
RESET
$1FFE$1FFF
N/A
N/A
Software
SWI
$1FFC$1FFD
N/A
N/A
External Interrupt
IRQ
$1FFA$1FFB
TSR
ICF
TIMER
$1FF8$1FF9
TSR
OCF
TIMER
$1FF8$1FF9
TSR
TOF
Timer Overflow
TIMER
$1FF8$1FF9
An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI
instruction causes the CPU state to be recovered from the stack and normal processing to resume at the
next instruction that was to be executed when the interrupt took place. Figure 5-1 shows the sequence of
events that occurs during interrupt processing.
33
Interrupts
FROM RESET
IS I BIT
SET?
N
IRQ
INTERRUPT?
CLEAR IRQ
REQUEST
LATCH
N
TIMER
INTERRUPT?
STACK
PC, X, A, CC
SET
I BIT IN CCR
LOAD PC FROM:
SWI: $1FFC, $1FFD
IRQ: $1FFA-$1FFB
TIMER: $1FF8-$1FF9
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
N
RTI
INSTRUCTION?
RESTORE RESISTERS
FROM STACK
CC, A, X, PC
N
EXECUTE INSTRUCTION
Freescale Semiconductor
Interrupt Types
35
Interrupts
Freescale Semiconductor
Chapter 6
Input/Output Ports
6.1 Introduction
In the user mode, 20 bidirectional I/O lines are arranged as two 8-bit I/O ports (ports A and C), one 3-bit
I/O port (port B), and one 1-bit I/O port (port D). These ports are programmable as either inputs or outputs
under software control of the data direction registers (DDRs). Port D also contains one input-only pin.
6.2 Port A
Port A is an 8-bit bidirectional port, which does not share any of its pins with other subsystems (see
Figure 6-1). The port A data register is located at address $0000 and its data direction register (DDR) is
located at address $0004. The contents of the port A data register are indeterminate at initial power up
and must be initialized by user software. Reset does not affect the data registers, but does clear the
DDRs, thereby setting all of the port pins to input mode. Writing a 1 to a DDR bit sets the corresponding
port pin to output mode. Port A has mask option register enabled interrupt capability with an internal pullup
device
NOTE
The keyscan (pullup/interrupt) feature available on port A is NOT available
in the ROM device, MC68HC05P6.
VDD
PULLUP MASK
OPTION REGISTER
READ $0004
WRITE $0004
RESET
(RST)
WRITE $0000
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0000
INTERNAL HC05
DATA BUS
TO IRQ
INTERRUPT SYSTEM
37
Input/Output Ports
6.3 Port B
Port B is a 3-bit bidirectional port which can share pins PB5PB7 with the SIOP communications
subsystem. The port B data register is located at address $0001 and its data direction register (DDR) is
located at address $0005. The contents of the port B data register are indeterminate at initial powerup
and must be initialized by user software. Reset does not affect the data registers, but clears the DDRs,
thereby setting all of the port pins to input mode. Writing a 1 to a DDR bit sets the corresponding port pin
to output mode (see Figure 6-2).
Port B may be used for general I/O applications when the SIOP subsystem is disabled. The SPE bit in
register SPCR is used to enable/disable the SIOP subsystem. When the SIOP subsystem is enabled, port
B registers are still accessible to software. Writing to either of the port B registers while a data transfer is
under way could corrupt the data. See Chapter 7 Serial Input/Output Port (SIOP) for a discussion of the
SIOP subsystem.
READ $0005
WRITE $0005
RESET
(RST)
WRITE $0001
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0001
INTERNAL HC05
DATA BUS
6.4 Port C
Port C is an 8-bit bidirectional port which can share pins PC3PC7 with the A/D subsystem. The port C
data register is located at address $0002 and its data direction register (DDR) is located at address
$0006. The contents of the port C data register are indeterminate at initial powerup and must be initialized
by user software. Reset does not affect the data registers, but clears the DDRs, thereby setting all of the
port pins to input mode. Writing a 1 to a DDR bit sets the corresponding port pin to output mode (see
Figure 6-3).
Port C may be used for general I/O applications when the A/D subsystem is disabled. The ADON bit in
register ADSC is used to enable/disable the A/D subsystem. Care must be exercised when using pins
PC0PC2 while the A/D subsystem is enabled. Accidental changes to bits that affect pins PC3PC7 in
the data or DDR registers will produce unpredictable results in the A/D subsystem. See Chapter 9 Analog
Subsystem.
Freescale Semiconductor
Port D
READ $0006
WRITE $0006
RESET
(RST)
DATA DIRECTION
REGISTER BIT
WRITE $0002
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0002
INTERNAL HC05
DATA BUS
6.5 Port D
Port D is a 2-bit port with one bidirectional pin (PD5) and one input-only pin (PD7). Pin PD7 is shared with
the 16-bit timer. The port D data register is located at address $0003 and its data direction register (DDR)
is located at address $0007. The contents of the port D data register are indeterminate at initial powerup
and must be initialized by user software. Reset does not affect the data registers, but clears the DDRs,
thereby setting PD5 to input mode. Writing a 1 to DDR bit 5 sets PD5 to output mode (see Figure 6-4).
Port D may be used for general I/O applications regardless of the state of the 16-bit timer. Since PD7 is
an input-only line, its state can be read from the port D data register at any time.
READ $0007
WRITE $0007
RESET
(RST)
DATA DIRECTION
REGISTER BIT
WRITE $0003
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0003
INTERNAL HC05
DATA BUS
39
Input/Output Ports
Accesses to
DDRA @ $0004
Accesses to Data
Register @ $0000
Read/Write
Read
Write
IN, Hi-Z
DDRA0DDRA7
I/O Pin
See Note
OUT
DDRA0DDRA7
PA0PA7
PA0PA7
Accesses to
DDRB @ $0005
Accesses to Data
Register @ $0001
Read/Write
Read
Write
IN, Hi-Z
DDRB5DDRB7
I/O Pin
See Note
OUT
DDRB5DDRB7
PB5PB7
PB5PB7
Accesses to
DDRC @ $0006
Accesses to Data
Register @ $0002
Read/Write
Read
Write
IN, Hi-Z
DDRC0DDRC7
I/O Pin
See Note
OUT
DDRC0DDRC7
PC0PC7
PC0PC7
Accesses to
DDRD @ $0007
Accesses to Data
Register @ $0003
Read/Write
Read
Write
IN, Hi-Z
DDRD5
I/O Pin
See Note 1
OUT
DDRD5
PD5
PD5
Notes:
1. Does not affect input, but stored to data register
2. PD7 is input only
NOTE
To avoid generating a glitch on an I/O port pin, data should be written to the
I/O port data register before writing a logic 1 to the corresponding data
direction register.
At power-on or reset, all DDRs are cleared, which configures all port pins as inputs. The DDRs are
capable of being written to or read by the processor. During the programmed output state, a read of the
data register will actually read the value of the output data latch and not the level on the I/O port pin.
Freescale Semiconductor
Chapter 7
Serial Input/Output Port (SIOP)
7.1 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to provide efficient serial
communications between peripheral devices or other MCUs. The SIOP is implemented as a 3-wire
master/slave system with serial clock (SCK), serial data input (SDI), and serial data output (SDO). A block
diagram of the SIOP is shown in Figure 7-1. A mask programmable option determines whether the SIOP
is MSB or LSB first.
The SIOP subsystem shares its input/output pins with port B. When the SIOP is enabled (SPE bit set in
register SCR), port B DDR and data registers are modified by the SIOP. Although port B DDR and data
registers can be altered by application software, these actions could affect the transmitted or received
data.
SPE
76 54 3210
7 6 54 3210
BAUD
CONTROL
STATUS
RATE
REGISTER
$0A
GENERATOR
76543210
8-BIT
SDO
SHIFT
REGISTER
$0B
REGISTER
$0C
I/O
SDO/PB5
CONTROL
SDI
LOGIC
SCK
SDI/PB6
SCK/PB7
INTERNAL
CPU CLOCK
41
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 6
BIT 7
SDO
SCK
100 ns
100 ns
SDI
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
Freescale Semiconductor
SIOP Registers
$000A
Bit 7
Read:
Write:
Reset:
6
SPE
0
5
0
0
4
MSTR
0
Bit 0
= Unimplemented
43
$000B
Bit 7
Bit 0
SPIF
DCOL
Write:
Reset:
= Unimplemented
$000C
Bit 7
Bit 0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Unaffected by reset
Freescale Semiconductor
Chapter 8
Capture/Compare Timer
8.1 Introduction
This section describes the operation of the 16-bit capture/compare timer. Figure 8-1 shows the structure
of the capture/compare subsystem.
INTERNAL BUS
HIGH LOW
BYTE BYTE
INTERNAL
PROCESSOR
CLOCK
8-BIT
BUFFER
$16
$17
OUTPUT
COMPARE
REGISTER
HIGH
BYTE
16-BIT FREE
RUNNING
COUNTER
LOW
BYTE
$18
$19
HIGH LOW
BYTE BYTE
INPUT
$14
CAPTURE $15
REGISTER
COUNTER $1A
ALTERNATE $1B
REGISTER
OUTPUT
COMPARE
CIRCUIT
TIMER
STATUS ICF OCF TOF $13
REG.
OVERFLOW
DETECT
CIRCUIT
EDGE
DETECT
CIRCUIT
OUTPUT
LEVEL
REG.
D Q
CLK
C
TIMER
CONTROLRESET
ICIE OCIE TOIE IEDG OLVL REG.
$12
INTERRUPT CIRCUIT
OUTPUT
LEVEL
(TCMP)
EDGE
INPUT
(TCAP)
45
Capture/Compare Timer
Freescale Semiconductor
$0012
Bit 7
ICIE
OCIE
TOIE
= Unimplemented
Bit 0
IEDG
OLVL
U = Undetermined
47
Capture/Compare Timer
$0013
Bit 7
Bit 0
ICF
OCF
TOF
Write:
Reset:
= Unimplemented
U = Undetermined
Freescale Semiconductor
TRH $0018
Bit 7
Bit 0
TRH7
TRH6
TRH5
TRH4
TRH3
TRH2
TRH1
TRH0
Bit 7
Bit 0
Write
Reset:
Address:
TRL $0019
Write:
Reset:
= Unimplemented
ATRH $001A
Bit 7
Bit 0
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
Bit 7
Bit 0
Write:
Reset:
Address:
ATRL $001B
Write:
Reset:
= Unimplemented
49
Capture/Compare Timer
ICRH $0014
Bit 7
Bit 0
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
Bit 0
Write:
Unaffected by reset
Address:
ICRL $0015
Bit 7
Write:
Unaffected by reset
= Unimplemented
OCRH $0016
Bit 7
Bit 0
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
Bit 0
Unaffected by reset
Address:
OCRL $0017
Bit 7
Read:
Unaffected by reset
Freescale Semiconductor
To prevent OCF from being set between the time it is read and the time the output compare registers are
updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
51
Capture/Compare Timer
Freescale Semiconductor
Chapter 9
Analog Subsystem
9.1 Introduction
The MC68HC705P6A includes a 4-channel, multiplexed input, 8-bit, successive approximation
analog-to-digital (A/D) converter. The A/D subsystem shares its inputs with port C pins PC3PC7.
53
Analog Subsystem
CC
Write:
Reset:
ADRC
ADON
Bit 0
CH2
CH1
CH0
= Unimplemented
Freescale Semiconductor
Signal
(VREFH + VSS)/2
VSS
Bit 7
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Unaffected by reset
= Unimplemented
55
Analog Subsystem
Freescale Semiconductor
Chapter 10
EPROM
10.1 Introduction
The user EPROM consists of 48 bytes of user page zero EPROM from $0020 to $004F, 4608 bytes of
user EPROM from $0100 to $12FF, the two MOR reset values located at $1EFF and $1F00, and 16 bytes
of user vectors EPROM from $1FF0 to $1FFF. The bootloader ROM and vectors are located from $1F01
to $1FEF.
57
EPROM
Address $001C
Read:
Bit 7
Write:
Reset:
2
ELAT
0
1
0
Bit 0
EPGM
= Unimplemented
EPROG
DATA
EPROM
EPGM
ORG
A6 02
B7 1C
A6 55
C7 07 00
10 1C
AD 03
3F 1C
81
EQU $1C
EQU $55
EQU $700
EQU $00
$D0
LDA #$04
STA EPROG
LDA #DATA
STA EPROM
BSET EPGM, EPROG
BSR DELAY
CLR EPROG
RTS
PROGRAMMING REG
DATA VALUE
A SAMPLE EPROM ADX
EPGM BIT IN EPROG REG
SET LAT BIT IN EPROG
DATA BYTE
WRITE IT TO EPROM LOC
TURN ON PGM VOLTAGE
WAIT 4 ms MINIMUM
CLR LAT AND PGM BITS
Freescale Semiconductor
EPROM Bootloader
PC4
PC3
Mode
Program/verify
Verify only
59
EPROM
PROGRAMMING?
PROGRAMMING?
Y
OPEN PROGRAM SWITCH
VERIFYING?
VERIFYING?
Y
OPEN VERIFY SWITCH
IS VERIFY
LED LIT?
VERIFICATION FAILED
VERIFICATION COMPLETE
TURN VDD ON
CLOSE RESET SWITCH
TURN VPP ON
TURN OFF VPP
OPEN RESET SWITCH
TURN OFF VDD
REMOVE DEVICES
Freescale Semiconductor
DD
MC68HC705P6A
VPP
IRQ/VPP
10 k
2764
PD7/TCAP
MC74HC4040
VDD
OSC1
PGM
2 MHz
OSC2
20 pF
10 M
20 pF
VDD
10 k
RESET
RESET
PB5
A12
PA7
D7
PA6
D6
PA5
D5
PA4
D4
PA3
D3
PA2
D2
PA1
D1
PA0
D0
1 F
VDD
CE
A11
Q12
A10
Q11
A9
Q10
A8
Q9
A7
Q8
A6
Q7
A5
Q6
A4
Q5
A3
Q4
A2
Q3
A1
Q2
A0
Q1
OE
V
RST
DD
CLK
10 k
PC6
PC1
PROG
PB7
PC2
330
DD
10 k
VERF
DD
10 k
PGM
PB6
PC3
330
PC5
VFY
PC4
V = 5.0 V
DD
V = 16.5 V
PP
61
EPROM
Freescale Semiconductor
Chapter 11
Mask Option Register (MOR)
11.1 Introduction
The mask option register (MOR) contains two bytes of EPROM used to enable or disable each of the
features controlled by mask options on the MC68HC05P6 (a ROM version of the MC68HC705P6A).
The seven programmable options on the MC68HC705P6A are:
1. COP watchdog timer (enable or disable)
2. IRQ triggering (edge- or edge- and level-sensitive)
3. SIOP data bit order (most significant bit or least significant bit first)
4. SIOP clock rate (OSC divided by 8, 16, 32, or 64)
5. Stop instruction mode (stop mode or halt mode)
6. Secure EPROM from external reading
7. Keyscan interrupt/pullups on PA0PA7
Bit 7
Bit 0
PA7PU
PA6PU
PA5PU
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
Bit 0
SWAIT
SPR1
SPR0
LSBF
LEVEL
COP
Address: $1F00
Bit 7
Read:
Write:
Erased State:
SECURE
0
= Unimplemented
63
SPR0
fosc 64
fosc 32
fosc 16
fosc 8
1. No security feature is absolutely secure. However, Freescales strategy is to make reading or copying the EPROM/OTPROM
difficult for unauthorized users.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
64
Freescale Semiconductor
MOR Programming
EPROG
DATA2
DATA1
MOR2
MOR1
EPGM
00E0
00E0
00E2
00E4
00E6
00E9
00EB
00ED
00EF
A6
B7
A6
C7
12
AD
3F
81
04
1C
FF
1E FF
1C
03
1C
EQU
EQU
EQU
EQU
EQU
EQU
$1C
$FF
#23
$1EFF
$1F00
$00
ORG
$E0
LDA
STA
LDA
STA
BSET
BSR
CLR
RTS
#$04
EPROG
#DATA2
MOR2
EPGM,EPROG
DELAY
EPROG
PROGRAMMING REG
SAMPLE MOR VALUES
MOPR ADDRESSES
EPGM BIT IN EPROG REG
65
Freescale Semiconductor
Chapter 12
Central Processor Unit (CPU) Core
12.1 Introduction
The MC68HC705P6A has an 8-K memory map. Therefore, it uses only the lower 13 bits of the address
bus. In the following discussion, the upper three bits of the address bus can be ignored. Also, the STOP
instruction can be modified to place the MCU in either the normal stop mode or the halt mode by means
of a MOR bit. All other instructions and registers behave as described in this section.
12.2 Registers
The MCU contains five registers which are hard-wired within the CPU and are not part of the memory
map. These five registers are shown in Figure 12-1 and are described in the following paragraphs.
7
15
14
13
12
11
10
ACCUMULATOR
INDEX REGISTER
STACK POINTER
SP
PROGRAM COUNTER
PC
CC
12.2.1 Accumulator
The accumulator is a general-purpose 8-bit register as shown in Figure 12-1. The CPU uses the
accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The
accumulator is unaffected by a reset of the device.
67
Freescale Semiconductor
Registers
69
Freescale Semiconductor
Chapter 13
Instruction Set
13.1 Introduction
The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include
all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X).
The high-order product is stored in the index register, and the low-order product is stored in the
accumulator.
13.2.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP).
Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
13.2.2 Immediate
Immediate instructions are those that contain a value to be used in an operation with the value in the
accumulator or index register. Immediate instructions require no operand address and are two bytes long.
The opcode is the first byte, and the immediate data value is the second byte.
13.2.3 Direct
Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the
opcode, and the second is the low byte of the operand address. In direct addressing, the CPU
automatically uses $00 as the high byte of the operand address.
71
Instruction Set
13.2.4 Extended
Extended instructions use three bytes and can access any address in memory. The first byte is the
opcode; the second and third bytes are the high and low bytes of the operand address.
When using the Freescale assembler, the programmer does not need to specify whether an instruction is
direct or extended. The assembler automatically selects the shortest form of the instruction.
13.2.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the
effective branch destination by adding the signed byte following the opcode to the contents of the program
counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed,
twos complement byte that gives a branching range of 128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Freescale assembler, the programmer does not need to calculate the offset, because the
assembler determines the proper offset and verifies that it is within the span of the branch.
Freescale Semiconductor
Instruction Types
Mnemonic
ADC
ADD
AND
BIT
Compare Accumulator
CMP
CPX
EOR
LDA
LDX
Multiply
MUL
ORA
SBC
STA
STX
SUB
73
Instruction Set
Mnemonic
ASL
ASR
Bit Clear
BCLR(1)
Bit Set
BSET(1)
Clear Register
CLR
COM
Decrement
DEC
Increment
INC
LSL
LSR
NEG
ROL
ROR
TST(2)
Freescale Semiconductor
Instruction Types
Mnemonic
BCC
BCS
Branch if Equal
BEQ
BHCC
BHCS
Branch if Higher
BHI
BHS
BIH
BIL
Branch if Lower
BLO
BLS
BMC
Branch if Minus
BMI
BMS
BNE
Branch if Plus
BPL
Branch Always
BRA
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
75
Instruction Set
Mnemonic
BCLR
BRCLR
BRSET
Bit Set
BSET
Mnemonic
CLC
CLI
No Operation
NOP
RSP
RTI
RTS
SEC
SEI
STOP
Software Interrupt
SWI
TAX
TXA
WAIT
Freescale Semiconductor
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
IMM
DIR
EXT
IX2
IX1
IX
2
A9 ii
B9 dd 3
C9 hh ll 4
D9 ee ff 5
4
E9 ff
3
F9
IMM
DIR
EXT
IX2
IX1
IX
2
AB ii
BB dd 3
CB hh ll 4
DB ee ff 5
4
EB ff
3
FB
IMM
DIR
EXT
IX2
IX1
IX
2
A4 ii
B4 dd 3
C4 hh ll 4
D4 ee ff 5
4
E4 ff
3
F4
38
48
58
68
78
dd
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
Effect
on CCR
Description
H I N Z C
A (A) + (M)
A (A) (M)
Logical AND
0
b7
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
BCC rel
b0
C
b7
b0
PC (PC) + 2 + rel ? C = 0
ff
5
3
3
6
5
5
3
3
6
5
24
rr
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC (PC) + 2 + rel ? C = 1
REL
25
rr
Mn 0
ff
Cycles
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Address
Mode
Source
Form
Operand
BCLR n opr
Clear Bit n
BCS rel
BEQ rel
Branch if Equal
PC (PC) + 2 + rel ? Z = 1
REL
27
rr
BHCC rel
PC (PC) + 2 + rel ? H = 0
REL
28
rr
BHCS rel
PC (PC) + 2 + rel ? H = 1
REL
29
rr
BHI rel
Branch if Higher
PC (PC) + 2 + rel ? C Z = 0
REL
22
rr
BHS rel
REL
24
rr
PC (PC) + 2 + rel ? C = 0
77
Instruction Set
Address
Mode
Opcode
Operand
Cycles
BIH rel
REL
2F
rr
BIL rel
REL
2E
rr
A5
B5
C5
D5
E5
F5
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
Source
Form
Operation
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BLO rel
BLS rel
Description
Effect
on CCR
H I N Z C
IMM
DIR
EXT
IX2
IX1
IX
(A) (M)
PC (PC) + 2 + rel ? C = 1
REL
25
rr
PC (PC) + 2 + rel ? C Z = 1
REL
23
rr
BMC rel
PC (PC) + 2 + rel ? I = 0
REL
2C
rr
BMI rel
Branch if Minus
PC (PC) + 2 + rel ? N = 1
REL
2B
rr
BMS rel
PC (PC) + 2 + rel ? I = 1
REL
2D
rr
BNE rel
PC (PC) + 2 + rel ? Z = 0
REL
26
rr
BPL rel
Branch if Plus
PC (PC) + 2 + rel ? N = 0
REL
2A
rr
BRA rel
Branch Always
PC (PC) + 2 + rel ? 1 = 1
REL
20
rr
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN rel
PC (PC) + 2 + rel ? 1 = 0
Branch Never
BSET n opr
PC (PC) + 2 + rel ? Mn = 0
Set Bit n
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
21
rr
PC (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
REL
AD
rr
BSR rel
Branch to Subroutine
CLC
C0
INH
98
CLI
I0
INH
9A
Freescale Semiconductor
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
dd
IMM
DIR
EXT
IX2
IX1
IX
2
A1 ii
B1 dd 3
C1 hh ll 4
D1 ee ff 5
4
E1 ff
3
F1
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
IMM
DIR
EXT
IX2
IX1
IX
2
A3 ii
B3 dd 3
C3 hh ll 4
D3 ee ff 5
4
E3 ff
3
F3
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
IMM
DIR
EXT
IX2
IX1
IX
2
A8 ii
B8 dd 3
C8 hh ll 4
D8 ee ff 5
4
E8 ff
3
F8
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
DIR
EXT
IX2
IX1
IX
BD dd 5
CD hh ll 6
DD ee ff 7
6
ED ff
5
FD
Effect
on CCR
H I N Z C
M $00
A $00
X $00
M $00
M $00
Clear Byte
(A) (M)
(X) (M)
M (M) 1
A (A) 1
X (X) 1
M (M) 1
M (M) 1
Decrement Byte
A (A) (M)
M (M) + 1
A (A) + 1
X (X) + 1
M (M) + 1
M (M) + 1
Increment Byte
Unconditional Jump
PC Jump Address
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3)
Push (PCL); SP (SP) 1
Push (PCH); SP (SP) 1
PC Effective Address
0 1
ff
dd
ff
dd
ff
dd
ff
Cycles
Description
Operand
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Operation
Opcode
Source
Form
Address
Mode
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
79
Instruction Set
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
2
A6 ii
B6 dd 3
C6 hh ll 4
D6 ee ff 5
4
E6 ff
3
F6
A (M)
IMM
DIR
EXT
IX2
IX1
IX
2
AE ii
BE dd 3
CE hh ll 4
DE ee ff 5
4
EE ff
3
FE
X (M)
38
48
58
68
78
dd
DIR
INH
INH
IX1
IX
0
b7
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
MUL
Unsigned Multiply
0 0
INH
42
DIR
INH
INH
IX1
IX
30
40
50
60
70
INH
9D
b0
C
b7
X : A (X) (A)
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NOP
No Operation
0
b0
A (A) (M)
C
b7
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
RSP
dd
ff
39
49
59
69
79
dd
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
INH
9C
5
3
3
6
5
5
3
3
6
5
2
AA
BA
CA
DA
EA
FA
5
3
3
6
5
1
1
IMM
DIR
EXT
IX2
IX1
IX
b0
SP $00FF
ff
ii
dd
hh ll
ee ff
ff
b0
C
b7
ff
Cycles
Description
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
IMM
DIR
EXT
IX2
IX1
IX
Effect
on CCR
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Opcode
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
Operation
Address
Mode
Source
Form
Operand
ff
ff
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
2
Freescale Semiconductor
INH
80
INH
81
IMM
DIR
EXT
IX2
IX1
IX
2
A2 ii
B2 dd 3
C2 hh ll 4
D2 ee ff 5
4
E2 ff
3
F2
Description
RTI
RTS
Effect
on CCR
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SEC
C1
INH
99
SEI
I1
INH
9B
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STOP
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SWI
Software Interrupt
TAX
TST opr
TSTA
TSTX
TST opr,X
TST ,X
M (A)
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
INH
8E
Cycles
H I N Z C
Opcode
Operation
Address
Mode
Source
Form
Operand
2
2
dd
hh ll
ee ff
ff
4
5
6
5
4
2
dd
hh ll
ee ff
ff
4
5
6
5
4
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
IMM
DIR
EXT
IX2
IX1
IX
2
A0 ii
B0 dd 3
C0 hh ll 4
D0 ee ff 5
4
E0 ff
3
F0
INH
83
1
0
INH
97
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
M (X)
A (A) (M)
X (A)
(M) $00
dd
ff
4
3
3
5
4
81
Instruction Set
WAIT
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
A (X)
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
()
( )
?
:
H I N Z C
INH
9F
INH
8F
Effect
on CCR
Cycles
Description
Opcode
TXA
Operation
Address
Mode
Source
Form
Operand
Freescale Semiconductor
Freescale Semiconductor
0
1
2
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
3
4
5
6
7
8
9
A
B
C
D
E
F
Branch
REL
DIR
Read-Modify-Write
INH
INH
IX1
4
IX
7
5
5
3
5
3
3
6
5
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BCLR0
BRN
3
DIR 2
DIR 2
REL
1
5
5
3
11
BRSET1
BSET1
BHI
MUL
3
DIR 2
DIR 2
REL
1
INH
5
5
3
5
3
3
6
5
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BCLR5
BMI
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BCLR6
BMS
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BSET7
BIL
3
DIR 2
DIR 2
REL
1
5
6
3
3
5
3
5
5
CLR
CLR
CLRX
CLRA
CLR
BIH
BCLR7
BRCLR7
IX 1
IX1 1
INH 2
INH 1
DIR 1
REL 2
DIR 2
3
DIR 2
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
9
RTI
INH
6
RTS
INH
2
2
2
10
SWI
INH
2
2
2
2
1
1
1
1
1
1
1
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
2
STOP
INH
2
2
TXA
WAIT
INH
INH 1
IMM
DIR
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
MSB
LSB
Register/Memory
EXT
IX2
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
C
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
D
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
IX1
IX
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
MSB
LSB
3
SUB
IX
3
CMP
IX
3
SBC
IX
3
CPX
2
3
IX
3
AND
IX
3
BIT
IX
3
LDA
IX
4
STA
IX
3
EOR
IX
3
ADC
IX
3
ORA
IX
3
ADD
IX
2
JMP
IX
5
JSR
IX
3
LDX
D
E
IX
4
STX
IX
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
83
Opcode Map
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
Control
INH
INH
Instruction Set
Freescale Semiconductor
Chapter 14
Electrical Specifications
14.1 Introduction
This section contains the electrical and timing specifications.
Symbol
Value
Unit
Supply voltage
VDD
0.3 to +7.0
Input voltage
VIn
VIn
25
mA
Tstg
65 to +150
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to 14.5 5.0-Volt DC Electrical Characteristics and
14.6 3.3-Volt DC Electrical Charactertistics for guaranteed operating
conditions.
Symbol
Value
TL to TH
0 to +70
40 to +85
Unit
Symbol
Value
Unit
JA
60
60
C/W
TA
85
Electrical Specifications
Symbol
Min
Typ(2)
Max
Unit
VOL
VOH
VDD 0.1
0.1
VOH
VDD 0.8
VDD 0.8
VOL
0.4
0.4
VIH
0.7 x VDD
VDD
VIL
VSS
0.2 x VDD
4.0
2.0
1.3
7.0
4.0
2.0
mA
mA
mA
30
50
100
A
A
A
Output voltage
ILoad = 10.0 A
ILoad = 10.0 A
Output high voltage
(ILoad = 0.8 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
(ILoad = 5.0 mA) PC0:1
Output low voltage
(ILoad = 1.6 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
(ILoad = 10 mA) PC0:1
IDD
IIL
10.0
IOZ
1.0
Input current
RESET, IRQ/VPP, OSC1, PD7/TCAP
IIn
1.0
IIn
175
385
750
COut
CIn
12
8
pF
Capaitance
Ports (as input or output)
RESET, IRQ/VPP
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = 40C to +85C, unless otherwise noted. All values shown refelect pre-silicon
estimates.
2. Typical values at midpoint of voltage range, 25C only.
3. Run (Operating) IDD, Wait IDD: To be measured using external square wave clock source (fosc = 4.2 MHz), all inputs 0.2 V
from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD 0.2 V.
5. Wait IDD will be affected linearly by the OSC2 capacitance.
6. Stop IDD to be measured with OSC1 = VSS.
Freescale Semiconductor
Symbol
Min
Typ(2)
Max
Unit
VOL
VOH
VDD 0.1
0.1
VOH
VDD 0.3
VDD 0.3
VOL
0.3
0.3
VIH
0.7 x VDD
VDD
VIL
VSS
0.2 x VDD
1.8
1.0
0.6
2.5
1.4
1.0
mA
mA
mA
20
40
50
A
A
A
Output voltage
ILoad = 10.0 A
ILoad = 10.0 A
Output high voltage
(ILoad = 0.2 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
(ILoad = 1.2 mA) PC0:1
Output low voltage
(ILoad = 0.4 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
(ILoad = 2.5 mA) PC0:1
IDD
IIL
10.0
IOZ
1.0
Input current
RESET, IRQ/VPP, OSC1, PD7/TCAP
IIn
1.0
IIn
75
175
350
COut
CIn
12
8
pF
Capaitance
Ports (as input or output)
RESET, IRQ/VPP
1. VDD = 3.3 Vdc 0.3 Vdc, VSS = 0 Vdc, TA = 40C to +85C, unless otherwise noted. All values shown reflect pre-silicon
estimates.
2. Typical values at midpoint of voltage range, 25C only.
3. Run (Operating) IDD, Wait IDD: To be measured using external square wave clock source (fosc = 4.2 MHz), all inputs 0.2 V
from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD 0.2 V.
5. Wait IDD will be affected linearly by the OSC2 capacitance.
6. Stop IDD to be measured with OSC1 = VSS.
87
Electrical Specifications
Min
Max
Unit
Resolution
Bits
Absolute accuacy
(VDD VREFH > 4.0)
1 1/2
LSB
VSS
VSS
VREFH
VDD
Input leakage
AD0, AD1, AD2, AD3
VREFH
1
1
Conversion time
MCU external oscillator
Internal RC oscillator
32
32
tcyc
s
Conversion range
VREFH
Monotonicity
Comments
Including quanitization
A/D accuracy may decrease
proportionately as VREFH is
reduced below 4.0
00
01
Hex
Vin = 0 V
Full-scale reading
FE
FF
Hex
Vin = VREFH
Sample time
MCU external oscillator
Internal RC oscillator
12
12
tcyc
s
Input capacitance
12
pF
VSS
VREFH
100
tADON
IOZ
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = 40C to +85C, unless otherwise noted.
Symbol
Min
Typ
Max
Unit
Programming voltage
IRQ/VPP
VPP
16.25
16.5
16.75
Programming current
IRQ/VPP
IPP
5.0
10
mA
tEPGM
ms
Freescale Semiconductor
SIOP Timing
Characteristic
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fop(m)
fop(s)
0.25
dc
0.25
0.25
fop
Cycle time
Master
Slave
tcyc(m)
tcyc(s)
4.0
4.0
4.0
tcyc
tcyc
932
ns
tv
200
ns
tho
ns
ts
100
ns
th
100
ns
t1
t2
SCK
t5
SDI
BIT 0
t3
SDO
BIT 1 ... 6
t6
BIT 7
t4
BIT 0
BIT 1 ... 6
BIT 7
89
Electrical Specifications
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
External clock option
fOSC
DC
4.2
4.2
MHz
fOP
DC
2.1
2.1
MHz
Cycle time
tCYC
476
ns
tOXOV
100
ms
tILCH
100
ms
tRL
1.5
tCYC
tILIH
125
ns
tILIL
Note 2
tCYC
tOH, tOL
200
ns
tADON
100
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = 40C to +125C, unless otherwise noted
2. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tCYC.
Freescale Semiconductor
Freescale Semiconductor
tVDDR
V
V
DD
DD
(2)
OSC1
4064 tcyc
t
INTERNAL
PROCESSOR
(1)
CLOCK
cyc
INTERNAL
ADDRESS
BUS(1)
1FFE
1FFF
INTERNAL
DATA
(1)
BUS
NEW
PCH
NEW
PCL
NEW PC
NEW PC
1FFE
1FFE
1FFE
OP
CODE
1FFE
1FFF
PCH
PCL
NEW PC
NEW PC
OP
CODE
tRL
RESET
NOTE 3
Notes:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal clock following the rising edge of RESET initiates the reset sequence.
91
Control Timing
Electrical Specifications
Freescale Semiconductor
Chapter 15
Mechanical Specifications
15.1 Introduction
The MC68HC705P6A is available in either a 28-pin plastic dual in-line (PDIP) or a 28-pin small outline
integrated circuit (SOIC) package.
28
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
15
B
1
14
C
N
G
F
K
SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
36.45 37.21
13.72 14.22
5.08
3.94
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.38
0.20
3.43
2.92
15.24 BSC
0
15
0.51
1.02
INCHES
MIN
MAX
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 BSC
0.065 0.085
0.008 0.015
0.115 0.135
0.600 BSC
0
15
0.020 0.040
93
Mechanical Specifications
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
15
14X
-B1
P
0.010 (0.25)
14
28X D
0.010 (0.25)
R X 45
C
-T26X
-T-
G
K
SEATING
PLANE
F
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
17.80 18.05
7.60
7.40
2.65
2.35
0.49
0.35
0.90
0.41
1.27 BSC
0.32
0.23
0.29
0.13
8
0
10.05 10.55
0.75
0.25
INCHES
MIN
MAX
0.701 0.711
0.292 0.299
0.093 0.104
0.014 0.019
0.016 0.035
0.050 BSC
0.009 0.013
0.005 0.011
8
0
0.395 0.415
0.010 0.029
Freescale Semiconductor
Chapter 16
Ordering Information
16.1 Introduction
This section contains ordering information for the available package types.
MC68HC705P6ACDW
(extended)
Operating
Temperature Range
40C to 85C
40C to 85C
95
Ordering Information
Freescale Semiconductor
blank
RoHS-compliant and/or Pb- free versions of Freescale products have the functionality
and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
E-mail:
support@freescale.com
MC68HC705P6A
Rev. 2.1, 9/2005
Mouser Electronics
Authorized Distributor
Freescale Semiconductor:
MC705P6ACPE MC705P6ECPE
NXP:
MC705P6ACDWE MC705P6AMDWE