Toshiba Satellite C55 Compal LA-B301P r1.0

A
Compal Confidential
ZSWAA/ZCWAA Schematics Document
Intel Haswell ULT/Broadwell U with DDR3L
AMD GPU Jet Pro/Topaz XT S3 (Single Rank)
LA-B301P REV 1.0 Schematic

3
Intel Processor (Haswell ULT/Broadwell U)

2014-02-10 Rev 1.0
2013/09/25
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/09/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Cover Page
Rev
1.0
ZSWAA/ZCWAA LA-B301P
Date:
Monday, February 10, 2014
Sheet
E
of
52
External Graphics
AMD GPU Jet Pro S3/Topaz XT S3
Single Rank
VRAM (gDDR3) 900MHz @ 1.35V
1
Intel Haswell ULT/Broadwell U
PCI-Express 4X Gen3 8GT/s
Dual Channel
page 16,17
BANK 0, 1, 2
1.35V DDR3L 1333/1600 MT/s
Haswell ULT/
Broadwell U
LVDS Translator
RTD2132N-CGT
page 27
Memory BUS(DDR3L) 204pin DDR3-SO-DIMM X2
eDP 1X 5.4GT/s
page 18~25
LVDS Conn.
Colay eDP
USB30 2x
Processor
5V 5GT/s
page 26
USB20 2x
USB3.0 x2 Right
USB20 port 0,1
USB30 port 1,2
5V 480MHz
page 34
OPI
HDMI Conn.
USB20 1x
page 28
5V 480MHz
Lynx Point - LP/

Wildcat Point - LP
NGFF Slot 1
WLAN PCIe port 4
PCIe Gen1 1x
5V 480MHz
PCH
1.5V 5GT/s
USB20 port 4
USB20 1x
SATA Gen3 port 0
Touch Screen
USB20 port 5
page 27
Int. Camera
USB20 port 7
page 27
SATA HDD/SSD
SATA port 0
page 31
5V 6GHz(600MB/s)
USB20 1x
page 32
5V 480MHz
SATA Gen3 port 1
SATA ODD
SATA port 1
page 31
5V 6GHz(600MB/s)
DP 2X 5.4GT/s
1168pin BGA
page 05~15
DP to CRT Translator
ITE IT6513FN
Sub Boards
LS-B301P
LED/B
RTC CKT.
page 37
page 7
SPI ROM
(8MB)
LPC BUS
HD Audio
3.3V 33 MHz
3.3V 24MHz
KB9012QF A4
page 30
LS-B302P
Power Button/B
page
ALC233-VB1-CG
(w/o S&M) page 35
DC/DC Interface CKT.

37
page 38
Int.KBD
page 37
LS-B303P
LAN+USB/B
Audio Combo Jack
HDA Codec
page 36
page 8
CRT Conn.
page 29
TPM
page 33
Power Circuit DC/DC
SPK Conn
page 35
page 39~48
4
page 33
Power On/Off CKT.

LS-B304P
CardReader/TP/LID B
page 37
2013/09/25
Issued Date
Compal Secret Data
page 37
2016/09/25
Deciphered Date
Title
Size
Date:
Block Diagram
Document Number
Rev
1.0
Sheet
E
of
52
B+
PU350
EC_ON
Ipeak=8A, Imax=5.6A, Iocp=9A
SY8208CQNC
DESIGN CURRENT 10.81A
+5VALW
+5VS
DESIGN CURRENT 1.1A
+5VS_ODD
SUSP#
U3
TPS22966DPUR
U7
+5VS
AP2151DWG-7
1
U16
ODD_EN
DESIGN CURRENT 1A
+HDMI_5V_OUT
DESIGN CURRENT 2A
+USB_VCCB
DESIGN CURRENT 2A
+USB_VCCC

+3VL
+3VALW
DESIGN CURRENT 6A
+3VS
DESIGN CURRENT 2A
+LCD_VDD
+3VGS
DESIGN CURRENT 253mA
+3VALW_PCH
+3V_WLAN
+1.5VS
+1.8VGS
+0.95VGS
Ipeak=10A, Imax=7A, Iocp=12A
+1.35V
TPS22967DSGR
USB_EN#0
UR1
SY6288D20AAC
USB_EN#2
UR3
SY6288D20AAC
EC_ON
PU300
SY8206BQNC

SUSP#
U3
TPS22966DPUR
U1
LCD_ENVDD
2
SY6288C20AAC
QV3
PXS_PWREN
AO3413
PCH_PWR_EN#
Q10
AO3413
WOWL_EN
U8
TPS22967DSGR
SUSP#
PUM00
Ipeak=0.5A, Imax=0.35A, Iocp=5.7A
APL5930KAI-TRG
3
PXS_PWREN
PU1800
PUF00
PXS_PWREN
SY8033BDBC
SYSON: Enable 1.35V
DDR_VTT_PG_CTRL: Enable
PUW00
Ipeak=1A, Imax=0.7A, Iocp=2.5A
SY8032ABC
0.675VS
RT8207MZQW
QV5
PXS_PWREN#
DESIGN CURRENT 6.5A
+1.35VGS
DESIGN CURRENT 1.5A
+0.675VS
+1.05VS_VTT
AO4354
SUSP#
PUH00
SY8206DQNC
VR_ON
PUZ00
DESIGN CURRENT 32A
+CPU_CORE
DESIGN CURRENT 24A
+VGA_CORE
TPS51624RSM
PUV00
PXS_PWREN
Compal Secret Data
RT8880BGQW
Issued Date
2013/09/25
Deciphered Date
2016/09/25
Title

Power Map
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Rev
1.0
Date:
Sheet
E
of
52
( O MEANS ON
Voltage Rails
X MEANS OFF )
+RTCVCC
B+
BTO Option Table
+5VL
+5VALW
+3VL
+3VALW
+1.35V
+5VS
VRAM
Internal Panel
HDMI
Wake On Wireless
Description UMA
DIS
HASWELL
BROADWELL
JET
TOPAZ
X76
LVDS
eDP
HDMI
WOWL
NON-WOWL
Explain
UMA
DIS
HASWELL
BROADWELL
JET
TOPAZ
X76
LVDS
eDP
HDMI
WOWL
NON-WOWL
BTO
UMA@
VGA@
HASWELL@
BROADWELL@
JET@
TOPAZ@
X76@
LVDS@
IEDP@
HDMI@
ISCT@
NOISCT@
+CPU_CORE
+VGA_CORE
SKU
Function
+3VS
+1.5VS
+1.5VALW
power
plane
Processor
GPU
+3VGS
+1.8VGS
+1.35VGS
+0.95VGS
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery

don't exist
CPU (R1 PN)
Function
+1.05VS_VTT
State
Description
I3-4005U
I5-4200U
I3-4010U
2990U
I5-4210U
I3-4015U
Explain
SA000072Q70
SA00006SM80
SA00006SXA0
SA00007LM00
SA00007LO00
SA00007LN00
BTO
4005UR1@
4200UR1@
4010UR1@
2990UR1@
4210UR1@
4015UR1@
CPU (R3 PN)
Function
Description
I3-4005U
I5-4200U
I3-4010U
Explain
SA000072Q60
SA00006SM90
SA00006SX90
BTO
4005UR3@
4200UR3@
4010UR3@
ODD
Function
Explain
PCH SM Bus Address
Zero Power ODD
Device
HEX
Address
+3VS
DDR SO-DIMM 0
A0 H
1010 0000 b
+3VS
DDR SO-DIMM 1
A4 H
1010 0100 b
FIX
Short pad
ESD
XDP
FIX
Short pad
ESD
Non-Zero Power ODD XDP
FIX
0 ohm short pad
ESD
FIX@
Rshort@
Non-ZPODD
ZPODD@
BTO
Power
XDP
ZPODD
Description
NONZP@
XDP@
ESD@
@ESD@
EMI
CAM_EMI
CRT_EMI
TPM_EMI
TOUCH_EMI
Description
EMI
CAM_EMI
CRT_EMI
TPM_EMI
TOUCH_EMI
Explain
EMI
CAM_EMI
CRT_EMI
TPM_EMI
TOUCH_EMI
Function
EMI@
BTO
EC SM Bus1 Address
Power
Device
HEX
Address
Power
Device
HEX
Smart Battery
16 H
0001 0110 b
+3VS
PCH
96 H
1001 0110 b
+3VL
Smart Charger
12 H
0001 0010 b
+3VGS
AMD GPU
9E H
1001 1010 b
Power
Device
HEX
Address
Intel
SharkBay ULT
@CAM_EMI@
CRT_EMI@
@CRT_EMI@
TPM_EMI@
@TPM_EMI@ TOUCH_EMI@
@TOUCH_EMI@
EC SM Bus2 Address
+3VL
Platform
@EMI@ CAM_EMI@
SKU
CPU
UMA
DIS
Haswell-M
ULT Processor
PCH
Address
VGA
Lynx Point - LP
AMD GPU
Jet Pro S3
Topaz XT S3
SIGNAL
STATE
Full ON
SLP_S3# SLP_S4# SLP_S5#

HIGH
HIGH
HIGH
S1(Power On Suspend)
HIGH
HIGH
HIGH
S3 (Suspend to RAM)
LOW
HIGH
HIGH
S4 (Suspend to Disk)
LOW
LOW
HIGH
S5 (Soft OFF)
LOW
LOW
LOW
G3
LOW
LOW
LOW
Compal Secret Data
2013/09/25
Issued Date
2016/09/25
Deciphered Date
Title
Notes List
Custom
Rev
1.0
Date:
Sheet
E
of
52
DP to CRT
<29>
<29>
<29>
<29>
CRT@
CRT@
CRT@
CRT@
H_DP1_C_N0
H_DP1_C_P0
H_DP1_C_N1
H_DP1_C_P1
C76
C80
C77
C74
1
1
1
1
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
C54
C55
B58
C58
B55
A55
A57
B57
H_DP1_N0
H_DP1_P0
H_DP1_N1
H_DP1_P1
<28>
<28>
<28>
<28>
<28>
<28>
<28>
<28>
HDMI
C51
C50
C53
B54
C49
B50
A53
B53
H_HDMI_TX2H_HDMI_TX2+
H_HDMI_TXCH_HDMI_TXC+
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
DDI
EDP
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL
T20
T97
+1.05VS_VTT
<36>
1
R68
62_0402_5%
H_PROCHOT#
@ESD@
1
2
H_CPUPW RGD
CH6
180P_0402_50V8J
D61
K61
N62
@
@
R25
R10
56_0402_5%
1
2
PROC_DETECT
CATERR
PECI
K63
2 10K_0402_5% H_CPUPW RGD
C61
PROCHOT
PROCPWRGD
+1.35V
R184
470_0402_5%
2 200_0402_1% SM_RCOMP0
AU60
2 121_0402_1% SM_RCOMP1
AV60
2 100_0402_1% SM_RCOMP2
AU61
DIMM_DRAMRST# AV15
<16,17> DIMM_DRAMRST#
AV61
<16> DDR_PG_CTRL
R24
R23
R41
1
1
1
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
DDR3 Compensation Signals
<26>
<26>
<26>
<26>
C47
C46
A49
B49
A45
B45
D20
A43
H_EDP_AUXN
H_EDP_AUXP
EDP_COMP R1 1
<26>
<26>
2 24.9_0402_1%
+VCCIOA_OUT
Trace width=20 mils,Spacing=25mil,Max length=100mils
MISC
PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
JTAG
H_PROCHOT#_R
H_EDP_TXN0
H_EDP_TXP0
H_EDP_TXN1
H_EDP_TXP1
HASWELL_MCP_E
UC1B @
H_PECI
C45
B46
A47
B47
Rev1p2
1 OF 19
<36>
HASWELL_MCP_E
UC1A @
THERMAL
J62
K62
E60
E61
E59
F63
F62
XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
J60
H60
H61
H62
K59
H63
K60
J61
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
T154
PWR
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
DDR3
@
@
@
@
@
@
@
@
T155
T156
T148
T149
T150
T151
T152
T153
Rev1p2
2 OF 19
PU/PD for JTAG signals
DIMM_DRAMRST#
+1.05VS_VTT
B
XDP_TMS
R86
XDP_TDI
R87
1 XDP@
2 51_0402_5%
XDP_PREQ#
R88
2 51_0402_5%
XDP_TDO
R89
1 XDP@
2 51_0402_5%
XDP_TCK
R90
1 XDP@
2 51_0402_5%
XDP_TRST#
R91
2 51_0402_5%
2 51_0402_5%
Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
5
Title
HSW MCP(1/11) DDI,MSIC,XDP
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
1
of
52
UC1C @
HASWELL_MCP_E
UC1D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
DDR CHANNEL A
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
SA_CLK_DDR#0 <16>
SA_CLK_DDR0 <16>
SA_CLK_DDR#1 <16>
SA_CLK_DDR1 <16>
AU43
AW43
AY42
AY43
DDRA_CKE0_DIMMA
DDRA_CKE1_DIMMA
AP33
AR32
DDRA_CS0_DIMMA#
DDRA_CS1_DIMMA#
<16>
<16>
<16>
<16>
AP32
AY34
AW34
AU34
AU35
AV35
AY41
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
<16>
<16>
<16>
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
<16>
<16>
<16>
AU36 DDR_A_MA0
AY37 DDR_A_MA1
AR38 DDR_A_MA2
AP36 DDR_A_MA3
AU39 DDR_A_MA4
AR36 DDR_A_MA5
AV40 DDR_A_MA6
AW39DDR_A_MA7
AY39 DDR_A_MA8
AU40 DDR_A_MA9
AP35 DDR_A_MA10
AW41DDR_A_MA11
AU41 DDR_A_MA12
AR35 DDR_A_MA13
AV42 DDR_A_MA14
AU42 DDR_A_MA15
AJ61 DDR_A_DQS#0
AN62 DDR_A_DQS#1
AM58 DDR_A_DQS#2
AM55 DDR_A_DQS#3
AV57 DDR_A_DQS#4
AV53 DDR_A_DQS#5
AL43 DDR_A_DQS#6
AL48 DDR_A_DQS#7
AJ62 DDR_A_DQS0
AN61 DDR_A_DQS1
AN58 DDR_A_DQS2
AN55 DDR_A_DQS3
AW57DDR_A_DQS4
AW53DDR_A_DQS5
AL42 DDR_A_DQS6
AL49 DDR_A_DQS7
AP49
AR51
AP51
<16>
<16>
<16>
<16>
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
SM_DIMM_VREFCA
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
<16>
<16>
<17>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
HASWELL_MCP_E
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
DDR CHANNEL B
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
SB_CLK_DDR#0 <17>
SB_CLK_DDR0 <17>
SB_CLK_DDR#1 <17>
SB_CLK_DDR1 <17>
AY49
AU50
AW49
AV50
AM32
AK32
DDRB_CKE0_DIMMB
DDRB_CKE1_DIMMB
<17>
<17>
DDRB_CS0_DIMMB#
DDRB_CS1_DIMMB#
<17>
<17>
AL32
AM35
AK35
AM33
DDR_B_RAS# <17>
DDR_B_WE# <17>
DDR_B_CAS# <17>
AL35
AM36
AU49
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
<17>
<17>
<17>
AP40 DDR_B_MA0
AR40 DDR_B_MA1
AP42 DDR_B_MA2
AR42 DDR_B_MA3
AR45 DDR_B_MA4
AP45 DDR_B_MA5
AW46 DDR_B_MA6
AY46 DDR_B_MA7
AY47 DDR_B_MA8
AU46 DDR_B_MA9
AK36 DDR_B_MA10
AV47 DDR_B_MA11
AU47 DDR_B_MA12
AK33 DDR_B_MA13
AR46 DDR_B_MA14
AP46 DDR_B_MA15
AW30 DDR_B_DQS#0
AV26 DDR_B_DQS#1
AN28 DDR_B_DQS#2
AN25 DDR_B_DQS#3
AW22DDR_B_DQS#4
AV18 DDR_B_DQS#5
AN21 DDR_B_DQS#6
AN18 DDR_B_DQS#7
AV30 DDR_B_DQS0
AW26 DDR_B_DQS1
AM28 DDR_B_DQS2
AM25 DDR_B_DQS3
AV22 DDR_B_DQS4
AW18 DDR_B_DQS5
AM21 DDR_B_DQS6
AM18 DDR_B_DQS7
<17>
<17>
<17>
<17>
DDR_B_D[0..63]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
Rev1p2
3 OF 19
4 OF 19
Rev1p2
Issued Date
Compal Secret Data
2013/09/25
2016/09/25
Deciphered Date
Title
HSW MCP(2/11) DDRIII
Custom
Rev
1.0
Date:
Sheet
1
of
52
UC1E
1
15P_0402_50V8J
YH1
32.768KHZ_12.5P_1TJF125DP1A000D
D
CMOS Setting, near DDR Door

RH23 1
20K_0402_5%
+RTCVCC
PCH_RTCRST#
2
JCMOS @
1
2
CH4 1
1U_0402_6.3V6K
JME
1
2PCH_SRTCRST#
INTVRMEN
H Integrated VRM enable
L Integrated VRM disable
PCH_INTVRMEN
SM_INTRUDER#
<36>
R73
2 330K_0402_5%
R72
2 1M_0402_5%
AZ_SDIN0_HD
@
2
T6
T7
T8
T9
T95
51_0402_5% 1
HASWELL_MCP_E
RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST
J5
H5
B15
A15
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
RTC
PCH_RTCRST#
HDA_BIT_CLK
HDA_SYNC
HDA_RST#
+RTCVCC
AW5
AY5
AU6
AV7
AV6
AU7
J8
H8
A17
B17
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
CH5 1
1U_0402_6.3V6K
1
15P_0402_50V8J
<35>
iME Setting.
RH24 1
20K_0402_5%
CH3
PCH_RTCX1
PCH_RTCX2
SM_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#
RH2
10M_0402_5%
2
1
2
CH2
2 R98
T21
T19
T15
T10
T11
T22
T12
@
HDA_SDOUT
@
@
@
@ PCH_JTAG_RST#
PCH_JTAG_TCK
@ PCH_JTAG_TDI
@ PCH_JTAG_TDO
@ PCH_JTAG_TMS
@
@
@ PCH_TCK_JTAGX
@
AW8
AV11
AU8
AY10
AU12
AU11
AW10
AV10
AY8
AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2
HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK
AUDIO
SATA
SATA_PRX_C_DTX_N1 <31>
SATA_PRX_C_DTX_P1 <31>
SATA_PTX_DRX_N1 <31>
SATA_PTX_DRX_P1 <31>
ODD
F5
E5
C17
D17
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
ODD_DETECT# PU at Page10
V1
U1
V6 @
AC1 @
EC_SMI# <36>
ODD_DETECT# <10,31>
T159
T165
A12
L11 @
K10 @
C12
U3
SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED
JTAG
HDD/SSD
J6
H6
B14
C15
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD
RSVD
JTAGX
RSVD
SATA_PTX_DRX_N0 <31>
SATA_PTX_DRX_P0 <31>
T13
T14
SATA_RCOMP
+1.05VS_ASATA3PLL
within 500 mils

1
R2
2 3.01K_0402_1%
Rev1p2
5 OF 19
HDA for AUDIO

RP14
1
2
3
4
<35> AZ_RST_HD#
<35> AZ_BITCLK_HD
<35> AZ_SDOUT_HD
<35> AZ_SYNC_HD
8
7
6
5
HDA_RST#
HDA_BIT_CLK
HDA_SDOUT
HDA_SYNC
33_0804_8P4R_5%
<36>
1 Rshort@ 2
R163
0_0402_5%
PWRME_CTRL
ME Debug
FAN Control Circuit

B
+5VS
RTC schematic for non-chargeable
JFAN
C502
0.1U_0402_16V4Z
2
1
R277 1K_0402_5%
@
C60
10U_0805_6.3V6M
U4
<36>
1
1K_0402_5%
10mil
DFAN1
SUYIN_060003HA002G202ZL
@
EN
VIN
VOUT
VSET
GND
GND
GND
GND
@
2
C43
1000P_0402_50V7K
1
8
7
6
5
4
5
1
2
3
GND
GND
CVILU_CI4403M1HRT-NH
R29
P2793BB0_SO8
10K_0402_5%
1
+3VS
FAN_SPEED1
C71
10U_0805_6.3V6M
R437
1
2
3
4
+FAN2
JRTC
+RTC_R
+5VS_FAN
D17
1
2
3
+FAN2
1 Rshort@ 2
R32
0_0603_5%
1
1
+3VL
D16
2
RB751V40_SC76-2
2 +RTCBATT_R
RB751V40_SC76-2
1A
+RTCBATT
+RTCVCC
FAN_SPEED1
<36>
C75
0.01U_0402_25V7K
@
Main source SA00005CA00

2nd source SA00005JO00
0812 -> Add R277 for RTC reserve charge

A
Change D16,D17 P/N from

SCS0340L010 to SCS00003500
for X code.
Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
5
Title
HSW MCP(3/11) RTC,SATA,XDP
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
1
of
52
PCH_X1
2
1M_0402_5%
1
R48
C2
12P_0402_50V8J
T158
<37> CLK_CR#
<37> CLK_CR
<37> CLKREQ_CR#
C3
12P_0402_50V8J
WLAN
RH90
RH92
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18
B41
A41
Y5
CLKREQ_LAN#
C41
B42
AD1
CLK_WLAN#
CLK_WLAN
CLKREQ_WLAN#
CLKREQ_W LAN#
B38
C37
N1
<18> CLK_PCIE_VGA#
<18> CLK_PCIE_VGA
<19> CLK_REQ_VGA#
CLK_REQ_VGA#
<32>
<32>
<10,32>
+3VS
C43
C42
U2
CLKREQ_CR#
<33> CLK_LAN#
<33> CLK_LAN
<33> CLKREQ_LAN#
PCIE LAN
HASWELL_MCP_E
UC1F @
PCH_X2
Y2
1
3
2
4
24MHZ_12PF_X3G024000DC1H
1
T160
RSVD
RSVD
DIFFCLK_BIASREF
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLOCK
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
SIGNALS
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
A39
B39
U5
CLKREQ_CR#
10K_0402_5%
XTAL24_IN
XTAL24_OUT
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
B37
A37
T2
@
A25
B25
PCH_X1
PCH_X2
K21 @
M21 @
C26
T16
T17
XCLK_BIASREF
C35
C34
AK8
AL8
R140
R141
R142
R148
1
1
1
1
2
2
2
2
AN15
AP15
CLKOUT_LPC0
CLKOUT_LPC1_R
R78
2 3.01K_0402_1%
+1.05VS_AXCK_LCPLL
R390
R391
B35 CLK_BCLK_ITP#
A35 CLK_BCLK_ITP
@
@
2 EMI@ 1 22_0402_5%
2
1 22_0402_5%
TPM@EMI@
T18
T130
+3VS
CLK_PCI_EC <36>
CLKOUT_LPC1 <33>
CLK_PCI_EC
1
1
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
CH11
10P_0402_50V8J
CLKREQ_LAN#
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
@EMI@
CH10
@EMI@
10P_0402_50V8J
Rev1p2
6 OF 19
CLKREQ_WLAN# pull high on page 10

UC1G
+3VS
<33,36> LPC_AD0
<33,36> LPC_AD1
<33,36> LPC_AD2
<33,36> LPC_AD3
<33,36> LPC_FRAME#
AU14
AW12
AY12
AW11
AV12
LAD0
LAD1
LAD2
LAD3
LFRAME
SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SMBUS
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74
LPC
RH89
10K_0402_5%
UMA@
HASWELL_MCP_E
PCH_SPICLK
PCH_SPICS0#
CLK_REQ_VGA#
PCH_SPIDI
PCH_SPIDO1
PCH_SPIDO2
PCH_SPIDO3
RH91
10K_0402_5%
VGA@
AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
SPI
C-LINK
CL_CLK
CL_DATA
CL_RST
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
SMB_ALERT#
PCH_SMBCLK
PCH_SMBDATA
@
T170
PCH_SMLCLK1
PCH_SMLDATA1
AF2
AD2
AF4
@
@
@
<10>
PCH_SMBDATA <10>
LAN_EN <10,33>
SML0CLK <10>
SML0DATA <10>
<10>
T23
T24
T25
+3VALW _PCH
RP8
<9>
<11>
SUSW ARN#
PCH_SMLCLK1
USB_CHG_OC#
PCH_SMBCLK
1
2
3
4
8 2.2K_0804_8P4R_5%
7
6
5
Rev1p2
7 OF 19
PCH_SMBDATA pull high on page 10
+3VS
B
1 1K_0402_5%
PCH_SPIDO2
RH16 2
1 1K_0402_5%
PCH_SPIDO3
RH5
+3VALW _PCH
SPI ROM for BIOS & ME & Win8 (8MByte )
PCH_SMBCLK
CH9
0.1U_0402_10V7K
2
EC_SDIO
RH61 1 FIX@
RH68 1
RH69 1
2 15_0402_5%
2 15_0402_5%
2 15_0402_5%
RH72 1 FIX@
2 15_0402_5%
PCH_SPICS0#
PCH_SPI0_DO1
PCH_SPI0_DO2
1
2
3
4
CS#
SO
WP#
GND
VCC
HOLD#
SCLK
SI
8
7
6
5
PCH_SPI0_DO3
PCH_SPI0_CLK
PCH_SPI0_DI
1
4
2 15_0402_5%
RH65 1
RH66 1 Rshort@ 2 0_0402_5%
2 15_0402_5%
RH67 1
PCH_SPIDO3
PCH_SPICLK
PCH_SPIDI
<16,17,37>
PM_SMBCLK
<16,17,37>
+3VS
S IC FL 64M W 25Q64FVSSIQ SOIC 8P SPI ROM

RH74 1 FIX@
2 15_0402_5%
RH78 1 FIX@
2 15_0402_5%
<36>
PCH_SPIDO1
PCH_SPIDO2
EC_SCK
EC_SDI
PU 2.2K at EC side (+3VS)
<36>
PCH_SMLDATA1
<36>
EC_CS0#
PM_SMBDATA
Q7B
2N7002DW -T/R7_SOT363-6
UH3
<36>
R119
4.7K_0402_5%
Q7A
2N7002DW -T/R7_SOT363-6
PCH_SMBDATA 6
R116
4.7K_0402_5%
+3VALW _PCH
+3VS
Please place UH3 close to U1 CPU,

Please place RH66, RH67, RH68 near UH3
PCH_SMLCLK1
EC_SMB_DA2
QH4B
2N7002DW -T/R7_SOT363-6
1
EC_SMB_CK2
<19,36>
<19,36>
QH4A
A
2N7002DW -T/R7_SOT363-6
Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
5
Title
HSW MCP(4/11) CLK,SPI,SMBUS
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
1
of
52
DH2
+3VALW _PCH
PCH_PW ROK
+3VS
1
1
EC_SW I# RH171
<36,42>
R227
10K_0402_5%
PCH_RSMRST#
POK
2
1
1K_0402_5%
* LH
Enable(DEFAULT)
Disable
DSWODVREN - On Die DSW VR Enable
BAS40-04_SOT23-3
SYS_RESET#
UC1H
R124 1
@ESD@
1
2
PLT_RST#
CH7
180P_0402_50V8J
10K_0402_5% 2
1 R117
SUSW ARN#
<36>
PCH_RSMRST#
SUSACK#
SYS_RESET#
SYS_PW ROK
PCH_PW ROK
PLT_RST#
PLT_RST#
AK2
AC3
AG2
AY7
AB5
AG7
SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST
<36>
1
PCH_PW ROK
0.1U_0402_16V7K
PCH_RSMRST#
PCH_RSMRST#
SUSW ARN#
<8> SUSW ARN#

<36> PBTN_OUT#
R156 1
+3VALW _PCH
V5
AG4
AE6
AP5
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29
DSW ODVREN
PCH_RSMRST#
EC_SW I#
EC_SW I#
1
R157
@
CLKRUN#
@
@
AJ6
AT4
AL5
AP4
AJ7
SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN
<33,36>
CLK_EC <32>
PM_SLP_S5# <36>
PM_SLP_S4#
PM_SLP_S3#
@
@
PM_SLP_LAN#
T27
T28
<36,41>
ACIN
<36>
<36>
+3VALW _PCH
not support Deep S4,S5 can NC
T29
PM_SLP_S4#
PM_SLP_S3#
T30
T96
R118 1
@
10K_0402_5%
R245
100K_0402_5%
D21
2
+3VS
8.2K_0402_5%
T104
PM_SLP_S5#
+3VALW_PCH
PCH_ACIN
2 8.2K_0402_5% PCH_BATLOW #
T31
@
AW6
AV4
AL7
AJ8
AN4
AF3
AM5
AW7
AV5
AJ5
DSWVRMEN
DPWROK
WAKE
1
PCH_RSMRST#
0.1U_0402_16V7K
2
C170
2 330K_0402_5%
SYSTEM POWER MANAGEMENT
R206
2 0_0402_5%
PCH_PW ROK
<18,36>
2
C169
+RTCVCC
HASWELL_MCP_E
Note for PCH_ACIN: Deep Sx need use

EC GPIO for ACPRESENT function
PCH_ACIN
Rev1p2
8 OF 19
DDPB_CTRLDATA: Port B Detected

RB751V40_SC76-2
DDPC_CTRLDATA: Port C Detected

C
Change D21 P/N from

SCS0340L010 to SCS00003500
for X code.
1: Port B or C is detected
0: Port B or C is not detected
(Have internal PD)
UC1I
HASWELL_MCP_E
+3VS
RH17 1 LVDS@ 2 0_0402_5%
<26>
PCH_PW M_TL
<27>
PCH_PW M_EDP
RH18 1 IEDP@ 2 0_0402_5%

RH19 1 Rshort@ 2 0_0402_5%
PCH_PW M
EC_ENBKL_R_CPU
EC_ENBKL_R
<26,36>
EC_ENBKL_R
EC_ENBKL_R
<27>
R418
100K_0402_5%
<10,37>
B8
A9
C6
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
eDP SIDEBAND
B9
C9
D9
D11
R271 1
2 2.2K_0402_5%
UMA_HDMI_CLK
UMA_HDMI_DATA
<28>
<28>
LCD_ENVDD
<18,48> DGPU_PW RGD

<10,20,45,48> PXS_PW REN
<10,18> DGPU_HOLD_RST#
1
2
TP_INTR#
RH7 HASW ELL@ 0_0402_5%
1
2
RH8
0_0402_5%
BROADW ELL@
B
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
T157
T26
@
PCH_GPIO54
PCH_GPIO51
PCH_GPIO53
U6
P4
N4
N2
AD4
U7
L1
L3
R5
L4
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
DISPLAY
GPIO
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
C5
B6
B5
A6
C8
A8
D6
H_DDI1_AUXN
<29>
H_DDI1_AUXP
<29>
H_DP_HPD <29>
HDMI_HPD <10,28>
H_EDP_HPD <26,27>
H_EDP_HPD
H_EDP_HPD
Rev1p2
9 OF 19
R417
100K_0402_5%
R403
0_0402_5%
2
1
@
SYS_PW ROK
+3VS
PLT_RST#
IN1
IN2
OUT
PLT_RST_BUF#
<32,33,37>
R416
100K_0402_5%
U30
MC74VHC1G08DFT2G_SC70-5
R208
10K_0402_5%
VCC
1 Rshort@ 2 0_0402_5%
GND
R65
PCH_PW ROK
Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
5
Title
HSW MCP(5/11) PM,GPIO,DDI
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
1
of
52
Note: need check all GPIO PU need or not after BIOS post
+3VS
RP23 1
2
3
4
8
7
6
SERIRQ
5
ODD_EN
10K_0804_8P4R_5%
TP_INTR#
<37,9>
UC1J
HASWELL_MCP_E
<36> EC_LID_OUT#
<38> ODD_EN
<31> ODD_DA#
ESD@
1
2
ODD_DA#
180P_0402_50V8J
JPW
@
+3VALW _PCH
1
2
3
4
RP35
8
7
6
5
8
7
6
5
RP34
10K_0804_8P4R_5%
1
2
3
4
SML0DATA <8>
LAN_EN <33,8>
SMB_ALERT# <8>
SML0CLK <8>
PCH_SMBDATA <8>
PCH_SMLDATA1 <8>
USB_OC#2 <11,33,36>
USB_OC#0 <11,34,36>
<36>
RP28 1
2
3
4
+3VS
8
PCH_GPIO27
7
PASSW ORD_CLEAR#
6
5
10K_0804_8P4R_5%
EC_LID_OUT#
ODD_EN
ODD_DA#
PCH_GPIO24
PCH_GPIO27
PCH_GPIO28
PCH_GPIO26
P1
AU2
AM7
AD6
Y1
T3
AD5
AN5
AD7
AN3
PASSW ORD_CLEAR# AG6

AP1
T166
@
PCH_GPIO58 AL4
PCH_GPIO59 AT5
AK4
PCH_GPIO47 AB6
U4
BROADW ELL@
2 DGPU_PRSNT#_GPIO49 Y3
DGPU_PRSNT# 1
P3
RH10
0_0402_5% T139
@
Y2
PCH_GPIO71
AT3
T168
@
PCH_GPIO14 AH4
AM4
T169
@
PCH_GPIO45 AG5
PCH_GPIO46 AG3
2.2K_0804_8P4R_5%
@
@
AM3
AM2
P2
C4
L2
N5
V2
HASW ELL@
PCH_GPIO9
2 0_0402_5%
RH4 1
EC_SCI#
<35>
BROADW ELL@
T136
@
2 0_0402_5%
RH6 1
PCH_SPKR
PCH_SPKR
BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46
CPU/
MISC
GPIO
LPIO
GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
ODD_DETECT# <31,7>
PXS_PW REN <20,45,48,9>
THERMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
D60
H_THERMTRIP#
V4
KB_RST#
T4
SERIRQ
AW15
PCH_OPIRCOMP
AF20 @
T106
AB21
R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2
+1.05VS_VTT
PCH_GPIO83
PCH_GPIO84
PCH_GPIO85
PCH_GPIO86
DGPU_PRSNT#_GPIO87
PCH_GPIO88
PCH_GPIO89
@
T135
@
T134
PCH_GPIO92
PCH_GPIO93
@
T114
@
@
PCH_GPIO3
@
PCH_GPIO5
PM_I2CSDA1
PM_I2CSCL1
PCH_GPIO64
PCH_GPIO65
PCH_GPIO66
PCH_GPIO67
PCH_GPIO68
ZP_DETECT
T111
T133
KB_RST# <36>
SERIRQ <33,36>
2 R146
49.9_0402_1%
HASW ELL@
RH9 0_0402_5%
1
2 DGPU_PRSNT#
DGPU_HOLD_RST# <18,9>
CLKREQ_W LAN# <32,8>
CH8
T162
T167
8
7
ODD_DA#
6
5
10K_0804_8P4R_5%
R144
1K_0402_5%
RP27 1
2
3
4
H_THERMTRIP#
HDMI_HPD
<28,9>
T132
C
PM_I2CSDA1
PM_I2CSCL1
<37>
<37>
Rev1p2
10 OF 19
+3VS
PM_I2CSDA1
R274 1
2 1K_0402_5%
PM_I2CSCL1
R272 1
2 1K_0402_5%
+3VS
R306
10K_0402_5%
UMA@
+3VS
Need to check the
resistors value
2
DGPU_PRSNT#
R215
10K_0402_5%
R219
10K_0402_5%
VGA@
PowerXpress
UMA
0
1
+3VS
R269 1
ZPODD@
DGPU_PRSNT#
ZP_DETECT
ZPODD SKU
None ZPODD SKU
1
R216
10K_0402_5%
2 1K_0402_1%
PCH_SPKR
GPIO69
GPIO87/GPIO49
NONZP@
SPKR / GPIO81 :
1
0
NO
REBOOT
1: ENABLED
0: DISABLED (Have internal PD)
GPIO88
TOUCH SKU
None TOUCH SKU
0
1
+3VALW _PCH
PCH_GPIO86
R273 1 @
2 1K_0402_5%
PCH_GPIO66
R247 1
2 10K_0402_5%
GPIO15 : TLS Confidentiality
GSPI0_MOSI / GPIO86 : Boot BIOS Strap
1: Intel ME TLS with confidentiality
1: ENABLED
0: Intel ME TLS with no confidentiality
0: SPI ROM (Have internal PD)
(Have internal PD)
2013/09/25
Deciphered Date
2 1K_0402_1%
1: ENABLED (Have internal PU)

0: DISABLED

2016/09/25
5
SDIO_D0 / GPIO66 : Top-Block Swap Override
Compal Secret Data
Issued Date
R270 1
EC_LID_OUT#
Title
HSW MCP(6/11) GPIO,LPIO
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
1
10
of
52
UC1K
PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_P0
1
1
PCIE_CTX_C_GRX_N0 C78
PCIE_CTX_C_GRX_P0 C79
PCIE_GTX_C_CRX_N[0..3]
PCIE_GTX_C_CRX_P[0..3]
D
PCIE_CTX_C_GRX_N[0..3]
PCIE_CTX_C_GRX_P[0..3]
2 VGA@
2 VGA@
.1U_0402_16V7K
.1U_0402_16V7K
<18>
<18>
PEG_HTX_GRX_N0
PEG_HTX_GRX_P0
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_P1
<18>
<18>
1
1
2 VGA@
2 VGA@
.1U_0402_16V7K
.1U_0402_16V7K
PEG_HTX_GRX_N1
PEG_HTX_GRX_P1
F10
E10
C23
C22
F8
E8
B23
A23
PCIE_GTX_C_CRX_N2 H10
PCIE_GTX_C_CRX_P2 G10
1
1
2 VGA@
2 VGA@
.1U_0402_16V7K
.1U_0402_16V7K
PEG_HTX_GRX_N2
PEG_HTX_GRX_P2
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_P3
1
1
PCIE LAN
WLAN NGFF type
<33>
<33>
PCIE_PRX_C_LANTX_N3
PCIE_PRX_C_LANTX_P3
<33>
<33>
PCIE_PTX_C_LANRX_N3
PCIE_PTX_C_LANRX_P3
<32>
<32>
PCIE_PRX_W LANTX_N4
PCIE_PRX_W LANTX_P4
<32>
<32>
2 VGA@
2 VGA@
.1U_0402_16V7K
.1U_0402_16V7K
PEG_HTX_GRX_N3
PEG_HTX_GRX_P3
B21
C21
E6
F6
B22
A21
G11
F11
C155
C160
1
1
2 0.1U_0402_16V7K PCIE_PTX_LANRX_N3
2 0.1U_0402_16V7K PCIE_PTX_LANRX_P3
C29
B30
F13
G13
C156
C157
PCIE_PTX_C_W LANRX_N4
PCIE_PTX_C_W LANRX_P4
1
1
2 0.1U_0402_16V7K PCIE_PTX_W LANRX_N4 B29

2 0.1U_0402_16V7K PCIE_PTX_W LANRX_P4 A29
G17
F17
C30
C31
PCIE Card Reader
<37>
<37>
PCIE_PRX_C_CRTX_N2
PCIE_PRX_C_CRTX_P2
<37>
<37>
PCIE_PTX_C_CRRX_N2
PCIE_PTX_C_CRRX_P2
F15
G15
C163
C161
1
1
2 0.1U_0402_16V7K PCIE_PTX_CRRX_N2
2 0.1U_0402_16V7K PCIE_PTX_CRRX_P2
B31
A31
HASWELL_MCP_E
PERN5_L0
PERP5_L0
USB2N0
USB2P0
PETN5_L0
PETP5_L0
USB2N1
USB2P1
PERN5_L1
PERP5_L1
USB2N2
USB2P2
PETN5_L1
PETP5_L1
USB2N3
USB2P3
PERN5_L2
PERP5_L2
USB2N4
USB2P4
PETN5_L2
PETP5_L2
USB2N5
USB2P5
PERN5_L3
PERP5_L3
USB2N6
USB2P6
PETN5_L3
PETP5_L3
USB2N7
USB2P7
PERN3
PERP3
USB3.0 P1
PETN3
PETP3
USB
PCIe
USB3.0 P2
PETN4
PETP4
R232
2 3.01K_0402_1%
@ E15
@ E13
A27
B27
USB3RN1
USB3RP1
USB3TN1
USB3TP1
PERN4
PERP4
USB3RN2
USB3RP2
USB3TN2
USB3TP2
AN8
AM8
AR7
AT7
AR8
AP8
USB20_N0
USB20_P0
<34>
<34>
USB-Right1
USB20_N1
USB20_P1
<34>
<34>
USB-Right2
USB20_N2
USB20_P2
<33>
<33>
USB-Left1
AR10
AT10
AM15
AL15
AM13
AN13
USB20_N4
USB20_P4
<32>
<32>
WiMAX / BT
USB20_N5
USB20_P5
<27>
<27>
Touch Screen
USB20_N7
USB20_P7
<27>
<27>
Camera
AP11
AN11
AR13
AP13
G20
H20
C33
B34
E18
F18
B33
A33
PERN1/USB3RN3
PERP1/USB3RP3
U3RXDN2
U3RXDP2
<34>
<34>
U3TXDN2
U3TXDP2
<34>
<34>
C
USB3.0 P3 / PCIE P1
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
USB3.0 P4 / PCIE P2
USBRBIAS
USBRBIAS
RSVD
RSVD
PETN2/USB3TN4
PETP2/USB3TP4
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
+1.05VS_AUSB3PLL
T33
T34
PCIE_RCOMP
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
11 OF 19
AJ10
USBRBIAS
AJ11
AN10 @
T35
AM10 @
T36
AL3
AT1
AH2
AV3
R154 1
2 22.6_0402_1%
CAD note:
Route single-end 50-ohms and max 450-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils
USB_OC#0_R
R167 1
2 0_0402_5%
USB_OC#2_R
R168 1
1
R234
2 0_0402_5%
2
10K_0402_5%
USB_OC#0 <10,34,36>
USB_CHG_OC# <8>
USB_OC#2 <10,33,36>
+3VALW _PCH
USB-Right
USB-Left
Rev1p2
Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
5
Title
HSW MCP(7/11) PCIE,USB
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
1
11
of
52
UC1L
T37
T38
+1.35V
@
@
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
+CPU_CORE
T107
T39
T40
@
@
VCC_SENSE_R
T41
+VCCIO_OUT
T42
T44
+VCCIOA_OUT
F59
N58
AC58
E63
AB23
A59
E20
AD23
AA23
AE59
L62
N63
L63
B59
F60
C59
H_CPU_SVIDALRT#
<47>
VR_SVID_CLK
VIDSOUT
VCCST_PG_EC_R
+3VS
U18
<36>
VCCST_PG_EC
NC
VCC
A
Y
R309
10K_0402_5%
5
4
<47> VR_ON
<47> VGATE
+3VALW _PCH
R422
100K_0402_5%
@
VCCST_PG_EC_R
C167
2 0.1U_0402_16V7K
@
T131
@ CPU_PW R_DEBUG
R166
0_0402_5%
1
2
@
GND
74AUP1G07GW _TSSOP5
VCCST_PWRGD
T45
T46
T47
T48
T98
T142
T143
T144
T141
T140
T147
T145
T146
<36,44>
C168
0.1U_0402_16V7K
@
+1.05VS_VTT
SVID ALERT
@
@
@
@
@
@
@
@
@
@
@
@
@
AC22
AE22
AE23
+CPU_CORE
+1.05VS_VTT
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
Reserved Only
2
+1.05VS_VTT
Place the PU
resistors close to CPU
AB57
AD57
AG57
C24
C28
C32
R171
75_0402_1%
<47>
VR_SVID_ALRT#
R172
43_0402_1%
2
1
HASWELL_MCP_E
RSVD
RSVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
HSW ULT POWER
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
H_CPU_SVIDALRT#
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
Rev1p2
12 OF 19
+1.35V
L59
J58
+1.35V
SVID DATA
VDDQ DECOUPLING
+1.05VS_VTT
22U_0603_6.3V6M
CC53
22U_0603_6.3V6M
CC54
1
2
C17
10U_0603_6.3V6M
C19
10U_0603_6.3V6M
C15
10U_0603_6.3V6M
C14
10U_0603_6.3V6M
C13
10U_0603_6.3V6M
C12
10U_0603_6.3V6M
VR_SVID_DAT
C11
2.2U_0402_6.3V6M
2
VIDSOUT
C10
2.2U_0402_6.3V6M
<47>
2 Rshort@ 1
R174
0_0402_5%
C9
2.2U_0402_6.3V6M
R173
130_0402_1%
C8
2.2U_0402_6.3V6M
Place the PU
resistors close to CPU
+CPU_CORE
R177
100_0402_1%
Note: 0 ohm PLACED CLOSE TO CPU

2
VCC_SENSE_R
2 Rshort@ 1 R178
0_0402_5%
VCC_SENSE
+1.35V : 470UF/2V/7343 *2
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4
<47>
2 Rshort@ 1 R235
0_0402_5%
VSS_SENSE
<47>
VSS_SENSE_R
Compal Secret Data
R233
100_0402_1%
2013/09/25
Issued Date
2
<14>
Deciphered Date
2016/09/25
4
Title
HSW MCP(8/11) Power
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
1
12
of
52
Near K9
1@
Near L10
+1.05VS_AUSB3PLL
+1.05VS_ASATA3PLL
+3VALW _PCH
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
@ Y20
AA21
W21
T99
+1.05VS_APLLOPI
Near M9
HASWELL_MCP_E
C73
mPHY
VCCSUS3_3
VCCRTC
DCPRTC
RTC
SPI
RSVD
VCCAPLL
VCCAPLL
VCCSPI
OPI
VCCASW
VCCASW
+3VALW _PCH
+1.05VS_VTT
HDA --> 3.3V or 1.5V

I2C --> 1.8V
+1.05VS_AUSB3PLL
T105
J13
1
1
2 1U_0402_6.3V6K
2 22U_0603_6.3V6M
1 C38
1U_0402_6.3V6K
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
Near B11
R210 @
0_0805_5%
1
2
1
1
2 1U_0402_6.3V6K
2 22U_0603_6.3V6M
Near AC9
Near AH10
VRM/USB2/AZALIA
CORE
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
GPIO/LCC
THERMAL SENSOR
+3VS
Near AA21
C47
1
2
L3
C66
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%
1
1
2 1U_0402_6.3V6K
2 22U_0603_6.3V6M
J18
K19
A20
J17
R21
T21
@ K18
@ M20
V21
AE20
AE21
+1.05VS_AXCK_DCB
+1.05VS_AXCK_LCPLL
+1.05VS_VTT
+1.05VS_VTT
Near V8
DCPSUS2
+3VALW _PCH
C39
1 22U_0603_6.3V6M
AC9
AA9
C59 @
1 0.1U_0402_16V7K
AH10
V8
C61
1 22U_0603_6.3V6M
W9
+1.05VS_APLLOPI
AXALIA/HDA
VCCHDA
@ AH13
T116
+1.05VS_ASATA3PLL
C46
1
2
L2
C65
Idc 1.2A Rdc 0.11ohm +/-30%
AH14
Near J17
+1.05VS_AXCK_DCB
Near R21
C57
1 1U_0402_6.3V6K
C56
1 1U_0402_6.3V6K
2
2
T100
T101
Near J18
C48
1
2
L4
C67
Idc 1.2A Rdc 0.11ohm +/-30%
1
1
2 1U_0402_6.3V6K
2 22U_0603_6.3V6M
+3VALW _PCH
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
2 1U_0402_6.3V6K
AH11
AG10
AE7 +VCCRTCEXT 1
C54
+3VALW _PCH
Y8
1 0.1U_0402_16V7K
C58
SDIO/PLSS
VCCTS1_5
VCC3_3
VCC3_3
VCCSDIO
VCCSDIO
+RTCVCC
0.1U_0402_16V7K
2
@
AG14
AG13
2
D
+1.05VS_VTT
+1.05VS_VTT
USB3
DCPSUS3
Near B18
C42
1
2
L1
C64
Idc 1.2A Rdc 0.11ohm +/-30%
+RTCVCC
0.1U_0402_16V7K
C50
C70
1U_0402_6.3V6K
K9
L10
M9
N8
P9
B18
B11
0.1U_0402_16V7K
C51
UC1M
C20
1U_0402_6.3V6K
C21
1U_0402_6.3V6K
+1.05VS_VTT
1U_0402_6.3V6K
C52
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
C81
C84
C40
1
1
1
2 10U_0603_6.3V6M
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
C41
1U_0402_6.3V6K
1
2
+PCH_VCCDSW
C53
C37
@
1
1
2 22U_0805_6.3V6M
2 1U_0402_6.3V6K
+1.05VS_VTT
C69
2 0.47U_0402_16V4Z
+3VALW _PCH
T108
Near AG19
J15
K14
K16
U8
T9
C55
2 0.1U_0402_16V7K
C44 1
1U_0402_6.3V6K
+1.5VS
+3VS
+3VS
C
LPT LP POWER
SUS OSCILLATOR
USB2
DCPSUS4
RSVD
VCC1_05
VCC1_05
AB8 @
AC20
AG16
AG17
T137
@
T103
+1.05VS_VTT
C45 1
1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL
Near A20
C49
1
2
L5
C68
Idc 1.2A Rdc 0.11ohm +/-30%
1
1
13 OF 19
Rev1p2
2 1U_0402_6.3V6K
2 22U_0603_6.3V6M
+3VALW to +3VALW_PCH
B
+3VALW
+3VALW _PCH
@
2
PJ2
1
1 JUMP_43X39
Q10
@ AO3413_SOT23
D
<38>
PCH_PW R_EN#
PCH_PW R_EN#
2
RH3
CH113
CH112
@
0.1U_0402_10V7K
0.01U_0402_25V7K
0.1U_0402_25V6
CH111
1
47K_0402_5%
Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
5
Title
HSW MCP(9/11) Power
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
1
13
of
52
@
UC1N
D
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
@
HASWELL_MCP_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
UC1O
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
14 OF 19
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
@
HASWELL_MCP_E
UC1P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
15 OF 19 Rev1p2 VSS
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HASWELL_MCP_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
16 OF 19 Rev1p2 VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
V58
AH46
V23
E62
AH16
VSS_SENSE_R
<12>
Rev1p2
Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
5
Title
HSW MCP(10/11) GND
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
1
14
of
52
UC1Q
T49
T50
AY2
DC_TEST_AY2_AW 2
AY3
DC_TEST_AY3_AW 3
AY60
@
DC_TEST_AY61_AW 61 AY61
DC_TEST_AY62_AW 62 AY62
B2
@
B3
DC_TEST_A3_B3
B61
DC_TEST_A61_B61
B62
DC_TEST_B62_B63
B63
C1
DC_TEST_C1_C2
C2
DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
HASWELL_MCP_E
UC1R
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
17 OF 19 Rev1p2DAISY_CHAIN_NCTF_AW63
A3
A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
DC_TEST_A3_B3
@
@
DC_TEST_A61_B61
@
@
@
DC_TEST_AY2_AW 2
DC_TEST_AY3_AW 3
DC_TEST_AY61_AW 61
DC_TEST_AY62_AW 62
@
T58
T59
T60
T61
T62
T51
T52
T53
T54
@
@
@
@
AT2
AU44
AV44
D15
T55
T56
T57
@
@
@
F22
H22
J21
HASWELL_MCP_E
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
T63
@
@
@
@
@
@
@
@
@
@
@
T128
T127
T129
T126
@
@
@
@
CFG16
CFG18
CFG17
CFG19
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
AA62
U63
AA61
U62
V63
CFG_RCOMP
T90
A5
T91
T92
T93
T94
TD_IREF
@
@
@
@
E1
D1
J20
H18
B12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
@
@
@
@
@
@
@
T68
T69
T70
T71
T72
T73
T74
HASWELL_MCP_E
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RESERVED
RSVD
RSVD
RSVD
PROC_OPI_RCOMP
CFG16
CFG18
CFG17
CFG19
RSVD
RSVD
CFG_RCOMP
VSS
VSS
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
AV63
AU63
@
@
T75
T76
C63
C62
B43
@
@
@
T77
T78
T79
A51
B51
@
@
T80
T81
L60
T82
N60
T83
W23
Y22
AY15
@
@
T84
T85
OPI_COMP
AV62
D58
@
@
T86
T87
@
@
T88
T89
CFG Straps for Processor

C
CFG3
T113
T117
T115
T119
T118
T121
T120
T124
T122
T125
T123
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
AL1
AM11
AP7
AU10
AU15
AW14
AY14
R224
1K_0402_1%
@
@
@
@
T64
T65
T66
T67
Physical Debug Enable
P22
N21
P20
R20
(DFX Privacy)
1: DISABLED
CFG3
0: ENABLED; SET DFX ENABLED BIT

IN DEBUG INTERFACE MSR
CFG4
T110
T109
T112
@
@
@
@
Rev1p2
18 OF 19
UC1S
N23
R23
T23
U10
Rev1p2
19 OF 19
R225
1K_0402_5%
1
CFG_RCOMP
49.9_0402_1%
1
OPI_COMP
49.9_0402_1%
1
TD_IREF
8.2K_0402_5%
R222
2
R223
2
R226
Display Port Presence Strap
1 : Disabled; No Physical Display Port

attached to Embedded Display Port
CFG4
0 : Enabled; An external Display Port device is

connected to the Embedded Display Port
Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
5
Title
HSW MCP(11/11) RSVD
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
1
15
of
52
+1.35V
+1.35V
JDIMM1
DDR_A_D44
DDR_A_D41
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47
+1.35V
All VREF traces should

have 10 mil trace width
Layout Note:
Place near JDIMM1
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
C110
1U_0402_6.3V6K
C109
1U_0402_6.3V6K
C108
1U_0402_6.3V6K
C107
1U_0402_6.3V6K
<6>
DDRA_CKE0_DIMMA
<6>
DDR_A_BS2
DDRA_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
+1.35V
DDR_A_MA3
DDR_A_MA1
C114
10U_0603_6.3V6M
C113
10U_0603_6.3V6M
C112
10U_0603_6.3V6M
C111
10U_0603_6.3V6M
<6>
<6>
<6>
SA_CLK_DDR0
SA_CLK_DDR#0
SA_CLK_DDR0
SA_CLK_DDR#0
<6>
DDR_A_BS0
DDR_A_MA10
DDR_A_BS0
<6>
<6>
DDR_A_WE#
DDR_A_CAS#
DDR_A_WE#
DDR_A_CAS#
DDRA_CS1_DIMMA#
DDR_A_MA13
DDRA_CS1_DIMMA#
+1.35V
1
@
2
C117
10U_0603_6.3V6M
C116
10U_0603_6.3V6M
C115
10U_0603_6.3V6M
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6
DDR_A_D21
DDR_A_D20
DDR_A_D17
DDR_A_D16
+0.675VS
DDR_A_DQS#4
DDR_A_DQS4
C124
1U_0402_6.3V6K
C123
1U_0402_6.3V6K
C122
1U_0402_6.3V6K
C121
1U_0402_6.3V6K
DDR_A_D36
DDR_A_D33
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D58
DDR_A_D60
DDR_A_D61
Layout Note:
Place near JDIMM1.203,204
+3VS
205
207
R212
0_0402_5%
Rshort@
R211
0_0402_5%
Rshort@
C125
0.1U_0402_16V7K
+0.675VS
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
GND1
BOSS1
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
+5VS
U45
1
<5>
DIMM_DRAMRST#
DDR_PG_CTRL
DIMM_DRAMRST#
NC
A
<17,5>
VCC
5
1
DDR_A_D25
DDR_A_D24
GND
74AUP1G07GW_TSSOP5
DDR_A_D27
DDR_A_D26
DDR_A_D45
DDR_A_D40
SA_ODT0
+1.35V
R191
R188 1
66.5_0402_1%
100K_0402_5%
Q20
LBSS138LT1G_SOT-23-3
D
R189 1
2
66.5_0402_1%
G
S
R190 1
M_A_B_DIMM_ODT
66.5_0402_1%
SA_ODT1
SB_ODT0
SB_ODT1
DDR_VTT_PG_CTRL
DDR_A_DQS#[0..7]
DDR_A_D[0..63]
DDR_A_D52
DDR_A_D53
SB_ODT0
<17>
SB_ODT1
<17>
<43>
<6>
<6>
DDR_A_MA[0..15]
<6>
DDR_A_DQS#6
DDR_A_DQS6
Place near DDR connector for DQA easy access
DDR_A_D54
DDR_A_D55
<36,37>
DDRA_CKE1_DIMMA
ON/OFFBTN#
1
R8
2
0_0805_5%
<6>
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
2
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
SA_CLK_DDR1
SA_CLK_DDR#1
SA_CLK_DDR1
SA_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_A_BS1
<6>
DDR_A_RAS#
<6>
DDRA_CS0_DIMMA#
SA_ODT0
<6>
<6>
DDRA_CS0_DIMMA#
+1.35V
<6>
R56
1.8K_0402_1%
SA_ODT1
+VREF_CA
DDR_A_D5
DDR_A_D4
1
DDR_A_D3
DDR_A_D7
DDR_A_D18
DDR_A_D19
DDR_A_DQS#2
DDR_A_DQS2
R296
1
2
2_0402_1%
SM_DIMM_VREFCA
@
R295
1.8K_0402_1%
<6>
C162
0.022U_0402_25V7K
R294
24.9_0402_1%
Note: Depend on Project

3
DDR_A_D22
DDR_A_D23
+VREF_CA
<17>
DDR_A_D37
DDR_A_D32
DDR_A_D35
DDR_A_D39
DDR_A_D63
DDR_A_D59
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D56
DDR_A_D57
PM_SMBDATA <17,37,8>
PM_SMBCLK <17,37,8>
+0.675VS
206
208
LCN_DAN06-K4406-0103
@
Channel A
4
<Address: SA1:SA0=00>
DIMM_1 REV H:4mm

Issued Date
Compal Secret Data
2013/09/25
2016/09/25
Deciphered Date
Title
DDRIII DIMMA
Size
Document Number
Custom
Rev
1.0
Date:
<6>
DDR_A_DQS[0..7]
DDR_A_D42
DDR_A_D46
DDRA_CKE1_DIMMA
R187 1
66.5_0402_1%
2
2
DDR_A_D15
DDR_A_D11
C120
0.1U_0402_16V7K
DDR_A_D0
DDR_A_D1
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR3 SO-DIMM A
Reverse Type
H=4.0mm
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D30
DDR_A_D31
DDR_A_D9
DDR_A_D12
DDR_A_DQS#3
DDR_A_DQS3
R176
24.9_0402_1%
@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
DDR_A_D29
DDR_A_D28
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
DDR_A_D14
DDR_A_D10
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
1
R185
1.8K_0402_1%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDR_A_D13
DDR_A_D8
C106
0.1U_0402_16V7K
@
C158
0.022U_0402_25V7K
+V_DDR_REFA
R54
1.8K_0402_1%
1
SA_DIMM_VREFDQ
+1.35V
C34
0.1U_0402_16V7K
<6>
R293
2_0402_1%
1
2
+1.35V
Sheet
E
16
of
52
+1.35V
+1.35V
JDIMM2
1
R213
1.8K_0402_1%
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
R179
24.9_0402_1%
@
DDR_B_D10
DDR_B_D11
C128
0.1U_0402_16V7K
@
C159
0.022U_0402_25V7K
R297
2_0402_1%
2
DDR_B_D8
DDR_B_D14
SB_DIMM_VREFDQ
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
+V_DDR_REFB
R57
1.8K_0402_1%
<6>
DDR_B_D26
DDR_B_D27
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D42
+1.35V
All VREF traces should

have 10 mil trace width
Layout Note:
Place near JDIMM1
DDR_B_D56
DDR_B_D57
DDR_B_D59
DDR_B_D58
C132
1U_0402_6.3V6K
C131
1U_0402_6.3V6K
C130
1U_0402_6.3V6K
C129
1U_0402_6.3V6K
<6>
DDRB_CKE0_DIMMB
<6>
DDR_B_BS2
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
+1.35V
DDR_B_MA3
DDR_B_MA1
C136
10U_0603_6.3V6M
C135
10U_0603_6.3V6M
C134
10U_0603_6.3V6M
C133
10U_0603_6.3V6M
<6>
<6>
<6>
SB_CLK_DDR0
SB_CLK_DDR#0
SB_CLK_DDR0
SB_CLK_DDR#0
<6>
DDR_B_BS0
DDR_B_MA10
DDR_B_BS0
<6>
<6>
DDR_B_WE#
DDR_B_CAS#
DDR_B_WE#
DDR_B_CAS#
DDRB_CS1_DIMMB#
DDR_B_MA13
DDRB_CS1_DIMMB#
+1.35V
DDR_B_D4
DDR_B_D1
1
@
2
C139
10U_0603_6.3V6M
C138
10U_0603_6.3V6M
C137
10U_0603_6.3V6M
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D3
DDR_B_D7
DDR_B_D21
DDR_B_D20
DDR_B_D22
DDR_B_D23
+0.675VS
DDR_B_D35
DDR_B_D39
DDR_B_D52
DDR_B_D49
+3VS
DDR_B_DQS#4
DDR_B_DQS4
C146
1U_0402_6.3V6K
C145
1U_0402_6.3V6K
C144
1U_0402_6.3V6K
C143
1U_0402_6.3V6K
DDR_B_D36
DDR_B_D33
Layout Note:
Place near JDIMM1.203,204
DDR_B_D48
DDR_B_D53
R229
10K_0402_5%
+3VS
+0.675VS
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
GND1
BOSS1
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_B_D12
DDR_B_D9
DDR_B_DQS#[0..7]
<6>
DDR_B_DQS[0..7]
<6>
DDR_B_D[0..63]
DDR_B_DQS#1
DDR_B_DQS1
<6>
DDR_B_MA[0..15]
<6>
DDR_B_D13
DDR_B_D15
DDR_B_D25
DDR_B_D24
DIMM_DRAMRST#
DIMM_DRAMRST#
<16,5>
DDR_B_D30
DDR_B_D31
DDR3 SO-DIMM B
Reverse Type
H=4.0mm
DDR_B_D45
DDR_B_D44
DDR_B_D47
DDR_B_D43
DDR_B_D61
DDR_B_D60
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D63
DDR_B_D62
DDRB_CKE1_DIMMB
DDRB_CKE1_DIMMB
<6>
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
2
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
SB_CLK_DDR1
SB_CLK_DDR#1
SB_CLK_DDR1
SB_CLK_DDR#1
DDR_B_BS1
DDR_B_RAS#
DDR_B_BS1
<6>
DDR_B_RAS#
<6>
DDRB_CS0_DIMMB#
SB_ODT0
DDRB_CS0_DIMMB#
SB_ODT0 <16>
SB_ODT1
SB_ODT1
<6>
<6>
<6>
<16>
+VREF_CA
+VREF_CA
<16>
DDR_B_D5
DDR_B_D0
1
DDR_B_D2
DDR_B_D6
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2

3
DDR_B_D19
DDR_B_D18
DDR_B_D37
DDR_B_D32
DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
PM_SMBDATA <16,37,8>
PM_SMBCLK <16,37,8>
+0.675VS
206
208
205
207
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
C142
0.1U_0402_16V7K
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDRB_CKE0_DIMMB
+1.35V
R231
0_0402_5%
Rshort@
C147
0.1U_0402_16V7K
LCN_DAN06-K4406-0103
@
Channel B
4
<Address: SA1:SA0=10>
DIMM_2 REV H:4mm
Issued Date
Compal Secret Data
2013/09/25
2016/09/25
Deciphered Date
Title
DDRIII DIMMB
Size
Document Number
Custom
Rev
1.0
Date:
Sheet

E
17
of
52
UV1A
<11>
<11>
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
<11>
<11>
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
<11>
<11>
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
<11>
<11>
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
AF30
AE31
AE29
AD28
AD30
AC31
AC29
AB28
AB30
AA31
AA29
Y28
Y30
W31
W29
V28
V30
U31
U29
T28
R29
P28
P30
N31
N29
M28
M30
L31
L29
K30
AC Coupling Capacitor
PCIe Gen3: Recommended value is 220 nF
PCIe Gen1 and Gen2 only: Recommended value is 100 nF
PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
PCIE_RX4P
PCIE_RX4N
PCIE_TX4P
PCIE_TX4N
PCIE_RX5P
PCIE_RX5N
PCIE_TX5P
PCIE_TX5N
PCIE_RX6P
PCIE_RX6N
PCIE_TX6P
PCIE_TX6N
PCIE_RX7P
PCIE_RX7N
PCIE_TX7P
PCIE_TX7N
NC#V30
NC#U31
NC#W24
NC#W23
NC#U29
NC#T28
NC#V27
NC#U26
PCI EXPRESS INTERFACE
T30
R31
NC#T30
NC#R31
NC#R29
NC#P28
NC#U24
NC#U23
NC#T26
NC#T27
NC#P30
NC#N31
NC#T24
NC#T23
NC#N29
NC#M28
NC#P27
NC#P26
NC#M30
NC#L31
NC#P24
NC#P23
NC#L29
NC#K30
NC#M27
NC#N26
AH30
AG31
PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0
.1U_0402_16V7K
.1U_0402_16V7K
2
2
1 VGA@
1 VGA@
CV1
CV2
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0
AG29
AF28
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
.1U_0402_16V7K
.1U_0402_16V7K
2
2
1 VGA@
1 VGA@
CV3
CV4
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
AF27
AF26
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
.1U_0402_16V7K
.1U_0402_16V7K
2
2
1 VGA@
1 VGA@
CV5
CV6
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
AD27
AD26
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3
.1U_0402_16V7K
.1U_0402_16V7K
2
2
1 VGA@
1 VGA@
CV7
CV8
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0
<11>
<11>
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
<11>
<11>
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
<11>
<11>
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3
<11>
<11>
LVDS Interface
AC25
AB25
UV1F
+VGA_CORE
Y23
Y24
VARY_BL
DIGON
AB27
AB26
Y27
Y26
TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N
W24
W23
TX1P_DPA1P
TX1M_DPA1N
V27
U26
TX2P_DPA0P
TX2M_DPA0N
U24
U23
NC_TXOUT_L3P
NC_TXOUT_L3N
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_PCIE_VGA#
AK30
AK32
Topaz
AL15
AK14
AH16
AJ15
B
AL17
AK16
AH18
AJ17
AL19
AK18
TMDP
T26
T27
TXCBP_DPB3P
TXCBM_DPB3N
T24
T23
TX3P_DPB2P
TX3M_DPB2N
P27
P26
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
P24
P23
NC_TXOUT_U3P
NC_TXOUT_U3N
M27
N26
AH20
AJ19
AL21
AK20
AH22
AJ21
AL23
AK22
AK24
AJ23
C
@
<8>
<8>
AB11
AB12
2160856030-A0_FCBGA631
CLOCK
PCIE_REFCLKP
PCIE_REFCLKN
+0.95VGS
CALIBRATION
PCIE_CALR_TX
PCIE_CALR_RX
Y22
VGA_PCIE_CALRP
RV1
1 VGA@
2 1.69K_0402_1%
AA22
VGA_PCIE_CALRN
RV3
1 VGA@
2 1K_0402_1%
+3VGS
For CRB reserved
PERSTB
2160856030-A0_FCBGA631
PLT_RST#
<48,9>
+3VGS
1
2
DGPU_PW RGD
IN1
IN2
DGPU_PW ROK_R
DGPU_PW ROK
<48>
0_0402_5%
RV56
100K_0402_5%
@
IN1
IN2
UV8
VGA@
OUT
PLTRST_VGA#
DGPU_HOLD_RST#
RV52
100K_0402_5%
VGA@
Compal Secret Data
2013/09/25
Issued Date
<10,9>
PLT_RST#
GND
<36,9>
VCC
UV11
@
@
RV167
OUT
AL27
TEST_PG
PLTRST_VGA#
N10
VCC
2 1K_0402_5%
GND
1 VGA@
RV2
Deciphered Date
2016/09/25
1

PCIE/LVDS
Size
Document Number
Custom
ZSWAA/ZCWAA
LA-B301P
Date:
Sheet
18
of
52
Title
Rev
1.0
UV1B
NC#AK5
NC#AM3
NC#AK6
NC#AM5
DPB
NC#AJ7
NC#AH6
NC#AK8
NC#AL7
+3VGS
W6
V6
JTAG_TRSTB
JTAG_TDI
JTAG_TMS
JTAG_TCK
AC6
AC5
AA5
AA6
10K_8P4R_5%
NC#W6
NC#V6
NC#V4
NC#U5
NC#AC5
NC#AC6
NC#AA5
NC#AA6
NC#W3
NC#V2
DPC
NC#Y4
NC#W5
@
TV25
BP_0
FB_VDDCI
BP_1
@
TV26
PLL_Analog_in
RP1
+3VGS
8
7
6
5
GPU_DOWN#
VGA_SMB_CK2
VGA_SMB_DA2
NC#U1
NC#W1
NC#U3
NC#Y6
NC#AA1
47K_0804_8P4R_5%
VGA@
U6
U10
T10
U8
U7
T9
(From <36>
EC)
GPU_DOWN#
T8
PCC_GPIO_6
T7
P10
P4
P2
N6
+VGA_CORE
N5
N3
Y9
N1
GPU_VID3
M4
R6
@
W10
10K_0402_5%
1
2
M2
GPIO19_CTF
RV8
P8
GPU_VID1
P7
N8
AK10
AM10
@
1 RV162 2
N7
CLK_REQ_VGA#_R
CLK_REQ_VGA#
0_0402_5%
L6
JTAG_TRSTB
L5
JTAG_TDI
L3
JTAG_TCK
L1
JTAG_TMS
1 JTAG_TDO
K4
TV22
K7
TESTEN
AF24
+VGA_CORE
+1.8VGS
RV82 2 TOPAZ@1 4.7K_0402_5%
BP_0
RV81 2 TOPAZ@1 4.7K_0402_5%
BP_1
<8>
2 10K_0402_5%
AB13
W8
W9
W7
AD10
AJ9
AL9
GPIO_28_FDO
Enable MLPS:
- Install on Jet/Sun
- DNI for Topaz
@
TV27
TV23
1
1
PX_EN
AC14
AB16
R
AVSSN#AK26
GPIO_0
GPIO_1
GPIO_2
SMBDATA
SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
GPIO_29
GPIO_30
CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
TESTEN
NC#AF24
G
AVSSN#AJ25
B
AVSSN#AG25
DAC1
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
FutureASIC/SEYMOUR/PARK
CEC_1
RSVD#AK12
RSVD#AL11
RSVD#AJ11
GENLK_CLK
GENLK_VSYNC
SWAPLOCKA
SWAPLOCKB
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE
NC#AJ9
NC#AL9
PS_0
PS_1
PS_2
HPD1
PX_EN
PS_3
+3VGS
TS_A
RV77
RV78
JET@
33_0402_5%
1
2
SVI2_SVD
1
2
SVI2_SVC
SVI2_SVD
SVI2_SVC
<48>
<48>
33_0402_5%JET@
RV74
10K_0402_5%
@
3.3V TO 1.8V LEVEL SHIF

For JET/SUN to support SVI2 reaulator
DNI for TOPAZ
1 0.1U_0402_10V7K
JET@
+1.8VGS +1.8VGS
RV83
16.2K_0402_1%
TOPAZ@
+VGA_CORE
VCCSENSE_VGA JET@ 1 RV161
VSSSENSE_VGA JET@ 1 RV160
RV84
10K_0402_5%
TOPAZ@
2 0_0402_5%
2 0_0402_5%
RV87
10K_0402_5%
@
FB_GND TOPAZ@
FB_VDDC TOPAZ@
SVI2_SVD
SVI2_SVC
AM26
AK26
1 RV158
1 RV159
2 0_0402_5%
2 0_0402_5%
VSSSENSE_VGA
VCCSENSE_VGA
<48>
<48>
B
AL25
AJ25
50 ohm trace for diffenent pair
AH24
AG25
RV89
10K_0402_5%
@
RV88
10K_0402_5%
TOPAZ@
WAKE#
AD22
RV163
4.7K_0402_5%
VGA@
AE23
AD23
Pull down for

none OBFF design.
AMD SVI2 Master Interface

Pin Name
GPIO_SVC
TOPAZ@1 RV155
TOPAZ@1 RV156
TOPAZ@1 RV157
2 0_0402_5% SVI2_SVD
2 0_0402_5% SVI2_SVT
2 0_0402_5% SVI2_SVC
SVI2_SVT
Type
PD/PU
I/O
1.8 V
(VDD_GPIO18)
AM12
AK12
AL11
AJ11
8
7
6
4
PLL_ANALOG_OUT
J8
AG24
AE22
VCCB
B1
B2
GND
SN74LVC2T45DCTR_SM8
CV167
AH26
AJ27
JET@
VCCA
A1
A2
DIR
JET@
CV169
10U_0603_6.3V6M
2
1
Description
Serial VID clock.
Push-pull clock output for the SVI2 data bus;
driven by the GPU. Point-to-point connection to
the SVI2 voltage regulator controller.
PU
<48>
Topaz SVI2
Add test point on

PX_EN for debug.
AC16
JET@
SCL
SDA
GENERAL PURPOSE I/O
10K_0402_5%
1 DIR
Y4
W5
AA3
Y2
1
RV79 2
R1
R3
VGA_SMB_DA2
VGA_SMB_CK2
RV53 1 JET@
NC#J8
+3VGS
W3
V2
I2C
+VGA_CORE
NC#AA3
NC#Y2
V4
U5
1
2
3
4
U1
W1
U3
Y6
AA1
RV73
10K_0402_5%
JET@
AK8
AL7
@
8
7
6
5
AJ7
AH6
CV170
0.1U_0402_10V7K
1
UV9
AK6
AM5
JET@
1
2
3
5
JET@ 33_0402_5%
1
2
GPU_VID3 RV75
GPU_VID3_GPIO_15
1
2
GPU_VID1 RV76
GPU_VID1_GPIO_20
JET@ 33_0402_5%
DIR
AK5
AM3
RP2
1
2
3
4
AK3
AK1
QV1B
2N7002DW-T/R7_SOT363-6
VGA@
NC#AK3
NC#AK1
DVO
VGA_SMB_CK2
+1.8VGS
RV72
10K_0402_5%
JET@
EC_SMB_CK2
RV71
10K_0402_5%
@
0.1U_0402_10V7K
1
JET@
<36,8>
CV166
AH3
AH1
+3VGS +3VGS
NC#AH3
NC#AH1
AG3
AG5
QV1A
2N7002DW-T/R7_SOT363-6
VGA@
DPA
+3VGS
AF2
AF4
VGA_SMB_DA2
NC#AG3
NC#AG5
DBG_DATA16
DBG_DATA15
DBG_DATA14
DBG_DATA13
DBG_DATA12
DBG_DATA11
DBG_DATA10
DBG_DATA9
DBG_DATA8
DBG_DATA7
DBG_DATA6
DBG_DATA5
DBG_DATA4
DBG_DATA3
DBG_DATA2
DBG_DATA1
DBG_DATA0
EC_SMB_DA2
NC#AF2
NC#AF4
N9
L9
AE9
Y11
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7
2
<36,8>
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TV3
TV4
TV5
TV6
TV7
TV8
TV1
TV9
TV2
TV10
TV11
TV12
TV13
TV14
TV15
TV16
TV17
DBG_DATA[12:16]
Available on Jet/Sun
only, NC balls on Topaz.
+3VGS
AL13
AJ13
GPIO_SVD
I/O
1.8 V
(VDD_GPIO18)
GPIO_SVT
I/O
1.8 V
(VDD_GPIO18)
Serial VID data.

Push-pull data output for the SVI2 data bus; driven
by the GPU. Sets the voltage, power-state
indicator, load-line slope, and voltage offsets for
two voltage rails. Point-to-point connection to
the SVI2 voltage regulator controller.
PD
AG13
AH12
AC19
PS_0
<25>
AD19
PS_1
<25>
AE17
PS_2
<25>
AE20
PS_3
<25>
Serial VID telemetry.

Push-pull data input driven by the SVI2 voltage
regulator controller. Continuously streams the
voltage and current telemetry information to the GPU.
Also provides and indication when positive voltage
transitions are complete (VOTFC).
AE19
DBG_VREFG
+3VGS
Enable JTAG access
RV9
5.11K_0402_5%
@
TESTEN
Design
1
1
1
1
DDC/AUX
DDC1CLK
DDC1DATA
PLL/CLOCK
AUX1P
AUX1N
DDC2CLK
DDC2DATA
XTALIN
XTALOUT
RV23 1
RV24 1
2 10K_0402_5%
2 10K_0402_5%
@
@
XO_IN
XO_IN2
AC22
AB22
XTALIN
XTALOUT
AUX2P
AUX2N
XO_IN
XO_IN2
NC#AD20
NC#AC20
RV11
1K_0402_5%
VGA@
AM28
AK28
NC#AE16
NC#AD16
Reserved signal, for

normal ASIC operation.
SEYMOUR/FutureASIC
On-die thermal sensor power.
CV13
@
DPLUS
DMINUS
THERMAL
DDCVGACLK
DDCVGADATA
RV10 1
YV1
AD2
AD4
+VGA_CORE
4
XTALIN
AC11
AC13
AD13
AD11
AD20
AC20
VGA@ 2 1M_0402_5%
CV9
15P_0402_50V8J
VGA@
NC
OSC
RV91
10K_0402_5%
TOPAZ@
VGA@
OSC
NC
XTALOUT
27MHZ 10PF +-20PPM X3G027000DA1H
CV10
15P_0402_50V8J
1 VGA@
FB_GND
FB_VDDC
RV90
1
PCC_GPIO_6
2
CVT90
0.1U_0402_10V7K
1
TOPAZ@
OCP_L
OCP_L
<48>
1K_0402_5%
TOPAZ@
Peak Current Control (PCC) CKT

Reversed (Topaz only)
AE16
AD16
AC1
AC3
D
GPIO_28_FDO
+TSVDD
0.1U_0402_16V4Z
CV12
2
VGA@
1U_0402_6.3V6K
+TSVDD
VGA@ LV1
(1.8V@13mA TSVDD)
1
2
BLM15BD121SN1D_0402
1
1
1
CV11
+1.8VGS
10U_0603_6.3V6M
T4
T2
AE6
AE5
Ref.CRB
0
0
1
0
TSVDD
120ohm
0.1u
1u
10u
R5
AD17
AC17
GPIO28_FDO
TSVDD
TSVSS
2160856030-A0_FCBGA631
Compal Secret Data
Issued Date
2013/09/25
Deciphered Date
2016/09/25
Title

JET_MSIC
Custom
Rev
1.0
Date:
Sheet
5
19
of
52
UV1E
UV1G
+3VS to +3VGS (25mA)

+3VGS
1.8V@40mA
0.95V@32mA
AG20
AG21
AF22
AG22
AD14
+1.8VGS
+3VS
CV23
0.1U_0402_10V6K
VGA@
+0.95VGS
CV22
+3VGS
CV21
CV20
1U_0402_6.3V4Z
VGA@
3
QV3
VGA@
10U_0603_6.3V6M
VGA@
PXS_PW REN
2
2
1U_0402_6.3V4Z
VGA@
PXS_PW REN
<10,45,48,9>
2N7002DW-T/R7_SOT363-6
VGA@
QV2A
Vgs=-4.5V,Id=3A,Rds<97mohm
PXS_PW REN#
VGA@
CV19
0.01U_0402_25V7K
VGA@
RV21
47K_0402_5%
1
2
AO3413_SOT23
3 1
VGA@
QV2B
2N7002DW -T/R7_SOT363-6
2@
CV18
0.1U_0402_16V7K
VGA@
RV22
100K_0402_5%
VGA@
RV20
470_0805_5%
+3VALW
AG14
AH14
AM14
AM16
AM18
AF23
AG23
AM20
AM22
AM24
AF19
AF20
AE14
AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32
NC/DP POWER
DP POWER
AG15
AG16
AF16
AG17
AG18
AG19
AF14
DP_VDDR#AG15
DP_VDDR#AG16
DP_VDDR#AF16
DP_VDDR#AG17
DP_VDDR#AG18
DP_VDDR#AG19
DP_VDDR#AF14
NC#AE11
NC#AF11
NC#AE13
NC#AF13
NC#AG8
NC#AG10
DP_VDDC#AG20
DP_VDDC#AG21
DP_VDDC#AF22
DP_VDDC#AG22
DP_VDDC#AD14
NC#AF6
NC#AF7
NC#AF8
NC#AF9
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
NC#AE1
NC#AE3
NC#AG1
NC#AG6
NC#AH5
NC#AF10
NC#AG9
NC#AH8
NC#AM6
NC#AM8
NC#AG7
NC#AG11
DPAB_CALR
NC#AE10
AE11
AF11
AE13
AF13
AG8
AG10
AF6
AF7
AF8
AF9
AE1
AE3
AG1
AG6
AH5
AF10
AG9
AH8
AM6
AM8
AG7
AG11
M6
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U9
V13
V16
V18
Y10
Y15
Y17
Y20
R11
T11
AA11
M12
N11
V11
AF17
+1.35V to +1.35VGS (6.5A)

+1.35V
AE10
2160856030-A0_FCBGA631
2
RV164
VGA@
RV165
1 VGA@ 2
220K_0402_5%
B+
VGA@
RV166
820K_0402_5%
5 PXS_PW REN#
QV4B
2N7002DW -T/R7_SOT363-6
VGA@
VGA@
QV4A
2N7002DW -T/R7_SOT363-6
CV174
VGA@ 2
0.1U_0402_25V6
CV171
VGA@
1U_0402_6.3V6K
1
2
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS_MECH
VSS_MECH
VSS_MECH
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6
A32
AM1
AM32
QV5
VGA@
AO4354_SOIC-8
8
7
6
5
470_0805_5%
+1.35VGS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2160856030-A0_FCBGA631
Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
1

JET_Power/GND
Size
Document Number
Custom
ZSWAA/ZCWAASheet
LA-B301P
Date:
20
of
52
Title
Rev
1.0
PCIE_PVDD
1u
10u
Design
1
1
SPLL_VDDC
0.1u
1u
Jet CRB
1
1
Design
1
1
(VDDR3: 3V@25mA)
I/O
AA17
AA18
AB17
AB18
V12
Y12
U12
VDDR3
VDDR3
VDDR3
VDDR3
VDDR4
VDDR4
VDDR4
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
CV40
CV39
10U_0603_6.3V6M
VGA@
+0.95VGS
AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
AA12
M11
N12
U11
CV52
CV45
CV44
CV43
(PCIE_VDDC: 0.95V@1A)
1
1U_0402_6.3V4Z
VGA@
CORE
L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22
1U_0402_6.3V4Z
VGA@
VDD_CT
VDD_CT
VDD_CT
VDD_CT
+3VGS
CV48
Jet CRB
1
1
LEVEL
TRANSLATION
AA20
AA21
AB20
AB21
POWER
SPLL_PVDD
1u
10u
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26
1U_0402_6.3V4Z
VGA@
Design
1
2
1U_0402_6.3V4Z
VGA@
Jet CRB
1
2
1U_0402_6.3V4Z
VGA@
MPLL_PVDD
1u
10u
CV47
(VDDCT: 1.8V@13mA)
NC#AB23
NC#AC23
NC#AD24
NC#AE24
NC#AE25
NC#AE26
NC#AF25
NC#AG26
CV42
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
1U_0402_6.3V4Z
VGA@
CV37
CV38
PCIE_PVDD
1U_0402_6.3V4Z
VGA@
H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22
Design
6
1
(PCIE_PVDD: 1.8V@100mA)
CV41
MEM I/O
+1.8VGS
Jet CRB
6
1
+1.8VGS
AM30
10U_0603_6.3V6M
VGA@
2.2U_0402_6.3V5M
VGA@
CV36
CV35
CV34
CV32
2.2U_0402_6.3V5M
VGA@
Design
1
2.2U_0402_6.3V5M
VGA@
Jet CRB
1
2.2U_0402_6.3V5M
VGA@
VDDR3
1u
10U_0603_6.3V6M
VGA@
Design
1
(VDDR1: 1.35V@2A)
2.2U_0402_6.3V5M
VGA@
Jet CRB
1
PCIE_VDDC/BIF_VDDC
1u
10u
UV1D
+1.35VGS
0.1U_0402_10V6K
VGA@
CV33
VDD_CT
1u
Design
1
1
1U_0402_6.3V4Z
VGA@
Design
1
1
5
1
0.01U_0402_16V7K
VGA@
CV31
Jet CRB
1
1
5
1
PCIE
VDDR1
0.01u
0.1u
2.2u
10u
Jet CRB
1
1
CV46
1U_0402_6.3V4Z
VGA@
(Topaz XT VDDC: TBD@19.5A)

+VGA_CORE
(Jet Pro VDDC: 0.800V to 1.075V@18A)
Topaz XT (TDP 18W/DDR3): VDDC + VDDCI (Merged)@24A
Jet Pro (TDP 18W/DDR3): VDDC + VDDCI (Merged)@21A
PLL
+0.95VGS
C
BIF_VDDC
BIF_VDDC
+1.8VGS
L8
+VGA_CORE
LV4 VGA@
1
2
BLM15BD121SN1D_0402
+SPLL_PVDD
H7
(SPLL_VDDC: 0.95V@100mA )
+SPLL_VDDC
H8
CV56
J7
CV55
(SPLL_PVDD: 1.8V@75mA )
SPLL_PVDD
+0.95VGS
SPLL_VDDC
(Jet Pro VDDCI: 0.95V GDDR5@1125MHz 4.5A)
M13
M15
M16
M17
M18
M20
M21
N20
SPLL_PVSS
1
@
1U_0402_6.3V4Z
VGA@
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
2160856030-A0_FCBGA631
0.1U_0402_10V6K
VGA@
CV54
(BIF_VDDC: 0.95V@0.8A)
MPLL_PVDD
ISOLATED
CORE I/O
LV3 VGA@
1
2
BLM15BD121SN1D_0402
CV53
+MPLL_PVDD
+1.8VGS
1U_0402_6.3V4Z
VGA@
10U_0603_6.3V6M
VGA@
CV51
CV50
1U_0402_6.3V4Z
VGA@
10U_0603_6.3V6M
VGA@
CV49
(MPLL_PVDD: 1.8V@90mA)
1
10U_0603_6.3V6M
VGA@
LV2 VGA@
1
2
MBK1608221YZF_2P
R21
U21
Compal Secret Data
Issued Date
2013/09/25
2016/09/25
Deciphered Date

JET_Power
Custom
ZSWAA/ZCWAA
LA-B301P
Date:
Sheet
21
of
52
Title
1
Rev
1.0
UV1C
MDA[63..0]
<23,24>
MAA[15..0]
<23,24>
DQMA[7..0]
<23,24>
QSA[7..0]
<23,24>
QSA#[7..0]
MDA[63..0]
DQMA[7..0]
QSA[7..0]
QSA#[7..0]
Place close to GPU (within 25mm)
VGA@
RV27
40.2_0402_1%
VGA@
RV26
40.2_0402_1%
+1.35VGS
+1.35VGS
VGA@
CV57
1U_0402_6.3V4Z
VGA@
RV29
100_0402_1%
VGA@
RV28
100_0402_1%
+MVREFSA
+MVREFDA
VGA@
CV58
1U_0402_6.3V4Z
Place all these components very close to GPU (within 25mm)

and keep all components close to each other.
VRAM_RST#
VGA@
RV31
10_0402_1%
2
1
VRAM_RST#_R
<23,24>
VGA@
RV30
49.9_0402_1%
1
2
VGA@
RV32
5.1K_0402_1%
VGA@
CV59
120P_0402_50V8J
K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
MAA[15..0]
@
CV128
68P_0402_50V8J
DNI
+MVREFDA
+MVREFSA
RV33
1 VGA@
2 120_0402_1%
MEM_CALRP0
K26
J26
VRAM_RST#_R
1
1
2 51.1_0402_1%
2 51.1_0402_1%
CLKTESTA_R
CLKTESTB_R
CV60 @1
CV61 @1
2 0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
CLKTESTA
CLKTESTB
GDDR5/DDR3
DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA0_8/MAA_13
MAA0_9/MAA_15
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1
MAA1_8/MAA_14
MAA1_9/RSVD
WCKA0_0/DQMA0_0
WCKA0B_0/DQMA0_1
WCKA0_1/DQMA0_2
WCKA0B_1/DQMA0_3
WCKA1_0/DQMA1_0
WCKA1B_0/DQMA1_1
WCKA1_1/DQMA1_2
WCKA1B_1/DQMA1_3
EDCA0_0/QSA0_0
EDCA0_1/QSA0_1
EDCA0_2/QSA0_2
EDCA0_3/QSA0_3
EDCA1_0/QSA1_0
EDCA1_1/QSA1_1
EDCA1_2/QSA1_2
EDCA1_3/QSA1_3
DDBIA0_0/QSA0_0B
DDBIA0_1/QSA0_1B
DDBIA0_2/QSA0_2B
DDBIA0_3/QSA0_3B
DDBIA1_0/QSA1_0B
DDBIA1_1/QSA1_1B
DDBIA1_2/QSA1_2B
DDBIA1_3/QSA1_3B
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
MVREFDA
MVREFSA
J25
K25
CSA1B_0
CSA1B_1
NC#J25
MEM_CALRP0
Route 50ohms single-ended/8mil trace width
RV34 @
RV35 @
GDDR5/DDR3
MEMORY INTERFACE
<23,24>
CKEA0
CKEA1
L10
WEA0B
WEA1B
DRAM_RST
K8
L7
K17
J20
H23
G23
G24
H24
J19
K19
G20
L17
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA13
MAA15
J14
K14
J11
J13
H11
G11
J16
L15
G14
L16
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1
MAA14
E32
E30
A21
C21
E13
D12
E3
F4
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
H28
C27
A23
E19
E15
D10
D6
G5
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
H27
A27
C23
C19
C15
E9
C5
H4
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
L18
K16
ODTA0
ODTA1
H26
H25
CLKA0
CLKA#0
G9
H9
CLKA1
CLKA#1
G22
G17
RASA#0
RASA#1
G19
G16
CASA#0
CASA#1
H22
J22
CSA#0
G13
K13
CSA#1
K20
J17
CKEA0
CKEA1
G25
H10
W EA#0
W EA#1
A_BA2
A_BA0
A_BA1
<23,24>
<23,24>
<23,24>
ODTA0
ODTA1
<23>
<24>
CLKA0 <23>
CLKA#0 <23>
CLKA1 <24>
CLKA#1 <24>
RASA#0
RASA#1
<23>
<24>
CASA#0
CASA#1
<23>
<24>
CSA#0
<23>
CSA#1
<24>
CKEA0
CKEA1
<23>
<24>
W EA#0
W EA#1
<23>
<24>
CLKTESTA
CLKTESTB
Route 50ohms single-ended/100ohm diff and keep short

debug only, for clock observation,if not need, DNI.
2160856030-A0_FCBGA631
Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
1
Title
Size
Custom
Date:

MEM IF
Document Number
Sheet
5
22
of
52
Rev
1.0
Memory Partition A - Lower 32 bits
VGA@
RV36
4.99K_0402_1%
<22,24>
QSA[7..0]
<22,24>
QSA#[7..0]
MDA[63..0]
MAA[15..0]
DQMA[7..0]
+1.35VGS
QSA#[7..0]
VGA@
RV37
4.99K_0402_1%
<22,24>
<22,24>
<22,24>
A_BA0
A_BA1
A_BA2
CLKA0
CLKA#0
CKEA0
<22>
<22>
<22>
<22>
<22>
ODTA0
CSA#0
RASA#0
CASA#0
WEA#0
M2
N8
M3
CLKA0
CLKA#0
CKEA0
J7
K7
K9
ODTA0
CSA#0
RASA#0
CASA#0
WEA#0
K1
L2
J3
K3
L3
QSA2
QSA0
F3
C7
DQMA2
DQMA0
E7
D3
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
MDA5
MDA3
MDA4
MDA1
MDA6
MDA0
MDA7
MDA2
D7
C3
C8
C2
A7
A2
B8
A3
Data Group 2
Data Group 0
+1.35VGS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.35VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
CLKA0
CLKA#0
RV42
40.2_0402_1%
VGA@
RV43
40.2_0402_1%
VGA@
T2
VRAM_RST#
L8
VGA@
RV40
243_0402_1%
2
J1
L1
J9
L9
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A_BA0
A_BA1
A_BA2
M2
N8
M3
CLKA0
CLKA#0
CKEA0
J7
K7
K9
ODTA0
CSA#0
RASA#0
CASA#0
WEA#0
K1
L2
J3
K3
L3
QSA3
QSA1
F3
C7
DQMA3
DQMA1
E7
D3
VGA@
CV64
0.01U_0402_25V7K
QSA#3
QSA#1
G3
B7
VRAM_RST# T2
L8
1
<22,24>
G3
B7
VGA@
CV63
0.1U_0402_10V6K
B1
B9
D1
D8
E2
E8
F9
G1
G9
VGA@
RV41
243_0402_1%
96-BALL
SDRAM DDR3
H5TC2G63FFR-11C_FBGA96
X76@
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA30
MDA27
MDA31
MDA24
MDA29
MDA26
MDA28
MDA25
D7
C3
C8
C2
A7
A2
B8
A3
MDA11
MDA9
MDA13
MDA15
MDA10
MDA12
MDA8
MDA14
Data Group 3
Data Group 1
Channel A0, Data Group 1
+1.35VGS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
DQMA1
QSA1
QSA#1
+1.35VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
J1
L1
J9
L9
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
DQMA2
QSA2
QSA#2
B1
B9
D1
D8
E2
E8
F9
G1
G9
CV89
CV88
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
DQMA3
QSA3
QSA#3
Need closed to UV4 side

Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
Title
Size
Custom
Date:
0.1U_0402_16V7K
VGA@
0.1U_0402_16V7K
VGA@
CV87
CV86
CV85
1U_0402_6.3V6K
VGA@
1U_0402_6.3V6K
VGA@
CV179
CV74
CV73
CV72
CV71
+1.35VGS
1U_0402_6.3V6K
VGA@
+1.35VGS
22U_0603_6.3V6M
VGA@
0.1U_0402_16V7K
VGA@
0.1U_0402_16V7K
VGA@
1U_0402_6.3V6K
VGA@
1U_0402_6.3V6K
VGA@
CV70
1U_0402_6.3V6K
VGA@
BA0
BA1
BA2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
96-BALL
SDRAM DDR3
X76@
+1.35VGS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
QSA#2
QSA#0
DML
DMU
VGA@
RV38
4.99K_0402_1%
VREFCA
VREFDQ
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
DQMA0
QSA0
QSA#0
UV5
M8
H1
+VREFC_A2A
A_BA0
A_BA1
A_BA2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
MDA16
MDA23
MDA21
MDA22
MDA18
MDA19
MDA17
MDA20
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
E3
F7
F2
F8
H3
H8
G2
H7
<22>
<22>
<22>
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
VGA@
CV62
0.1U_0402_10V6K
VREFCA
VREFDQ
2
1
M8
H1
QSA[7..0]
1
DQMA[7..0]
<Channel A0>
UV4
+VREFC_A1A
VGA@
RV39
4.99K_0402_1%
<22,24>
MDA[63..0]
MAA[15..0]
+1.35VGS
<22,24>
<22,24>

VRAM A Lower
Document Number
Sheet
5
23
of
52
Rev
1.0
Memory Partition A - Upper 32 bits

MDA[63..0]
MAA[15..0]
<22,23>
DQMA[7..0]
<22,23>
QSA[7..0]
VGA@
RV44
4.99K_0402_1%
<22,23>
QSA#[7..0]
MAA[15..0]
DQMA[7..0]
CLKA1
CLKA#1
CKEA1
ODTA1
CSA#1
RASA#1
CASA#1
WEA#1
CLKA1
CLKA#1
CKEA1
J7
K7
K9
ODTA1
CSA#1
RASA#1
CASA#1
WEA#1
K1
L2
J3
K3
L3
QSA4
QSA5
F3
C7
DQMA4
DQMA5
E7
D3
QSA#4
QSA#5
G3
B7
T2
VRAM_RST#
L8
VGA@
RV50
243_0402_1%
J1
L1
J9
L9
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
MDA42
MDA44
MDA43
MDA45
MDA41
MDA46
MDA40
MDA47
D7
C3
C8
C2
A7
A2
B8
A3
M8
H1
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A_BA0
A_BA1
A_BA2
M2
N8
M3
CLKA1
CLKA#1
CKEA1
J7
K7
K9
ODTA1
CSA#1
RASA#1
CASA#1
WEA#1
K1
L2
J3
K3
L3
QSA6
QSA7
F3
C7
DQMA6
DQMA7
E7
D3
QSA#6
QSA#7
G3
B7
VRAM_RST#
T2
M2
N8
M3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
+VREFC_A4A
Data Group 4
VGA@
RV47
4.99K_0402_1%
VGA@
CV96
0.1U_0402_10V6K
Data Group 5
+1.35VGS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.35VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
CLKA1
CLKA#1
RV48
40.2_0402_1%
VGA@
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
RV49
40.2_0402_1%
VGA@
VGA@
CV97
0.01U_0402_25V7K
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
VGA@
RV51
243_0402_1%
96-BALL
SDRAM DDR3
X76@
J1
L1
J9
L9
E3
F7
F2
F8
H3
H8
G2
H7
MDA51
MDA52
MDA49
MDA54
MDA50
MDA55
MDA48
MDA53
D7
C3
C8
C2
A7
A2
B8
A3
MDA60
MDA59
MDA63
MDA56
MDA62
MDA57
MDA61
MDA58
Data Group 6
Data Group 7
+1.35VGS
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
DQMA5
QSA5
QSA#5
+1.35VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
DQMA6
QSA6
QSA#6
B1
B9
D1
D8
E2
E8
F9
G1
G9
CV122
CV121
CV120
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
DQMA7
QSA7
QSA#7
0.1U_0402_16V7K
VGA@
1U_0402_6.3V6K
VGA@
0.1U_0402_16V7K
VGA@
CV119
CV118
1U_0402_6.3V6K
VGA@
Compal Secret Data
Issued Date
2013/09/25
2016/09/25
Deciphered Date
Title
Size
Custom
Date:
+1.35VGS
1U_0402_6.3V6K
VGA@
CV107
CV105
CV104
CV106
0.1U_0402_16V7K
VGA@
0.1U_0402_16V7K
VGA@
1U_0402_6.3V6K
VGA@
CV103
1U_0402_6.3V6K
VGA@
1U_0402_6.3V6K
VGA@
96-BALL
SDRAM DDR3
X76@
+1.35VGS
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
DQMA4
QSA4
QSA#4
UV7
A_BA0
A_BA1
A_BA2
MDA38
MDA36
MDA37
MDA35
MDA39
MDA32
MDA34
MDA33
<22,23>
A_BA0
A_BA1
A_BA2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
E3
F7
F2
F8
H3
H8
G2
H7
<22>
<22>
<22>
<22>
<22>
VGA@
CV95
0.1U_0402_10V6K
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
<22>
<22>
<22>
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
VREFCA
VREFDQ
VGA@
RV45
4.99K_0402_1%
QSA#[7..0]
<22,23>
<22,23>
<22,23>
M8
H1
+1.35VGS
QSA[7..0]
+VREFC_A3A
1
2
VGA@
RV46
4.99K_0402_1%
<Channel A1>
UV6
MDA[63..0]
+1.35VGS
<22,23>
<22,23>

VRAM A Upper
Document Number
Sheet
5
24
of
52
Rev
1.0
MLPS
Pin Name
Type
GPIO_0
I/O
3.3 V
(VDDR3)
I/O
3.3 V
(VDDR3)
GPIO_5_AC_BATT
PD/PU
Description
MLPS Bit
Strap Name
Legacy
Description
PD-reset
Power-state indicator.
Permits the voltage regulator to activate power-saving
features.
IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS.
PSI# :Low load current flag
DPRSLPVR : Deeper sleep enable flag
PS_0[1]
PS_0[2]
PS_0[3]
ROM_CONFIG[0]
ROM_CONFIG[1]
ROM_CONFIG[2]
GPIO[13:11]
If BIOS_ROM_EN = 1, ROM_CONFIG[2:0] define the ROM type. If BIOS_ROM_EN = 0,

ROM_CONFIG[2:0] define the primary memory-aperture size. Refer to current
databooks for details.
PS_0[4]
N/A
GENLK_VSYNC
Reserved for internal use only. Must be 1 at reset.
PS_1[1]
STRAP_BIF_
GEN3_EN_A
GPIO_2
Re-defined strap to indicate PCIe GEN3 capability.

1 = PCIe GEN3 supported.
0 = PCIe GEN3 not supported.
PD-reset
(Optional) An input which allows the system to

request a fastpower reduction by setting
GPIO_5_AC_BATT to low (0 V). The resulting state
transition may disturb the display momentarily.
Power reductions that are less time critical
should use the standard software methods in order
to prevent display disturbances.
PS_1[2]
GPIO_6
GPIO_15_PWRCNTL_0
I/O
3.3 V
(VDDR3)
GPIO_20_PWRCNTL_1
PD-reset
GPIO_29
GPIO_30
I
3.3 V
(VDDR3)
GPIO_8_ROMSO
PD-reset
GPIO_10_ROMSCK
B
PD-reset
GPIO_8
N/A
GENLK_CLK
Reserved for internal use only. Must be 0 at reset.
PS_1[4]
TX_PWRS_ENB
GPIO_0
Transmitter (Tx) power savings enable.

0 = 50% Tx output swing.
1 = Full Tx output swing.
PS_1[5]
TX_DEEMPH_EN
GPIO_1
PCI EXPRESS transmitter, deemphasis enable.

0 = Tx deemphasis disabled.
1 = Tx deemphasis enabled.
Serial-ROM input to ROM.

General purpose I/O or open-drain output.
PS_2[1]
N/A
N/A
Reserved.
Serial-ROM clock to ROM.

PS_2[2]
N/A
N/A
Reserved.
Serial-ROM output from ROM.

PS_2[3]
BIOS_ROM_EN
GPIO_22
PS_2[4]
BIF_VGA_DIS
GPIO_9
PD-reset
Thermal monitor interrupt.

An input from an external temperature sensor (ALERTb).
VGA disable determines whether or not the card will be recognized as the
system's VGA controller.
0 = VGA controller capacity enabled.
1 = The device will not be recognized as the systems VGA controller.
N/A
N/A
Reserved.
GPIO_19_CTF
PD-reset
Critical temperature fault (CTF) (active high) will

output 3.3 V if the on-die temperature sensor exceeds
a critical temperature so that the motherboard can
protect the ASIC from damage by removing power.
The CTF setpoint is 109
by default, and is
programmed during ASIC initialization. See the
advisory for AMD PowerPlay states for more details.
PS_2[5]
O
3.3 V
(VDDR3)
PS_3[1]
PS_3[2]
PS_3[3]
BOARD_CONFIG[0]
BOARD_CONFIG[1]
BOARD_CONFIG[2]
PD-reset
(Optional) Voltage control signal for the

memory-voltage regulator.
Note: This signal must be low (0 V) at reset
(failure to do so will prevent booting).
AUD_PORT_CONN_
PINSTRAP[0]
I/O
3.3 V
(VDDR3)
PS_0[5]
PS_3[4]
PS_3[5]
GPIO_21
I/O
3.3 V
(VDDR3)
I/O
3.3 V
(VDDR3)
GPIO_28_FDO
C
CLKREQB
PX_EN
PD-reset
Disable MLPS: PU 10K ohm to 3.3V.

(Do not install for Mars)
Enable MLPS: PD 10K ohm to GND.
(Install for Mars)
Supports the CLKREQB feature for saving power to turn

on/off the REFCLK clock on the ASIC.
On/off regulator switch in AMD PowerXpress? (switchable

graphics) BACO mode.
High (3.3 V) switches the regulators off (enter BACO
mode).
Low (0 V) switches the regulators on. (Default)
PX_EN is tri-state before internal TEST_PG is asserted
and PERSTb is deasserted.
PD
VGA@
RV15
8.45K_0402_1%
2
@
RV14
8.45K_0402_1%
1
VGA@
RV16
4.75K_0402_1%
Board configuration related strapping (such as memory ID).
Together with PS_0[5] form the three-bit strap option to indicate the number of
audio-capable display outputs. In a given ASIC there are as many endpoints as
there are digital display outputs, though not all outputs are audio capable.
111 = No usable endpoints.
110 = One usable endpoint.
101 = Two usable endpoints.
100 = Three usable endpoints.
011 = Four usable endpoints.
010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.
N/A
Memory ID
P/N
Vendor
Configuration
Size
000
SA000068U40
Samsung
K4W2G1646Q-BC1A
1G
001
SA00006H400
Hynix
H5TC2G63FFR-11C
1G
010
SA00005XB00
Micon
MT41K128M16JT-107G:K
1G
Bits[5:4]
Bits[3:1]
11
001
Capacitor
NC
R_pu
R_pd
8.45K
2K
PS_1[5:1]
11
000
NC
NC
4.75K
PS_2[5:1]
00
000
680 nF
NC
4.75K
PS_3[5:1]
11
XXX
NC
VGA@
RV17
2K_0402_1%
011
SA000076P00
Samsung
K4W4G1646D-BC1A
2G
100
SA00006E800
Hynix
H5TC4G63AFR-11C
2G
101
SA000065D00
Micon
MT41K256M16HA-107G:E
2G
00 for JET
Primary Memory Aperture Size

Requested at PCI Configuration
MLPS Strap
PS_0[5:1]
111
Size of the Primary

Memory Apertures
ROM_CONFIG [2:0]
128 MB
000
xx000
NC
4.75k
256 MB
001
xx001
8.45k
2.00k
xx010
4.53k
2.00k
Bits[5:1] PU(1%)
PD(1%) Cap
64 MB
010
xx011
6.98k
4.99k
Reserved
011
xx100
4.53k
4.99k
xx101
3.24k
5.62k
512 MB
Not supported
xx110
3.40k
10.0k
1 GB
Not supported
xx111
4.75k
NC
Mapping to VRAM type
10 for Topaz
00xxx
680nF
2 GB
Not supported
01xxx
82nF
4 GB
Not supported
10xxx
10nF
11xxx
NC
Compal Secret Data
Issued Date
2013/09/25
Deciphered Date
2016/09/25
1
MLPS configuration
VGA@
RV19
4.75K_0402_1%
X76@
RV18
2K_0402_1%
@
CV17
0.01U_0402_16V7K
0.01U_0402_16V7K
0.68U_0402_10V6K
0.01U_0402_16V7K
PS_0
PS_1
PS_2
PS_3
1 JET@ 1 @
CV15
CV16
Base on
VRAM ID
1
@
RV13
8.45K_0402_1%
X76@
RV12
4.53K_0402_1%
TOPAZ@
0.01U_0402_16V7K
PS_3[3:1]
CV15
AUD_PORT_CONN_
PINSTRAP[1]
N/A
AUD_PORT_CONN_
PINSTRAP[2]
+1.8VGS
@
CV14
To enable the external BIOS ROM device.

0 = Disable the external BIOS ROM device.
1 = Enable the external BIOS ROM device.
GPIO_17_THERMAL_INT
Determines whether or not the PCIe reference clock power

management capability is reported in the PCI configuration space
(otherwise known as CLKREQB).
0 = The CLKREQB power management capability is disabled
1 = The CLKREQB power management capability is enabled
STRAP_BIF_
CLK_PM_EN
BIOS-ROM chip select.

Used to enable the ROM for ROM read and program
operations.
Design: No use external VGA ROM, so use the test
points.
GPIO_22_ROMCSB
<19>
<19>
<19>
<19>
PS_1[3]
001
Design: No use external VGA ROM, so use the test point.
GPIO_9_ROMSI
O
3.3 V
(VDDR3)
Voltage control signals for the core (VDDC and VDDCI).

At reset, these signals will be inputs with weak
internal pulldown resistors.
The VBIOS can define all voltage-control signals to be
either 3.3-V or open-drain outputs (all signals must
be the same type).
The output states (high/low) of these pins are
programmable for each AMD PowerPlay state when they
are used as voltage control signals.
Note: GPIO_29 and GPIO_30 are only available on 28-nm
ASICs, and are NC on earlier generation ASICs.
Settings
Title

JET_MSIC

Custom
Date:
ZSWAA/ZCWAA
LA-B301P
Sheet
25
of
52
Rev
1.0
+3VS
Close to LT2
+3VS_RT
1
CT12
0.1U_0402_16V4Z
1
CT11
1
CT10
CT9
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0603_6.3V6M
+SWR_V12
CT8
0.1U_0402_16V4Z
1
CT7
CT6
LVDS@
LVDS@
+3VS_RT
+3VS_RT
Close to Pin13
Close to
Pin27
Close to Pin7
SWR_LX
SWR_VCCK
VCCK
DP_V12
Also can implement SWR mode by add inductor.
H_EDP_TXP0_C_TL
H_EDP_TXN0_C_TL
5
6
9
10
LANE0P
LANE0N
CIICSCL1
CIICSDA1
32
H_EDP_HPD
8
4
<27,9>
Close to Pin8
25
26
LCD_TL_TXOUT0+
LCD_TL_TXOUT0-
PIN30
HPD
ROM
+3VS_RT
LCD_EDID_DATA_TL RT9
MIICSCL1
MIICDA1
MIICSCL0
MIICSDA0
DP_REXT
DP_GND
GND
LVDS@
RT7
4.7K_0402_5%
PIN31
+LCD_VDD
GPIO(PWM OUT)
GPIO(Panel_VCC)
GPIO(PWM IN)
GPIO(BL_EN)
LVDS
EDID
RT6
4.7K_0402_5%
LVDS@
14
15
16
17
29
28
TL_INVT_PWM
TL_INVT_PWM
80mil
PCH_PWM_TL
ENBKL_TL 1
RT14 @
2
0_0402_5%
<27>
31
30
RT10 1 LVDS@ 2 4.7K_0402_5%
LCD_EDID_CLK_TL
PCH_PWM_TL <9>
EC_ENBKL_R
1 LVDS@ 2 4.7K_0402_5%
<36,9>
LCD_EDID_CLK_TL
LCD_EDID_DATA_TL
PCH_PWM_TL
33
LVDS@
RT13
100K_0402_5%
MIIC_SCL
MIIC_SDA
RTD2132R-VE-CG_QFN32_5X5
RT8
12K_0402_1%
LVDS@
LCD_TL_TXOUT1+
LCD_TL_TXOUT1-
RTD2132R
AUX_P
AUX_N
Other
EC_SMB_CK3
EC_SMB_DA3
LCD_TXOUT2+ <27>
LCD_TXOUT2- <27>
23
24
2
1
TXE1+
TXE1TXE0+
TXE0-
DP-IN
H_EDP_AUXP_C_TL
H_EDP_AUXN_C_TL
TXE2+
TXE2-
LCD_TXCLK+ <27>
LCD_TXCLK- <27>
21
22
SWR_VDD
PVCC
19
20
LDO mode is adopted as default power regulator mode.
12
11
27
7
TXEC+
TXEC-
LVDS
40mil
40mil
40mil
SWR / LDO Mode select
13
18
DP_V33
Power
100mil
LVDS@
MIIC_SCL
MIIC_SDA
UT2
LVDS@
1 +DP_V33
LT1 2
40mil
FBMA-L11-201209-221LMA30T_0805
LVDS@
100mil
1 +SWR_VDD
LT2 2
40mil
FBMA-L11-201209-221LMA30T_0805
+SWR_V12
40mil
LVDS@
<36>
<36>
RT4
4.7K_0402_5%
+3VS_RT
RT12
4.7K_0402_5%
LVDS@
LVDS@
LVDS@
LVDS@
LVDS@ LVDS@
GPIO
LVDS@
0.1U_0402_16V4Z
Mode Configure
ROM
only mode : PIN 30 4.7k pull low, Pin 31 4.7k pull high.
EP mode
: PIN 30 4.7k pull high, Pin 31 4.7k pull low.
EEPROM
: PIN 30 4.7k pull high, Pin 31 4.7k pull high.
Default mode
Close to LT3
CT3
CT2
LVDS@
LVDS@
0.1U_0402_16V4Z
CT1
2
0.1U_0402_16V4Z
10U_0603_6.3V6M
1
CT5
+DP_V33
+SWR_VDD
80mil
100mil
Close to Pin3
Close to Pin18
22U_0603_6.3V6M
1 Rshort@ 2
0_0805_5%
0.1U_0402_16V4Z
CT4
RT1
10U_0603_6.3V6M
100mil
+LCD_VDD
80mil
1
+LCD_VDD
<5>
H_EDP_AUXP
<5>
H_EDP_AUXN
<5>
<5>
H_EDP_TXP0
H_EDP_TXN0
H_EDP_AUXP_C_R
IEDP@
2 0.1U_0402_10V6K
C477 1
H_EDP_AUXN_C_R
LVDS@
2 0.1U_0402_10V6K
C478 1
H_EDP_AUXP_C_TL
LVDS@
2 0.1U_0402_10V6K
C479 1
H_EDP_AUXN_C_TL
LVDS@
2 0.1U_0402_10V6K
C480 1
H_EDP_TXP0_C_TL
LVDS@
2 0.1U_0402_10V6K
C481 1
H_EDP_TXN0_C_TL
IEDP@
2 0.1U_0402_10V6K
C482 1
H_EDP_TXP0_C_R
IEDP@
2 0.1U_0402_10V6K
C483 1
H_EDP_TXN0_C_R
CT13
4.7U_0603_6.3V6K
LVDS@ 1
RP4
1
2
3
4
LCD_EDID_CLK_TL
LCD_EDID_DATA_TL
LCD_TL_TXOUT0LCD_TL_TXOUT0+
LVDS@
8
7
6
5
LCD_EDID_CLK <27>
LCD_EDID_DATA <27>
LCD_TXOUT0- <27>
LCD_TXOUT0+ <27>
RT113
100K_0402_5%
LVDS@
2
IEDP@
2 0.1U_0402_10V6K
C476 1
Close to Panel conn.
0_0804_8P4R_5%
RP5
1
2
3
4
H_EDP_AUXP_C_R
H_EDP_AUXN_C_R
H_EDP_TXN0_C_R
H_EDP_TXP0_C_R
IEDP@
8
7
6
5
PIN15
PIN16
Accept voltage input (high level)
0_0804_8P4R_5%
2132S
TL_ENVDD
2132R
+LCD_VDD *
* Version R internal Power Switch, can

output 1A, Rds(on)=0.2 ohm
Place co-lay Resistor back to back on TOP and BOT
2132S
3.3V
2132R
1.5~3.3V
* Version R has internal level shifter, remove

level shifter circuit on AMD platform
Different between 2132S and 2132R(N)

2132S
<5>
H_EDP_TXP1
C62
IEDP@
1
2
0.1U_0402_10V7K
LCD_TXOUT1+ <27>
<5>
H_EDP_TXN1
C63
IEDP@
1
2
0.1U_0402_10V7K
LCD_TXOUT1-
1. Support SWR mode
<27>
LVDS@
LCD_TL_TXOUT1+
A
R42
2132R(N)
1. Support LDO mode and SWR mode
2. Internal ROM
3. Support LCD_VDD(internal Power switch)
4. Integrates Level shifter
2 0_0402_5%
LVDS@
LCD_TL_TXOUT1-
R43
2 0_0402_5%
Issued Date
Compal Secret Data
2013/09/25
2016/09/25
Deciphered Date
Title
LVDS Translator - RTD2132R(N)-CG
Custom
Rev
1.0
Date:
Sheet
1
26
of
52
1 Rshort@ 2
R4280
0_0402_5%
DLW21HN900HQ2L_4P
4
3
4
3
USB20_P5_R
BTO : TOUCH_EMI@
<11>
USB20_N5
<11>
LCD POWER CIRCUIT (For EDP panel only)
2
1
2
L61
@TOUCH_EMI@
1 Rshort@ 2
R4281
0_0402_5%
USB20_P5
USB20_N5_R
I rush=2A
W=80mils
+LCD_VDD
+3VS
U1
C4
+LCD_VDD_R
2
@
1 Rshort@ 2
R11
0_0402_5%
DLW21HN900HQ2L_4P
4
3
4
3
GND
OC
EN
SY6288C20AAC_SOT23-5
2
1
2
L62
@CAM_EMI@
1 Rshort@ 2
R9
0_0402_5%
USB20_P7_R
IN
USB20_N7
<11>
USB20_P7
<11>
SA000079400
IEDP@
1 R15
2
0_0402_5%
LCD_ENVDD_R
1
R3
IEDP@
USB20_N7_R
4.7U_0603_6.3V6K 2
IEDP@
OUT
EMI request - Close to JLVDS connector
1 Rshort@ 2
R106
0_0805_5%
LCD_ENVDD
<9>
C29
@
0.1U_0402_25V6
100K_0402_5%
Change L62 P/N from SM070003Y00 to SM070003K00
LVDS colay eDP cable
Camera & MIC

D29
Pin define will be change after ME ready
USB20_P7_R
ESD@
3
USB20_N7_R
2
+3VS
Camera
+3VS
20mils
JLVDS
1 Rshort@ 2
R432
0_0603_5%
<26>
<26>
<26>
<26>
<26>
<26>
<26>
<26>
+3VS_LVDS_CAM
USB20_P7_R
USB20_N7_R
LCD_TXOUT0+
LCD_TXOUT0LCD_TXOUT1+
LCD_TXOUT1LCD_TXOUT2+
LCD_TXOUT2LCD_TXCLK+
LCD_TXCLK-
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
Vbus
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
31
32
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
LCD_EDID_CLK <26>
LCD_EDID_DATA <26>
INT_MIC_CLK <35>
INT_MIC_DATA <35>
INT_MIC_CLK
INT_MIC_DATA
LED_PWM
BKOFF#_R
H_EDP_HPD
INT_MIC_DATA
<26,9>
+3VS
+LCD_VDD
6
SC300001400
Irush=1.5A
INT_MIC_CLK
close to LVDS conn.
60mils
+5VS
+LCD_INV
Irush=1.5A
60mils
Touch
32
JTOUCH @
20mils
1 Rshort@ 2
R431
0_0603_5%
E-T_3753K-F30N-07R
+5VS_LVDS_TOUCH
USB20_N5_R
USB20_P5_R
BKOFF#
1
2
3
4
5
6
7
8
1
2
3
4
5
6
GND
GND
ACES_50208-00601-P01
Irush=1.5A
60mils
B+
+LCD_INV
L63
2
1
FBMA-L11-201209-221LMA30T_0805
EMI@
D92
6
5
IEDP@
1
2
D90
RB751V40_SC76-2
PCH_PWM_EDP
1 Rshort@ 2
BKOFF#
R436
0_0402_5%
BKOFF#
<36>
GND
I/O3
I/O1
USB20_N5_R
1
D91
TL_INVT_PWM
2
RB751V40_SC76-2
BKOFF#
AZC099-04S.R7G_SOT23-6
<26>
close to JTOUCH conn.
1
2
R435
47K_0402_5%
R434
10K_0402_5%
4
VDD
LVDS@
D15
2
RB751V40_SC76-2
I/O2
<9>
USB20_P5_R
LED_PWM
1
BKOFF#_R
@ESD@
I/O4
+5VS
Change D15,D90,D91 P/N from

SCS0340L010 to SCS00003500
for X code.
2013/09/25
Issued Date
Compal Secret Data
2016/09/25
Deciphered Date
Title
Custom
LVDS
Rev
1.0
Date:
Sheet
E
27
of
52
PS8401
PS8201
Choke
HDMI TMDS BUS

1
Colay Cap
Colay Resistor
Componet close to Conn.

Impedance depend on platform design guide
ZZZ
HDMI45@
HDMI Royalty
RO0000003HM
+HDMI_5V_OUT
RP3 HDMI@
HDMI W/Logo + HDCP
+3VS
1
2
3
4
8
7
6
5
HDMI_SCLK
HDMI_SDATA
UMA_HDMI_CLK
UMA_HDMI_DATA
+3VS
HDMI W/O Logo: RO0000001HM

HDMI W/Logo: RO0000002HM
HDMI W/Logo + HDCP: RO0000003HM
+3VS
2.2K_0804_8P4R_5%
please manually load

this virtual material to 45@ BOM
G
UMA_HDMI_CLK
UMA_HDMI_CLK
<9>
HDMI@
R186
100K_0402_5%
HDMI@
HDMI_HPD
74AHCT1G125GW_SOT353-5
HDMI@
Q19
BSH111_SOT23-3
HDMI@
HDMI_HPD_C
2
C265
0.1U_0402_10V7K
HDMI@
1
HDMI_HPD
2
1
R571
2.2K_0402_5%
+3VS
HDMI_HPD
HDMI POWER CIRCUIT
<10,9>
1
OE#
P
3
VIN = 5V, IOUT = 0.5A , RDS(ON)

Current Limit: TYP=0.8A ; MAX=1A
Change L8,L9,L10,L11 P/N

from SM070003Y00 to SM070003K00
U16
<5>
H_HDMI_TXC+
<5>
H_HDMI_TXC-
C16
HDMI@
1
2
C22
H_DVI_TXC+
0.1U_0402_10V7K
DLW21HN900HQ2L_4P
4
3
4
3
HDMI_R_CK+
HDMI_R_CK-
<5>
<5>
HDMI@
1
2
H_HDMI_TX0-
C24
HDMI@
1
2
H_HDMI_TX0+
H_DVI_TXD0-
H_DVI_TXD0+
0.1U_0402_10V7K
C23
0.1U_0402_10V7K
1
L8
2
EMI@
L9
EMI@
; MAX=115m
C259
0.1U_0402_10V7K
IN
+5VS
GND
HDMI@
OUT
1
HDMI@
H_DVI_TXC0.1U_0402_10V7K
TYP=95m
+HDMI_5V_OUT
1
HDMI@
1
2
FLG
EN
AP2151DWG-7_SOT25-5
3
SA00006H000
HDMI_R_D0-
HDMI_R_D0+
HDMI Connector
HDMI_R_D0+
HDMI_R_D0HDMI_R_CK+
HDMI_R_CK-
DLW21HN900HQ2L_4P
1
2
3
4
RP9 HDMI@
8
7
6
5
JHDMI
HDMI_HPD_C
+HDMI_5V_OUT
HDMI_SDATA
HDMI_SCLK
680_8P4R_5%
<5>
<5>
HDMI@
1
2
H_HDMI_TX1+
C25
H_HDMI_TX1-
H_DVI_TXD1+
DLW21HN900HQ2L_4P
4
3
4
3
HDMI_R_D1+
H_DVI_TXD1-
HDMI_R_D1-
0.1U_0402_10V7K
HDMI@
1
2
C26
0.1U_0402_10V7K
1
L10
2
EMI@
HDMI_R_D2+
HDMI_R_D2HDMI_R_D1+
HDMI_R_D1-
1
2
3
4
HDMI_R_CK-
RP10 HDMI@
8
7
6
5
HDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1-
680_8P4R_5%
<5>
H_HDMI_TX2+
HDMI@
1
2
C28
L11
1
H_DVI_TXD2+
0.1U_0402_10V7K
HDMI@
1
2
C27
H_DVI_TXD2-
0.1U_0402_10V7K
H_HDMI_TX2-
HDMI_R_D1+
HDMI_R_D2-
Q24
+5VS
<5>
HDMI_SDATA
U9
UMA_HDMI_DATA
R145
2
HDMI_HPD_U 1
1K_0402_5%
HDMI@
<9>
HDMI_SCLK
2
UMA_HDMI_DATA 3
+HDMI_5V_OUT
Q18
BSH111_SOT23-3
1
HDMI@
S 2N7002KW_SOT323-3
2
G
HDMI@
HDMI_R_D2+
EMI@
HDMI_R_D2-
HDMI_R_D2+
DLW21HN900HQ2L_4P
Common CHOKE use 90ohm
2012/04/19
Issued Date
Title
Date:
20
21
22
23

2015/04/19
Deciphered Date
Size
A
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
GND
D2GND
D2_shield GND
D2+
GND
ACON_HMR2U-AK120C
Compal Secret Data
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI Conn.
Document Number
Rev
1.0
Sheet
E
28
of
52
Close to Pin24
Close to Pin31
Close to Pin14
Close to Pin38
CD16
0.1U_0402_16V4Z
5mil
CD14
0.1U_0402_16V4Z
1
2
LD3 TAI-TECH FCM1608KF-600T05
Rated current 500mA, DC 0.1ohm
CD12
0.1U_0402_16V4Z
CD10
0.1U_0402_16V4Z
CRT@
CRT@
CD9
0.1U_0402_16V4Z
Close to Pin13
Close to Pin35
CD8
4.7U_0603_6.3V6K
CRT@
Close to Pin7
CRT@
Close to Pin46
5mil
CD7
0.1U_0402_16V4Z
CD6
0.1U_0402_16V4Z
CRT@
CD5
4.7U_0603_6.3V6K
CD2
0.1U_0402_16V4Z
CRT@
CD4
1U_0402_6.3V6K
CRT@
1 Rshort@ 2
LD2
0_0603_5%
15mil
CD3
0.1U_0402_16V4Z
Close to Pin44
Close to Pin25
15mil
CD1
10U_0603_6.3V6M
1 Rshort@ 2
RD1
0_0603_5%
+1.8VS_DAC
+1.8VS_RXVDD
CRT@
+1.8VS_CRT
+1.8VS_CRT
Close to Pin36
CD11
0.1U_0402_16V4Z
+3VS_6513
CRT@
+1.8VS_CRT
+3VS
CD15
0.1U_0402_16V4Z
CD13
1U_0402_6.3V6K
Close to Pin10
Close to Pin12
+3VS_6513
+3VS
+1.8VS_CRT
+1.8VS_RXVDD
RD3
RD11 2
@
@
H_DP1_C_P1
H_DP1_C_N1
1 100K_0402_5%
<9> H_DDI1_AUXP
<9> H_DDI1_AUXN
+3VS
RD12 2
RD8
@
@
1 100K_0402_5%
1 1M_0402_5%
4
3
2
1
5
6
7
8
5mil
5mil
5mil
5mil
15mil
12
14
44
46
IVDD
IVDD
IVDD
IVDD
15mil
3815mil
39
IVDDO
IVDDO
15mil
3515mil
36
MCURSTN
URDBG
CRT@
2
2
CRT@
25
31
5mil
+1.8VS_CRT
5mil
B
RX1P
RX1N
22
5mil
+1.8VS_CRT
ISPSCL
ISPSDA
RXAUXP
RXAUXN
VGADDCCLK
VGADDCSDA
DCAUXP
DCAUXN
VSYNC
HSYNC
AVCC
AVCC
VDDC
DVDD18
IOBP
NC/VGADETECT
32
5mil
+1.8VS_CRT
43
42
RSET
COMP
PCSDA
PCSCL
UMA_CRT_CLK
28
T1
15
16
ISPSCL_R
ISPSDA_R
CRT@ 1
CRT@ 1
23
21
UMA_CRT_CLK_R
UMA_CRT_DATA_R
3
4
CRT@ RD6
CRT@ RD7
2
2
UMA_CRT_VSYNC
UMA_CRT_HSYNC
10
2 RD4
2 RD5
22_0402_5%
22_0402_5%
1 22_0402_5%
1 22_0402_5%
UMA_CRT_CLK
UMA_CRT_DATA
<30>
<30>
11
9
8
41
RD9
RSET
8mil
1
CRT@
2 100_0402_1%
8mil
6
COMP
8mil
34
33
UMA_CRT_R
<30>
UMA_CRT_G
<30>
UMA_CRT_B
<30>
RPD2
75_0804_8P4R_1%
CRT@
+1.8VS_DAC
2
@
RPD2
150_0804_8P4R_1%
@
CD21
GND
IN
@
CD22
Compal Secret Data
Issued Date
Title
Deciphered Date
4
If there is a pull down 150 resister near the

CRT conn., please change RPD2 to 150 too .
RD13 10K_0402_5%
RD10
1M_0402_5%
@
XTALIN_6513
YD1
27MHZ_10PF_X3G027000BA1H-U
Crystal
3
4
OUT
GND
XTALIN_6513
XTALOUT_6513
49
XTALOUT_6513
CRT@
1
2 CD20
0.1U_0402_16V4Z
CRT@
UMA_CRT_CLK <30>
UMA_CRT_DATA <30>
+1.8VS_DAC
5mil
PAD
PWDNB
XTALIN
XTALOUT
37
+3VS_6513
A
CRT@
47
ASPVCC
VDDA
PCSDA
PCSCL
UMA_CRT_DATA
IOGP
24
5mil
2 CD17 0.1U_0402_16V4Z
IT6513FN
PVCC
IORP
+1.8VS_RXVDD
5mil
RX0P
RX0N
1 1M_0402_5%
CD18
0.1U_0402_16V7K
1
H_DDI1_AUXP_C 20
1
H_DDI1_AUXN_C 19
CD19
0.1U_0402_16V7K
18
17
45
18P_0402_50V8J
+3VS
29
30
PCSCL
MCUVDDH
18P_0402_50V8J
<5>
<5>
26
27
H_DP1_C_P0
H_DP1_C_N0
PCSDA
+3VS_6513
8
7
6
5
<5>
<5>
CRT@
RPD1
2.2K_0804_8P4R_5%
1
2
3
4
RD2
4.7K_0402_5%
CRT@
IVDD33
IVDD33
HPD
OVDD
OVDD
40
H_DP_HPD
<9>
DDCSCL
DDCSDA
UD1
C
1
2
CRT@
1315mil
48
ISPSCL_R
ISPSDA_R
DP-CRT_ITE IT6513FN
Size
Document Number
Rev
1.0
Date:
Sheet
1
29
of
52
CRT CONNECTOR
UMA_CRT_R
L6
<29>
UMA_CRT_G
L12
<29>
UMA_CRT_B
L7
<29>
2 NBQ100505T-800Y_0402
CRT@EMI@
2 NBQ100505T-800Y_0402
CRT@EMI@
2 NBQ100505T-800Y_0402
CRT@EMI@
CRT_R_L
CRT_G_L
CRT_B_L
1
C241
1
C242
CRT@
1
C243
CRT_R_L
2.2P_0402_50V8C
C240
CRT@
CRT@
2.2P_0402_50V8C
C239
2.2P_0402_50V8C
C238
2.2P_0402_50V8C
2.2P_0402_50V8C
CRT@
CRT@
2.2P_0402_50V8C
JCRT @
CRT@
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
T102PAD
CRT_DDC_DAT
CRT_G_L
HSYNC
CRT_B_L
+HDMI_5V_OUT
VSYNC
T161PAD
CRT_DDC_CLK
USE HDMI POWER
G
G
16
17
J-L_TNBNRACZZ013015
CRT@
+3VS
BYP
VCC_VIDEO
VIDEO1
VCC_DDC
VIDEO2
DDC_IN1
VIDEO3
DDC_IN2
DDC_OUT1
1
C18
+HDMI_5V_OUT
2
0.22U_0402_16V7K
CRT_R_L
CRT_G_L
CRT_B_L
+3VS
VCC_SYNC
UMA_CRT_DATA
UMA_CRT_DATA
10
<29>
UMA_CRT_CLK
UMA_CRT_CLK
11
UMA_CRT_VSYNC
13
<29>
UMA_CRT_VSYNC
SYNC_IN1
DDC_OUT2
R153
4.7K_0402_5%
CRT@
<29>
UMA_CRT_HSYNC
UMA_CRT_HSYNC
15
SYNC_IN2
SYNC_OUT1
CRT_DDC_DAT
12
GND
SYNC_OUT2
14
16
CRT_DDC_CLK
CRT@
VSYNC_R
R64
R159
4.7K_0402_5%
CRT@
R62
<29>
U49
+HDMI_5V_OUT
HSYNC_R
CRT@
2 22_0402_5%
VSYNC
2 22_0402_5%
HSYNC
TPD7S019-15DBQR_SSOP16
CRT@
Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
A
Title
CRT
Size
Document Number
Rev
1.0
Date:
Sheet
E
30
of
52
SATA HDD/SSD Conn.

Close to JHDD
JHDD
@
GND
RX+
RXGND
TXTX+
GND
24
23
GND
GND
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Rsv
GND
12V
12V
12V
1
2
3
4
5
6
7
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
C511 1
C512 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
C513 1
C514 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_P0 <7>
SATA_PTX_DRX_N0 <7>
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+3VS
+5VS
+5VS
Place closely JHDD SATA CONN.
1.2A
1
LCN_ASF98-2231S10-0002
1
C515
10U_0805_10V4Z
C516
0.1U_0402_10V7K
C517
0.1U_0402_10V7K
SATA ODD Conn

+5VS_ODD
Peak
Read (CD)
Read (DVD)
Write
Standby
JODD
GND
GND
1800 mA
1100 mA
950 mA
1300 mA
20mA
1
C518
10U_0805_10V4Z
1
C519
0.1U_0402_10V7K
C520
0.1U_0402_10V7K
Conn@
GND
A+
AGND
BB+
GND
14
15
Place components closely ODD CONN.
1.1A
Power Consumption
DP
+5V
+5V
MD
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1
C521 1
C522 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
C523 1
C524 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
ODD_DETECT#
SATA_PTX_DRX_P1 <7>
SATA_PTX_DRX_N1 <7>
<10,7>
+5VS_ODD
ODD_DA#
<10>
SANTA_201902-1
Issued Date
Compal Secret Data
2013/09/25
2016/09/25
Deciphered Date
Title
Size
Date:
SATA HDD/SSD/ODD
Document Number
Rev
1.0
Sheet
E
31
of
52
NGFF-Slot1-E-Key-WLAN
JW LAN
68
<33,37,9>
<36> W L_OFF#
<36> BT_ON
PLT_RST_BUF#
<9> CLK_EC
<36> E51_RXD
<36> E51_TXD
Debug card using
pin 8-15
Removed for key A
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
GND2
GND1
GND_75
3.3VAUX_74
RSVD_73
3.3VAUX_72
RSVD_71
RSVD_70
GND_69
RSVD_68
RSVD/PCIE_TX_N1
RSVD_66
RSVD/PCIE_TX_P1
RSVD_64
GND_63
I2C_IRQ
RSVD/PCIE_RX_N1
I2C_CLK
RSVD/PCIE_RX_P1
I2C_DAT
GND_57
W_DISABLE1#
PEWAKE0#
W_DISABLE2#
CLKREQ0#
PERST0#
GND_51
SUSCLK(32KHz)
REFCLK_N0
COEX1
REFCLK_P0
COEX2
GND_45
COEX3
PER_TX_N0
CLink_CLK
PER_TX_P0
CLink_DATA
GND_39
CLink_RST
PET_RX_N0
UART_CTS
PET_RX_P0
UART_RTS
GND_33
UART_RX
UART_TX
UART_WAKE
GND_18
LED2#
PCM_IN
PCM_OUT
PCM_SYNC
PCM_CLK
LED1#
3.3VAUX_4
3.3VAUX_2
SDIO_RST
SDIO_WAKE
SDIO_DAT3
SDIO_DAT2
SDIO_DAT1
SDIO_DAT0
SDIO_CMD
SDIO_CLK
GND_7
USB_DUSB_D+
GND_1
+3V_W LAN
+3V_W LAN
1
69
CM6
0.1U_0402_10V7K
1
CM8
2
0.1U_0402_10V7K
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
CM7
2
4.7U_0603_6.3V6K
1
Close to JWLAN
W LAN_W AKE# <36>

CLKREQ_W LAN# <10,8>
CLK_W LAN# <8>
CLK_W LAN <8>
PCIE_PRX_W LANTX_N4
PCIE_PRX_W LANTX_P4
<11>
<11>
PCIE_PTX_C_W LANRX_N4
PCIE_PTX_C_W LANRX_P4
23
21
19
17
15
13
11
9
7
5
3
1
WLAN/ WiFi
<11>
<11>
USB20_N4
USB20_P4
<11>
<11>
WiMax/ BT
BELLW _80152-3221
Compal Secret Data
2013/09/25
Issued Date
Deciphered Date
2016/09/25
A
Title
NGFF-WLAN
Size
Document Number
Rev
1.0
Date:
Sheet
E
32
of
52
Left USB 2.0 x 1
LAN/USB Small board Conn
Current Limit 2A
Change LR9 P/N from SM070003Y00 to SM070003K00
+USB_VCCC
JLAN @
27
28
G1
G2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
W=80mils
+5VALW
@
LAN_OFF#
LR9
<36>
USB20_N2_L
USB20_P2_L
4
PCIE_PRX_C_LANTX_P3
PCIE_PRX_C_LANTX_N3
PCIE_PTX_C_LANRX_P3
PCIE_PTX_C_LANRX_N3
<11>
<11>
<11>
<11>
EMI@
2
3
USB20_N2
USB20_P2
USB20_P2
EMI@
3
2
EC_SWI#
<36,9>
PLT_RST_BUF#
<11>
2
<11>
R5 1 @EMI@ 2 0_0402_5%
DLW21HN900HQ2L_4P
CLK_LAN_R
CLK_LAN#_R
ISOLATE#
LANCLK_REQ#
PLT_RST_BUF#
USB20_N2
L56
4
1
CLK_LAN
<8>
CLK_LAN#
<8>
+USB_VCCC
Check Output Caps are on sub-board or not.
UR3
5
CR6
10U_0603_6.3V6M
+5VALW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
<36>
USB_EN#2
OUT
IN
GND
EN
OCB
1
D
2
3
USB_OC#2
<10,11,36>
SY6288D20AAC_SOT23-5
SA00007AO00
DLW21HN900HQ2L_4P
1
2
R4
0_0402_5%
@EMI@
<32,37,9>
+3V_LAN
PL <35>
PR <35>
EXT_MIC_L <35>
NBA_PLUG# <35>
+3V_LAN > 40 mil

E-T_6905-E26N-01R
@ PJ77
1
+3V_LAN
+3VALW_PCH
JUMP_43X39
C
LAN
LAN_EN
ISOLATEB
S0
Sx
S0
Sx
---------------------------------------------0
0
0
0
1
1
0
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0*
+3VS
For LAN function

RL24 2
1 10K_0402_5%
LANCLK_REQ#
+3VS
ISOLATE# RL433 1 Rshort@ 2 0_0402_5%
WOL_EN#
LAN_EN
<36>
CLKREQ_LAN#
3
S
<8>
<10,8>
1K_0402_5%
RL8
@
LANCLK_REQ#
RL9
15K_0402_5%
Sx Enable
Wake up
QL53
2N7002KW_SOT323-3
WOL_EN#
WOL
*
S3: after SUSP# assert low over 100ms
S4/S5: after SYSON assert low over 100ms
Sx Disable
Wake up
LOW
+3V_LAN rising time (10%~90%) need > 1ms and <100ms.
HIGH
<36,8>
<36,8>
<36,8>
<36,8>
2
10K_0402_5%
26
23
20
17
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
CLKOUT_LPC1
RT11
22_0402_5%
@EMI@
<8>
<36,8>
CLKOUT_LPC1
CLKOUT_LPC1
LPC_FRAME#
SERIRQ
<10,36>
PLT_RST_BUF#
1
CT42
10P_0402_50V8J
28
21
22
16
27
7
+3VS
TEST
LAD0
LAD1
LAD2
LAD3
LPCPD#
LCLK
LFRAME#
LRESET#
SERIRQ
PP
+3VALW
NC0
VDD3
VSS3
NC1
NC2
NC3
VSS0
VSS1
VSS2
+3VALW
+3VS
5
19
24
Close to Pin5
CT17
3
10
11
12
13
14
TPM@
4
18
25
CT21
TPM@
Close to Pin19
1
CT22
2
TPM@
Close to Pin10
CT33
CT34
TPM@
CT14
0.1U_0402_10V7K
For EMI
1
RT5
TPM@
VSB
VDD1
VDD2
10U_0603_6.3V6M
EEh - EFh
7Eh - 7Fh
GPIO0/XOR_OUT
GPIO1
GPIO2/GPX
GPIO3/BADD
GPIO4/CLKRUN#
0.1U_0402_10V7K
0
* Floating
1
2
6
9
15
0.1U_0402_10V7K
ADDRESS
0.1U_0402_10V7K
UT1
BADD
10U_0603_6.3V6M
TPM
TPM@
TPM@
Close to Pin24
@EMI@
NPCT650AA0WX_TSSOP28
Issued Date
Compal Secret Data
2013/09/25
2016/09/25
Deciphered Date
Title
Size
Date:
TPM
Document Number
Rev
1.0
Sheet
1
33
of
52
Right rear USB2.0 Conn.
Right side USB 3.0 x 1 W/O Sleep&Charge

Change L71,L72,LR7,LR8 P/N
from SM070003Y00 to SM070003K00
<11>
USB20_P0
<11>
USB20_N0
EMI@
2
LR7
USB20_P0_R
USB20_N0_R
<11>
U3RXDP2
<11>
U3RXDN2
1
4
DLW21HN900HQ2L_4P
L71
EMI@
U3RXDP2_L
U3RXDN2_L
<11>
USB20_N1
<11>
USB20_P1
EMI@
2
DLW21HN900HQ2L_4P
LR8
USB20_N1_R
USB20_P1_R
DLW21HN900HQ2L_4P
CLOSE UR1
+5VALW
+USB_VCCB
W=80mils
USB_EN#0
GND
EN
OCB
1
CR2
1
CR3
CR5
1
+
22U_0805_6.3V6M
OUT
IN
22U_0805_6.3V6M
5
<36>
CR4
22U_0805_6.3V6M
+USB_VCCB
UR1
0.1U_0402_10V7K
W=80mils
+5VALW
10U_0603_6.3V6M
CR1
100U_D2_6.3VM_R17M
CR14
Current Limit 2A
<11>
U3TXDP2
1
C526
2
U3TXDP2_C
0.1U_0402_10V7K
<11>
U3TXDN2
1
C528
2
U3TXDN2_C
0.1U_0402_10V7K
L72
EMI@
U3TXDP2_C_L
U3TXDN2_C_L
DLW21HN900HQ2L_4P
2
3
USB_OC#0
W=80mils
<10,11,36>
D88
U3TXDP2_C_L 1 1
SY6288D20AAC_SOT23-5
SA00007AO00
JUSBR
+USB_VCCB
USB20_N0_R
USB20_P0_R
1
2
3
4
5
6
7
8
@ESD@
10 9
JUSBF
9
1
8
2
7
3
6
4
5
U3TXDP2_C_L
U3TXDP2_C_L
U3TXDN2_C_L 2 2
9 8
U3TXDN2_C_L
U3RXDP2_L
4 4
7 7
U3RXDP2_L
U3RXDN2_L
5 5
6 6
U3RXDN2_L
+USB_VCCB
U3TXDN2_C_L
USB20_N1_R
VBUS
DD+
SHIELD
GND
GND
GND
GND
SANTA_360131-1
USB20_P1_R
U3RXDP2_L
U3RXDN2_L
3 3
SSTX+
VBUS
SSTXDGND
D+
SSRX+
GND
SSRX-
GND
GND
GND
GND
10
11
12
13
B
OCTEK_USB-09EAEB
8
YSCLAMP0524P_SLP2510P8-10-9
Compal Secret Data
Issued Date
2013/09/25
2016/09/25
Deciphered Date
Title

RUSB/S&C
Custom
Date:
Sheet
1
34
of
52
Rev
1.0
60 mil
+MIC2_VREFO
PR_L
PR_R
CA6 1
D
CA9
CA7 1
CA12 1
AC_VREF
RA7
2
147_0402_1% HPOUT_L
2
1
HPOUT_R
RA4
47_0402_1%
2 1U_0402_6.3V6K
CBN
CBP
2 1U_0402_6.3V6K
CPVEE
2 4.7U_0402_6.3V6M
2 4.7U_0402_6.3V6M
close to pin, 10mil

Reserve for solve pop noise
1
RA17
2
100K_0402_5%
1
CA18
2
4.7U_0402_6.3V6M
EC_MUTE_INT
RA12
1
2
@
0_0402_5%
32
33
35
37
34
LDO1-CAP
LDO2-CAP
LDO3-CAP
27
39
7
SPKLSPKL+
SPKRSPKR+
43
42
44
45
EC_MUTE_INT_R
48
4
25
38
49
LDO1-CAP
AVDD1
AVDD2
JDREF
PVDD1
PVDD2
CPVDD
VREF
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
CBN
CBP
SDATA-IN
SDATA-OUT
CPVEE
BCLK
LDO1-CAP
LDO2-CAP
LDO3-CAP
SYNC
PCBEEP
SPK-OUT-LSPK-OUT-L+
SPK-OUT-RSPK-OUT-R+
Sense A
Sense B
MIC1-L(PORT-B-L)
MIC1-R(PORT-B-R)
MIC2-L(PORT-F-L)
MIC2-R(PORT-F-R)
SPDIF-OUT/GPIO2
DVSS
AVSS1
AVSS2
Thermal Pad
LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)
LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R)
RESETB
DGND
close to pin, 10mil
PDB
1
9
+DVDD
+DVDD
26
40
+AVDD1
+AVDD2
41
46
36
+PVDD
+PVDD
+DVDD
8
5
6
AZ_BITCLK_HD
AZ_SDIN0_HD
<7>
AZ_SDOUT_HD <7>
AZ_BITCLK_HD
<7>
AZ_SYNC_HD
<7>
MONO_IN
SENSE_A
+AVDD2
LINE1-L
LINE1-R
CA16 1
CA17 1
RA15
LINE1-L_C 1
LINE1-R_C 1
RA16
2 2.2U_0402_6.3V6M
2 2.2U_0402_6.3V6M
EC_MUTE#
<36>
CA11
EC_MUTE#
Hight
LOW
PCI Beep
1K_0402_5%
2
2
1K_0402_5%
AZ_RST_HD#
PCH_SPKR
CA23
1
2
1 RA27
2
47K_0402_5%
MONO_IN
close to pin1
EXT_MIC
LA2
CA20 1
10P_0402_50V8J
EMI@
2
SBY100505T-470Y-N_2P
EXT_MIC_L
CA24
CA25
100P_0402_50V8J
2
EMI@
<33>
PR_R
LA1
1 Rshort@ 2 0_0402_5%
PR
<33>
PR_L
LA3
1 Rshort@ 2 0_0402_5%
PL
<33>
For better sound

by customer request
place close to chip

+3VS
<33>
NBA_PLUG#
1
RA29
2
100K_0402_5%
1
RA30
2
200K_0402_5%
CA26
@EMI@
(ALC233 supported IPhone headset/ Headphone/ MIC in)
close to pin36
For EMI protection

use SM01000GK00
CA13
4.7U_0402_6.3V6M
1 Rshort@ 2
RA20
0_0603_5%
1 Rshort@ 2
RA21
0_0603_5%
1 @
2
RA22
0_0603_5%
1 @EMI@ 2
RA24
0_0603_5%
1 @EMI@ 2
RA25
0_0603_5%
Change material
to SM01000GK00
2.2K_0402_5%
2
0.1U_0402_10V7K
RA28
4.7K_0402_5%
@
CA15
0.1U_0402_10V7K
PR_L
PR_R
AZ_BITCLK_HD
RA23 2
10_0402_5% EMI@
RA26
1
<7>
<10>
Enable
Disable
Combo Jack
+3VS
1U_0402_6.3V6K
For EMI reserve

close to codec
CA22
2.2U_0402_6.3V6M
+MIC2_VREFO
1 Rshort@ 2
RA10
0_0603_5%
CA19
0.01U_0402_25V7K
1
@ESD@
RA19
4.7K_0402_5%
@
Internal AMP
Beep sound
CA10
1U_0402_6.3V6K
+1.5VS
20 mil
ALC233-VB MQFN 48P
1U_0402_6.3V6K
+DVDD
1
1 Rshort@ 2
RA11
0_0603_5%
100P_0402_50V8J
20 mil
100P_0402_50V8J
close to pin26
1 Rshort@ 2
RA2
0_0603_5%
CA2
Reserve for solve noise issue
EXT_MIC
AC_VREF
@
CA21
0.1U_0402_10V7K
+AVDD1
1
4.7U_0402_6.3V6M
2
11
AGND
CA1
0.1U_0402_10V7K
+3VALW
CA14
1
22
21
24
23
47
+5VS
<27>
close to pin3
19
20
17
18
CA4
1 10U_0603_6.3V6M
<27>
INT_MIC_CLK
10
13
14
close to pin46
For EMI reserve
INT_MIC_CLK_R
RA8 CAM_EMI@
FBMA-10-100505-301T
1 22_0402_5%
AZ_SDIN0_HD_R 2
RA9
12
close to pin41
CA5
0.1U_0402_10V7K
INT_MIC_DATA
2
3
CA3
0.1U_0402_10V7K
For AMD & Baytrail, name Pin9 +DVDD-IO
<36>
28
DVDD
DVDD-IO
15
MONO-OUT
MIC2-VREFO
MIC1-VREFO-R
MIC1-VREFO-L
20 mil
RA5
UA1
16
29
30
31
CA8
EMI@
220P_0402_50V7K
4.7K_0402_5%
1
+MIC1-VREFO-R
1
+MIC1-VREFO-L
4.7K_0402_5%
2
2
RA3
PR_R
PR_L
1 Rshort@ 2
RA1
0_0603_5%
+PVDD
1
CA27
100P_0402_50V8J
@EMI@
SENSE_A
for Combo Jack normal Open
SPK
SPK Conn.
For EMI reserve

close to codec
DA8
3
SPKL+
1 Rshort@ 2
RA32
0_0603_5%
SPK_L1
SPKL-
1 Rshort@ 2
RA33
0_0603_5%
SPK_L2
CA28
1000P_0402_50V7K
@EMI@
1
2
YSDA0502C_SOT23-3
@ESD@
JSPK @
SPK_L1
SPK_L2
SPK_R1
SPK_R2
CA29
1000P_0402_50V7K
@EMI@
DA9
1
2
3
4
1
2
3 GND
4 GND
6
5
3
SPKR+
SPKR-
1 Rshort@ 2
RA34
0_0603_5%
SPK_R1
1 Rshort@ 2
RA35
0_0603_5%
SPK_R2
@EMI@
CA30
1000P_0402_50V7K
Issued Date
Compal Secret Data
2012/04/19
Deciphered Date
2015/04/19
Title
Size
Date:
RA13 LA2 CA24

close to small board connector
YSDA0502C_SOT23-3
@ESD@
@EMI@
CA31
1000P_0402_50V7K
RING2_L
EXT_MIC EXT_MIC_L RING2

Speaker 4 ohm: 40mil
Speaker 8 ohm: 20mil
CVILU_CI4404M1HRT-LF
ALC233/233VB
Document Number
Rev
1.0
1
Sheet
35
of
52
+3VL
UB1
RB4
10_0402_5%
@EMI@
1
CB11
22P_0402_50V8J
@EMI@
1
2
3
4
5
7
8
10
<10> KB_RST#
<10,33> SERIRQ
<33,8> LPC_FRAME#
<33,8> LPC_AD3
<33,8> LPC_AD2
<33,8> LPC_AD1
<33,8> LPC_AD0
+3VL
RB2
47K_0402_5%
1
2
1
CB12
<10> EC_SCI#
<38> WOWL_EN
EC_RST#
2
0.1U_0402_10V7K
<37>
<37>
12
13
37
20
38
CLK_PCI_EC
PLT_RST#
EC_RST#
<8> CLK_PCI_EC
<18,9> PLT_RST#
KSI[0..7]
KSO[0..17]
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI[0..7]
KSO[0..17]
RPB1
+3VL
+3VS
1
2
3
4
8
7
6
5
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<40,41>
<40,41>
<19,8>
<19,8>
77
78
79
80
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
AD Input
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
<7>
PCH_RTCRST#
1
RB27
2
E51_TXD
100K_0402_5%
2
RB28
1
EC_MUTE_INT
4.7K_0402_5%
RB29 1
2 0_0402_5%
PCH_RTCRST#_R
<33> USB_EN#2
<33> LAN_OFF#
<7> FAN_SPEED1
<32> WL_OFF#
<32> E51_TXD
<32> E51_RXD
<9> PCH_PWROK
<32> BT_ON
<37> NUM_LED#
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00
122
123
EC_MUTE_INT
<42,9> POK
XCLKI/GPIO5D
XCLKO/GPIO5E
SPI Flash ROM
GPIO
Bus
GPIO
QB1
2
2N7002K_SOT23-3
+3VS
63
64
65
66
75
76
BATT_PRES
BATT_PRES <40>
USB_OC#0 <10,11,34>
ADP_I <40,41>
ADP_V <41>
TRANS_SEL
EC_ENBKL_R
68
70
71
72
83
84
85
86
87
88
DFAN1
H_PROCHOT#_EC 1
RB6
+3VL
<26,9>
<7>
VCCST_PWRGD
<12,44>
LID_SW#
1
RB35
2
47K_0402_5%
WLAN_WAKE#
1
RB37
2
47K_0402_5%
Reserve this signal to EC by SW demand

2011/10/18a
EC_MUTE# <35>
PM_SLP_S4# <9>
EC_SMB_CK3 <26>
EC_SMB_DA3 <26>
TP_CLK <37>
TP_DATA <37>
EC_SMB_CK3
EC_SMB_DA3
TP_CLK
TP_DATA
97
98
99
109
+3VS
TP_CLK
1
RB13
2
4.7K_0402_5%
TP_DATA
1
RB14
2
4.7K_0402_5%
GPU_DOWN# <19>
PWRME_CTRL <7>
VCIN0_PH <40>
VCIN0_PH connect to power portion
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R
119
120
126
128
73
74
89
90
91
92
93
95
121
127
100
101
102
103
104
105
106
107
108
WLAN_WAKE#
EC_SMB_CK3
1
@
RB15
2
2.2K_0402_5%
EC_SMB_DA3
1
@
RB16
2
2.2K_0402_5%
SYSON
1
RB10
2
4.7K_0402_5%
SUSP#
1
RB21
2
10K_0402_5%
WLAN_WAKE# <32>
WOL_EN# <33>
BATT_FULL_LED# <37>
CAPS_LED# <37>
PBTN_LED# <37>
BATT_CHG_LOW_LED# <37>
SYSON <43>
VCCST_PG_EC <12>
SYSON
H_PROCHOT#_EC
VCOUT0_PH_L
PCH_RSMRST# <9>
EC_LID_OUT# <10>
PROCHOT_IN <40>
+3VS
EC_SDIO <8>
EC_SDI <8>
EC_SCK <8>
EC_CS0# <8>
PROCHOT_IN connect to power portion
BKOFF# <27>
PBTN_OUT# <9>
PCH_PWR_EN <38>
EC_SWI# <33,9>
110
112
114
115
116
117
118
ACIN
124
+EC_V18R
1
LID_SW#
SUSP#
VS_ON
<42>
VCOUT0_PH connect to power portion (9012 only)
1
RB19
EC_PECI
KB9012QF-A4_LQFP128_14X14
VCOUT0_PH_L 1 Rshort@ 2
RB34
0_0402_5%
ACIN <41,9>
EC_ON <42>
ON/OFFBTN# <16,37>
LID_SW# <37>
SUSP# <38,44,46>
2
43_0402_5%
H_PECI
<5>
Close to EC
SUSP#
@ESD@
1
2
CB14
180P_0402_50V8J
CB15
4.7U_0805_10V4Z
Reserve TRANS_PRSNT for panel timing tuning.

+3VL
2
2
VCIN0 pin109
VCIN1 pin102
>1.2V
VCOUT0 pin104
HIGH
(default)
HIGH
LVDS@
RB23
10K_0402_5%
TRANS_PRSNT
Voltage Comparator Pins FOR 9012 A3
VCOUT1 pin103
2
10K_0402_5%
<1.2V
IEDP@
RB22
10K_0402_5%
RB25
10K_0402_5%
@
1
2
100P_0402_50V8J
1
2
CB10 100P_0402_50V8J
1
2
1
2
TRANS_SEL
1
@ CB9
WL_BT_LED# <37>
USB_EN#0 <34>
TRANS_PRSNT
+3VL
RB26
10K_0402_5%
CB8
47P_0402_50V8J
BATT_PRES
Signal pull high is default status (ROM only mode).

If signal pull low, EC will send translator code to chip.(EP mode)
LVDS@
<5>
1
21
23
26
27
SPI Device Interface
11
24
35
94
113
<35>
E51_TXD
E51_RXD
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
PS2 Interface
GND/GND
GND/GND
GND/GND
GND/GND
GND0
<9> PM_SLP_S3#
<9> PM_SLP_S5#
<7> EC_SMI#
<10,11,33> USB_OC#2
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
DA Output
H_PROCHOT#
ACIN
PWM Output
2.2K_8P4R_5%
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
1 Rshort@ 2 0_0402_5%
67
RB1
VR_HOT#
EC_VDD/AVCC
2
0.1U_0402_10V7K
AGND/AGND
<47>
H_PROCHOT#_EC
69
CLK_PCI_EC
CB4
9
22
33
96
111
125
CB1
0.1U_0402_10V7K
CB3
0.1U_0402_10V7K
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
1
CB2
@
@ CB5
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
For EMI
+3VL
LOW
LOW
(default)
For Translator select
Issued Date
Compal Secret Data
2013/09/25
2016/09/25
Deciphered Date
Title
Size
Date:
LPC-EC-KB9012&930
Document Number
Rev
1.0
Sheet
E
36
of
52
PBTN/B to M/B
LED Small board to Conn
Power Button
2
+3VL
NOTICE: ON/OFFBTN# have

pull-hign resistance on
motherboard
R469
100K_0402_5%
ON/OFFBTN#
ON/OFFBTN#
<16,36>
JLED @
1
1 2
2 3
3 4
4 5
7
8 G1 5 6
G2 6
BATT_FULL_LED# <36>
BATT_CHG_LOW_LED# <36>
WL_BT_LED# <36>
JPWR @
5
6
E-T_6916K-Q06N-00L
TJG-533-V-T/R_6P
1
G1
G2
1
2
3
4
+5VALW
1
2
3
4
PBTN_LED#
ON/OFFBTN#
<36>
E-T_6916K-Q04N-03R
2
5
6
+5VALW
SW3
KEYBOARD CONN.
Card Reader + TP + Lid SW

JKB @
+3VS
2
1
R480 300_0402_5%
CLK_CR_R
CLK_CR#_R
DLW21HN900HQ2L_4P
1
2
R6
0_0402_5%
@EMI@
<10> PM_I2CSDA1
<10> PM_I2CSCL1
<16,17,8> PM_SMBDATA
<16,17,8> PM_SMBCLK
<36> LID_SW#
<10,9> TP_INTR#
<36> TP_DATA
<36> TP_CLK
R477 1
R478 1
R475 1
R476 1
TP_I2CSDA1
TP_I2CSCL1
@
@
CPU
2 0_0402_5%
2 0_0402_5%
H2
H_3P7
@
H3
H_4P3x4P0
@
H_4P1
@
PTH
NPTH
H4
H5
H_3P0
@
2 0_0402_5%
2 0_0402_5%
21
22
H1
H6
H7
H_3P0
@
H_3P0
@
H10
H_4P2x3P2N
@
H_3P0N
@
GND
GND
H8
ACES_50578-0200N-001
H9
H_3P0
@
H11
H_3P0
@
H12
H_3P0
@
H13
H_3P1
@
H_3P0
@
CLK_CR#
EMI@
<8>
L57
CLK_CR
Screw Hole
R7 1 @EMI@ 2 0_0402_5%
<8>
<11> PCIE_PTX_C_CRRX_P2
<11> PCIE_PTX_C_CRRX_N2
<11> PCIE_PRX_C_CRTX_P2
<11> PCIE_PRX_C_CRTX_N2
<32,33,9> PLT_RST_BUF#
<8> CLKREQ_CR#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
KSO16
+3VS_NUM
+3VL
KSO17
JCARD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
+3VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND1
GND2
+3VS_CAP
KSI1
KSI6
KSI5
KSI0
KSI4
KSI3
KSI2
KSI7
KSO15
KSO12
KSO11
KSO10
KSO9
KSO8
KSO13
KSO7
KSO6
KSO14
KSO5
KSO3
KSO4
KSO0
KSO1
KSO2
NUM_LED#
<36>
<36> CAPS_LED#
2
1
R483 300_0402_5%
+3VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CVILU_CF17341U0R0-NH
PCB Fedical Mark PAD
<36>
<36>
FD1
ISPD
R1 PN
UC1
4005UR1@
GPU
CPU
FD2
@
FD3
@
FD4
@
KSI[0..7]
KSO[0..17]
KSI[0..7]
KSO[0..17]
R3 PN
UC1
4005UR3@
UV1
TOPAZ@
ZZZ
SA000072Q70
SA000072Q60
I3-4005U
I3-4005U
UC1
UC1
DAZ15H00100
PCB LA-B301PR10
4200UR1@
4200UR3@
SA00006SM80
SA00006SM90
I5-4200U
I5-4200U
UC1
UC1
TOPAZ XT S3 FCBGA 631P GPU 0FD
UV1
4010UR1@
SA00006SXA0
SA00006SX90
I3-4010U
I3-4010U
UC1
JET@
4010UR3@
JET PRO S3 FCBGA 631P GPU 0FD
2990UR1@
SA00007LM00
2990U
A
UC1
4210UR1@
SA00007LO00
I5-4210U
UC1
4015UR1@
Issued Date
Compal Secret Data
SA00007LN00
2013/09/25
Deciphered Date
2016/09/25
Title
Size
I3-4015U
Date:
TP/ISPD/KB/Screw
Document Number
Rev
1.0
1
Sheet
37
of
52
+3VALW TO +3VS
+5VALW TO +5VS
Load Switch
VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
+5VALW
For ESD
+5VS
PJ3 @
U3
1
2
C537
1U_0402_6.3V6K
SUSP#
+5VALW
SUSP#
+3VALW
6
7
VIN1
VIN1
VOUT1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
14
13
+5VS_LS
12
C538
1
180P_0402_50V8J
2
C540
1
330P_0402_50V7K
2
2
PAD-OPEN 4x4m
11
10
9
8
PJ5
+3VS_LS
15
GPAD
TPS22966DPUR_SON14_2X3
C542
+5VS
C539
0.1U_0402_10V7K
@
+5VALW
+3VS
@
2
PAD-OPEN 4x4m
C541
@
C549
0.1U_0402_10V7K
ESD@
C550
0.1U_0402_10V7K
@ESD@
2 0.1U_0402_10V7K
1U_0402_6.3V6K
+5VS TO +5VS_ODD
Need mount RM3 if system
don't support ZPODD
+5VALW
1 Rshort@ 2
RM3
0_0805_5%
+5VS_ODD
+5VS
R482
100K_0402_5%
PCH_PWR_EN#
+5VS
VIN
VIN
VOUT
VOUT
ON
CT
<13>
PCH_PWR_EN#
<36>
Q195A
2N7002DW-T/R7_SOT363-6
PCH_PWR_EN
6
1
VBIAS
5
9
GND
GND
ZPODD@
C545
270P_0402_50V7K
C544
0.1U_0402_10V7K
@
+5VALW
+0.675VS
TPS22967DSGR_SON8_2X2
please refer to the table to choose C545
R485
100K_0402_5%
R486
22_0805_5%
R487
470_0805_5%
Need mount RM5 if system

don't support ISCT
D Q189
Q60
SUSP
S 2N7002KW_SOT323-3
2N7002KW_SOT323-3
+3V_WLAN
1 Rshort@ 2
RM5
0_0805_5%
+3VS
Q5539A
2N7002DW-T/R7_SOT363-6
SUSP#
<36,44,46>
+3VALW TO +3V_WLAN
for WOWL
SUSP
+1.05VS_VTT
ODD_EN
+5VS_ODD_LS
<10>
7
8
ZPODD@
1
2
RM6
0_0805_5%
ZPODD@
1
2
C543
1U_0402_6.3V6K
+5VS_ODD
VIN 0.8V-5.5V (VBIAS=5V),IMAX=4A,Rds=22mohm

U7
Part number is SA000070S00

+5VS
Part number is SA000070S00

3
U8
1
2
C546
1U_0402_6.3V6K
1
<36>
+3V_WLAN
VIN 0.8V-5.5V (VBIAS=5V),IMAX=4A,Rds=22mohm
+3VALW
WOWL_EN
WOWL_EN
+5VALW
VIN
VIN
ON
VOUT
VOUT
CT
VBIAS
GND
GND
+3VALW
7
8
ISCT@
1
+3V_WLAN_LS
RM7
2
0_0805_5%
6
1
5
9
ISCT@
C548
270P_0402_50V7K
C547
0.1U_0402_10V7K
@
TPS22967DSGR_SON8_2X2
please refer to the table to choose C548
1
RM4
10K_0402_5%
ISCT@
NOISCT@
WOWL_EN
RM2
10K_0402_5%
ISCT@
Issued Date
Compal Secret Data
2013/09/25
Deciphered Date
2016/09/25
Title
Size
Date:
DC-DC INTERFACE
Document Number
Rev
1.0
Sheet

E
38
of
52
Mark Green frame that means this part is not belong to layout module part .
Function Field :
D
Support 37.1
RTC 38.2
EMI Part 47.1
VIN
EMI@ PC1
1000P_0603_50V7K
1
2
EMI@ PL2
FBMA-L11-201209-121LMA50T_0805
EMI@ PC2
100P_0603_50V8
EMI@ PL1
FBMA-L11-201209-121LMA50T_0805
1
2
EMI@ PC3
100P_0603_50V8
PF1
5A_32V_F1206HI5000V032TM
1
2
DC_IN_S1
DC_IN
1
2
3
4
1
2
3
4
@ PJP1
ACES_50299-00401-001
EMI@ PC4
1000P_0603_50V7K
Compal Secret Data
Issued Date
Title
Deciphered Date
5

DCIN
Size
A3
Date:
Document Number
Rev
1.0
Sheet
1
39
of
52
Function Field :
Support 37.1
OTP 39.7
EMI Part 47.1
ESD DIODE 47.2
OTP
VMB
PF2
10A_24V_F1206HB10V024TM
1
2
@ PJP2
+3VL
EMI@
PL3
FBMA-L11-201209-121LMA50T_0805
1
2
<36,41>
BATT+
ADP_I
+RTC_R
<36>
<36>
@ PR10
0_0402_5%
1
2
VCIN0_PH
PR2
6.49K_0402_1%
1
2
PR5
PR4
2
BATT_PRES
Recovery
0.55V
0.43V
45W
UMA
<36>
100_0402_1%
Initial
PR3
1K_0402_1%
100_0402_1%
+3VL
EMI@ PD1
PJSOT24C_SOT23-3
@ PC7
0.1U_0402_10V7K
EMI@ PD2
PJSOT24C_SOT23-3
2
1
3
PR7
20K_0402_1%
@ PR8
0_0402_5%
1
2
PROCHOT_IN
EMI@ PC6
0.01U_0402_25V7K
SUYIN_200045MR009G171ZR
EMI@ PC5
1000P_0402_50V7K
PR9
12.1K_0402_1%
PR1
1K_0402_1%
PR6
1K_0402_1%
PH1
100K_0402_1%_TSM0B104F4251RZ
1
2
EMI@
PL4
FBMA-L11-201209-121LMA50T_0805
BATT_P5
EC_SMDA
EC_SMCA
GND
GND
BATT_S1
10
11
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
EC_SMB_DA1
<36,41>
EC_SMB_CK1
<36,41>
CPU
OTP
Initial
Recovery
90 C
70 C
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
5
Title
Size
A3
Date:

Battery Conn / OTP
Document Number
Sheet
1
40
Rev
1.0
of
52
Module model information
BQ24735A_V1.mdd
BQ24735A_V2.mdd
Function Field :
2
G
3
PQB05
2N7002KW_SOT323-3
PRB11
PRB12
1
2
1M_0402_5%
1
2
5
PQB01
AON7408L
PCB20
0.1U_0603_16V7K
PCB06
10U_0805_25V6K
PCB05
10U_0805_25V6K
PCB29
0.1U_0402_25V6
CSON1
1
2
1 CSOP1
2
BQ24725A_BATDRV
11
EMI@ PCB02
680P_0402_50V7K
12
PRB24
10_0603_1%
2 CSOP1
SRP1
PRB23
6.8_0603_1%
2 CSON1
SRN1
13
1
14
EMI@ PRB02
4.7_1206_5%
DL_CHG
ILIM
BQ24735RGRR_QFN20_3P5X3P5
10
+3VALW
2
PRB21
316K_0402_1%
VIN
PRB13
309K_0402_1%
2
BQ24725A_ILIM
1
BATDRV
PQB02
AON7406L
SRN
15
PCB28
0.1U_0402_25V6
3
2
1
5
3
2
1
ACDRV
BQ24725A_ACDET
PCB27
0.01U_0402_50V7K
1
2
1
2
@EMI@ PCB24
0.1U_0402_25V6
BATT+
PLB03
PRB51
4.7UH_5.5A 7X7X3 MOLDING
0.01_1206_1%
1
2
4
BQ24725A_LX
CHG1
SRP
PRB18
422K_0402_1%
1
2
REGN
BTST
HIDRV
CMSRC
<36,9> ACIN
@EMI@ PCB23
2200P_0402_25V7K
1
1
2
BQ24725A_REGN
16
PRB25
2.2_0603_5%
1
BQ24725A_BST2
17
DH_CHG
18
PRB26
10_1206_1%
BQ24725A_LX
19
1 1
GND
ACOK
PCB21
1U_0603_25V6K
ACP
VIN
PRB22
100K_0402_1%
PRB28
0_0402_5%
1
2
DH_CHG
2
100K_0402_1%
2 BQ24725A_BATDRV_1
PDB02
RB751V-40_SOD323-2
SCL
1
PRB17
VF = 0.37V
LODRV
+3VL
PRB27
4.12K_0603_1%
ACN
SDA
BQ24725A_ACDRV 4
BQ24725A_BATDRV
PCB01
0.047U_0402_25V7K
1
2
2
BQ24725A_CMSRC 3
PAD
PHASE
IOUT
21
VCC
PUB00
20
1U_0603_25V6K
ACDET
PRB16
4.12K_0603_1%
PCB22
1
2
BQ24725A_ACN
BQ24725A_ACP
PRB15
4.12K_0603_1%
PCB14
0.1U_0402_25V6
BQ24725A_IOUT
VF = 0.5V
PDB01
BAS40CW_SOT323-3
BQ24725A_VCC2
1
2
PCB13
0.1U_0402_25V6
BQ24725A_ACDRV_1
VIN
PCB26
10U_0805_25V6K
PQB07
SI7716ADN-T1-GE3_POWERPAK8-5
1
2
5
3
CHG_B+
EMI@ PLB01
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2
PCB19
0.01U_0402_25V7K
PRB50
0.01_1206_1%
4
PCB15
0.1U_0402_25V6
1
2
PCB11
0.01U_0402_25V7K
@ PRB10
0_0402_5%
PQB03
AON6414AL
P2
PCB25
10U_0805_25V6K
PQB04
1
2
3
5
1
2
3
1
2
P1
@ PCB10
2200P_0402_50V7K
B+
1
2
3M_0402_5%
VIN
Regulator 40.1
Support 40.2
EMI Part 47.1
Vin Dectector
ADP_V
<36>
EC_SMB_CK1
<36,40>
PRB14
@ PCB12
0.1U_0402_10V7K
47K_0402_1%
EC_SMB_DA1
@ PRB20
0_0402_5%
1
2
ADP_I
<36,40>
<36,40>
For A51 ADP_V function
PCB17
100P_0402_50V8J
2
1
VILIM = 20*ILIM*Rsr
ILIM = 3.3*100/(100+107)/20/0.02
= 3.986 A
PRB19
66.5K_0402_1%
1
Max.
18.12V
17.70V
Typ
17.63V
17.22V
PCB16
0.047U_0402_25V7K
2
1
L-->H
H-->L
Min.
17.16V
16.76V
Close EC chip
@ PCB18
@PCB18
100P_0402_50V8J
Issued Date
Compal Secret Data

Title
Deciphered Date
Custom
Date:
CHARGER
Rev
1.0
Sheet
1
41
of
52

SY8206B_V2.mdd
Function Field :
D
Regulator 35.1
Support 35.2
EMI Part 47.1
PR304
499K_0402_1%
1
2
ENLDO_3V5V
3.3V LDO 150mA~300mA
PC311
10U_0805_25V6K
2
1
EN2
IN
EN1
FB
BS
3
6
1
BST_3V
3V_FB
PR301
2
0_0603_5%
PC301
2
PL303
EMI@ PC302
2
1
PR310
100K_0402_1%
1
2
Ipeak : 5A
Imax : 3.5A
Iocp : 6A
FSW : 750KHz
C
PJ303
1
+3VALWP
+3VALW
JUMP_43X118
PR306
2.2K_0402_5%
1
2
<36> EC_ON
PJ302
1
+3VLP
+3VL
JUMP_43X39
@ PR307
1
<36> VS_ON
Place to 3V EN1 pin
0_0402_5%
@ PR311
0_0402_5%
1
2
3V5V_EN_3
1
2
SY8208C_V2.mdd
1
PR308
1M_0402_1%
PC304
4.7U_0402_6.3V6M
3V5V_EN
B+
+3VALWP
PC307
22U_0603_6.3V6M
1
PC309
4.7U_0603_6.3V6M
PC306
22U_0603_6.3V6M
2
1
+3VLP
LDO
+3VALWP
PC305
22U_0603_6.3V6M
2
1
PG
PC312
0.047U_0402_16V4Z
OUT
2.2UH_PCMB063T-1R0MS_12A_20%
4.7_1206_5%
GND
LX_3V
4
EMI@ PR302
2
1
3V_SN
10
POK
+3VL
B+
0.1U_0603_25V7K
LX
SY8206BQNC_QFN10_3X3
<36,9>
PC303
PR303
0.01U_0402_25V7K 1K_0402_5%
1
2
1
2
3V5V_EN_3
470P_0603_50V7K
EMI@ PC314
2200P_0402_50V7K
2
1
3V_VIN
PR305
1M_0402_1%
2
1
PU300
7
EMI@ PL301
HCB2012KF-121T50_0805
1
2
@EMI@ PC313
0.1U_0402_25V6
2
1
B+
EMI@ PL351
HCB2012KF-121T50_0805
1
2
5V_VIN
PU350
4
7
VL
SY8208CQNC_QFN10_3X3
+5VALWP
1
+
PC360
150U_D2_2V_Y
LDO
2
PC358
22U_0603_6.3V6M
PG
LX_5V
PC357
22U_0603_6.3V6M
2
1
OUT
10
PC356
22U_0603_6.3V6M
2
1
LX
VCC
+5VALWP
PL353
2.2UH_PCMB063T-1R0MS_12A_20%
PC355
22U_0603_6.3V6M
2
1
GND
PC351
0.1U_0603_25V7K
1
2
PC353
PR353
6800P_0402_25V7K 1K_0402_5%
1
2
1
2
PR351
0_0603_5%
2
BST_5V
PC365
4.7U_0603_6.3V6M
VCC_3V
5V_FB
4.7_1206_5%
BS
3V5V_EN
Ipeak : 8A
Imax : 5.6A
Iocp : 9A
FSW : 750KHz
2@
PJ352
1
+5VALWP
Issued Date
Compal Secret Data

Title
Deciphered Date
Custom
Date:
+5VALW
JUMP_43X118
680P_0603_50V7K
FB
@EMI@ PR352
2
1
EN
5V_SN
IN
PC359
4.7U_0603_6.3V6M
@EMI@ PC352
2
1
PC362
10U_0805_25V6K
2
1
PC361
10U_0805_25V6K
2
1
EMI@ PC364
2200P_0402_50V7K
2
1
@EMI@ PC363
0.1U_0402_25V6
2
1
+3VALW / +5VALW
Rev
1.0
Sheet
1
42
of
52

RT8207M_V1.mdd
RT8207M_V2.mdd
For Single layer

For Dual layer
Function Field :
D
Regulator 35.3
Support 35.4
EMI Part 47.1
PRW01
0_0603_5%
1
2
BST_1.35V
BOOT_1.35V
+1.35VP
+0.675VSP
VTT
VLDOIN
21
1
C
+1.35VP
VTTREF_1.35V
FB
S3
PCW10
0.033U_0402_16V7K
S5
FB_1.35V
PRW10
8.06K_0402_1%
1
2
+1.35VP
UMA@ PRW12
UMA@PRW12
510K_0402_1%
1
2
1.35V_B+
VDDQ
VDD
+5VALW
DIS@ PRW12
825K_0402_1%
BOOT
VTTREF
EN_1.35V
PCW13
1U_0603_10V6K
GND
RT8207MZQW_WQFN20_3X3
VDDP
EN_0.675VSP
11
VDD_1.35V
CS
TON
12
PGOOD
+5VALW
VTTSNS
10
PGND
PAD
VTTGND
DIS@ PUW00
13
@EMI@ PCW02
680P_0402_50V7K
PRW14
5.1_0603_5%
1
2
@EMI@ PRW02
4.7_1206_5%
1 2
DIS@ PCW05
150U_D2_2V_Y
DIS@ PQW02
FDMC7692S_MLP8-5
1
2
3
5
+1.35VP
PRW03
13.7K_0402_1%
1
2 CS_1.35V
PCW14
1U_0603_10V6K
1
2
1
2
3
PLW03
1UH_VMPI0703AR-1R0M-Z01_11A_20%
1
2
LGATE
1
14
PHASE
15
DL_1.35V
TON_1.35V
PQW01
AON7408L_DFN8-5
Ipeak : 10A
Imax : 7A
Iocp : 12A
FSW : 500KHz
UGATE
20
19
18
PCW01
0.1U_0603_25V7K
16
+1.35VP
PCW07
10U_0805_6.3V6K
SW_1.35V
PCW06
10U_0805_6.3V6K
DH_1.35V
PCW16
10U_0805_25V6K
PCW15
10U_0805_25V6K
EMI@ PCW18
2200P_0402_50V7K
@EMI@ PCW17
0.1U_0402_25V6
1.35V_B+
17
EMI@ PLW01
HCB2012KF-121T50_0805
1
2
B+
@ PCW12
0.1U_0402_10V7K
PRW11
10K_0402_1%
2
@ PRW04
0_0402_5%
1
2
<36> SYSON
@
1
+1.35VP
PJW02
2
2
@PRW05
@
PRW05
0_0402_5%
1
2
+1.35V
<16> DDR_VTT_PG_CTRL
JUMP_43X118
@
1
+0.675VSP
PJW04
2
2
@ PCW11
0.1U_0402_10V7K
+0.675VS
JUMP_43X39
1
2
@UMA@ PCW68
22U_0603_6.3V6M
near HW VDDQ
@UMA@ PCW67
22U_0603_6.3V6M
1
2
UMA@ PCW66
22U_0603_6.3V6M
UMA@ PCW65
22U_0603_6.3V6M
+1.35V
UMA@ PCW64
22U_0603_6.3V6M
1
2
1
2
UMA@ PCW63
22U_0603_6.3V6M
UMA@ PCW62
22U_0603_6.3V6M
+1.35VP
UMA@ PCW61
22U_0603_6.3V6M
For UMA SKU
UMA@ PUW00
RT8207P
UMA@ PQW02
Issued Date
Compal Secret Data

Title
Deciphered Date
Custom
Date:
+1.35V / +0.675VS
Rev
1.0
Sheet
1
43
of
52

SY8206D_V1.mdd
Function Field :
Regulator 35.5
Support 35.6
EMI Part 47.1
EN pin don't floating
If have pull down resistor at HW side, pls delete PR2
SUSP#
<36,38,46>
@ PRH05
0_0402_5%
1
2
@ PCH11
0.22U_0402_10V6K
PRH06
1M_0402_1%
Ipeak : 5A
Imax : 3.5A
Iocp : 6A
FSW : 800KHz
SY8206DQNC_QFN10_3X3
1
2
PCH08
22U_0603_6.3V6M
1
2
1
2
@
1
+1.05VSP
PJH02
2
2
+1.05VS_VTT
JUMP_43X118
PRH13
20K_0402_1%
2
1
2
PCH16
4.7U_0603_6.3V6K
VCCST_PWRGD
+3VALW
PCH07
22U_0603_6.3V6M
LDO_3V
PCH06
47U_0805_6.3V6M
LDO
PCH05
47U_0805_6.3V6M
PG
FB
+1.05VSP
1
BYP
PLH03
1UH_PCMB063T-1R0MS_12A_20%
1
2
10 LX_1.05V
ILMT
PCH01
0.1U_0603_25V7K
1
2
PCH18
330P_0402_50V7K
LX
PRH01
0_0603_5%
1
2
BST_1.05V
GND
PRH12
15K_0402_1%
BS
9
3
+1.05V_PGOOD
EN
PCH13
10U_0805_25V6K
IN
PCH17
4.7U_0603_6.3V6K
2
PRH11
10K_0402_5%
PCH12
10U_0805_25V6K
2
1
1
2
+3VS
@EMI@ PCH15
0.1U_0402_25V6
2
1
B+_1.05V
<12,36>
+1.05VSP
@EMI@ PCH02
680P_0603_50V7K
1
2
SNB_1.05V
PUH00
EMI@ PCH14
2200P_0402_50V7K
2
1
B+
@EMI@ PRH02
4.7_1206_5%
1
2
EMI@ PLH01
HCB2012KF-121T50_0805
1
2
Pin 7 BYP is for CS.

Common NB can delete
+3VALW and PC15
The current limit is set to 6A, 8A or 12A when this pin

is pull low, floating or pull high
Issued Date
Compal Secret Data

Title
Deciphered Date
Custom
Date:
+1.05VS
Rev
1.0
Sheet
1
44
of
52

SY8033_V1.mdd
Function Field :
D
Regulator 35.15
Support 35.16
EMI Part 47.1
+0.95VGSP
Ipeak : 3A
Imax : 2.1A
Iocp : 4A
FSW : 1MHz
2
+0.95VGSP
1
2
DIS@ PCF06
22U_0603_6.3V6M
1
2
@
1
+1.8VGSP
Ipeak :1A
Imax : 0.7A
Iocp : 2.5A
FSW : 1MHz
DIS@ PU1800
SY8032ABC_SOT23-6
1
2
PJ1802
2
2
+1.8VGS
JUMP_43X79
FB_1.8V
+1.8VGSP
@EMI@ PC1802 DIS@ PR1812

680P_0402_50V7K 10K_0402_1%
2
DIS@ PR1805
1M_0402_1%
DIS@ PR1811
20K_0402_1%
DIS@ PC1806
22U_0603_6.3V6M
@EMI@ PR1802
4.7_0603_5%
+1.8VSP_ON
EN
+1.8VGSP
2
DIS@ PC1805
22U_0603_6.3V6M
FB
GND
DIS@ PL1803
1UH_PH041H-1R0MS_3.8A_20%
1
2
LX_1.8V
DIS@ PR1804
0_0402_5%
1
2
DIS@ PC1811
0.1U_0402_16V7K
PXS_PWREN
<10,20,45,48,9>
PG
LX
DIS@ PC1812
68P_0402_50V8J
2
1
5
B
IN
+3VALW
+0.95VGS
DIS@ PRF12
34K_0402_1%
PJ1801
JUMP_43X79
1
2
1
2
PJF02
2
2
JUMP_43X79
DIS@ PC1810
22U_0805_6.3VAM
1
FB_0.95V
DIS@ PCF05
22U_0603_6.3V6M
DIS@ PCF12
68P_0402_50V8J
2
1
1
2
DIS@ PRF11
20K_0402_1%
+0.95VGSP
1
2
1
DIS@ PUF00
SY8033BDBC_DFN10_3X3
@EMI@ PRF02
4.7_0603_5%
PG
FB
EN
1
2
SVIN
+0.95VSP_ON
DIS@ PRF05
1M_0402_5%
LX
LX_0.95V 1UH_PH041H-1R0MS_3.8A_20%
@EMI@ PCF02
680P_0402_50V7K
DIS@ PRF04
0_0402_5%
1
2
PXS_PWREN
<10,20,45,48,9>
PVIN
NC
DIS@ PCF10
22U_0805_6.3VAM
DIS@ PLF03
LX
NC
JUMP_43X79
PVIN
TP
11
10
PJF01
1
DIS@ PCF11
0.1U_0402_16V7K
+3VALW
Note:Use VCCSA_SEL to switch High & Low Level for VID[1]

(ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.
Issued Date
Compal Secret Data

Title
Deciphered Date
Custom
Date:
+0.95VGS / +1.8VS
Rev
1.0
Sheet
1
45
of
52

APL5930_V1.mdd
Function Field :
D
Regulator 35.31
Support 35.32
EMI Part 47.1
+5VALW
+1.5VSP
PCM13
1U_0402_6.3V6K
Ipeak : 0.5A
Imax : 0.35A
Iocp : 4.2A
PRM11
1.54K_0402_1%
+1.5VSP
+1.5VSP
PCM14
0.01U_0402_25V7K
PJM02
2
2
+1.5VS
C
JUMP_43X79
PCM05
22U_0603_6.3V6M
@ PRM05
@PRM05
47K_0402_5%
+1.5V_FB
+1.5V_EN
GND
@ PRM04
0_0402_5%
1
2
PCM12
0.1U_0402_16V7K
SUSP#
<36,38,44>
PUM00
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT
8
7 EN
2
POK
FB
PCM11
4.7U_0805_6.3V6K
@ PJM01
JUMP_43X39
+3VALW
PRM12
1.74K_0402_1%
Issued Date
Compal Secret Data

Title
Deciphered Date
Custom
Date:
+1.5VS
Rev
1.0
Sheet
1
46
of
52

TPS51622_V2A.mdd
TPS51624_V2B.mdd
for IC portion
for SW portion
VR_HOT#
PR606 10K ohm for 100 degree
PR606 8K ohm for 110 degree
CPU
Frequency = 1MHz
OCP Current 39 A
DCR: 0.85m +-7% ohm
PH601 B value: 4250k 1%
PH602 B value: 3435k 1%
Function Field :
D
VREF
Regulator 36.1
Driver 36.2
Support 36.3
Output Cap 36.4
Acoustic Cap 37.2
EMI Part 47.1
36.5K_0402_1%
2 PRZ13 1
1
PRZ14
2
20K_0402_1%
1
PRZ15
2
1
PRZ16
2
1
PRZ18
2
O-USR
100K_0402_1%
F-IMAX
150K_0402_1%
2 PRZ20 1
56K_0402_1%
B-RAMP
681K_0402_1%
75_0402_1%
@ PRZ17
2
1
1
PRZ19
2
442K_0402_1%
PCZ12
1
OCP-I
PRZ23
39K_0402_1%
PCZ13
0.01U_0402_16V7K
2
1
PRZ21
9.09K_0402_1%
2
1
SLEWA
@ PRZ22
75_0402_1%
4700P_0402_25V7K
IMON
PHZ01
100K_0402_1%_TSM0B104F4251RZ
EMI@ PLZ01
FBMA-L11-201209-121LMA50T_0805
1
2
1
2
EMI@ PLZ02
FBMA-L11-201209-121LMA50T_0805
B+
PRZ24
10K_0402_5%
1
2
CPU_B+
CPU_B+
1
+
PCZ31
33U_25V_M
VIN MAX
19.5V
VIN MIN
12V
MAX current
32A
Thermal current
10A
Dynamic current
27A
OCP
38.4A
Switching frequency
1.2MHz
Boot voltage
1.7V
DC Load- line
2m Ohm
+CPU_CORE
1
+
PCZ77
220U_D2 SX_2VY_R9M
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
PRZ31
130_0402_1%
1
PRZ30
54.9_0402_1%
2
@ PCZ76
22U_0603_6.3V6M
@ PCZ75
22U_0603_6.3V6M
PCZ74
22U_0603_6.3V6M
PCZ17
1U_0603_10V6K
PCZ68
22U_0603_6.3V6M
PCZ67
22U_0603_6.3V6M
PCZ66
22U_0603_6.3V6M
VR_SVID_DAT
PCZ73
22U_0603_6.3V6M
<12>
PCZ65
22U_0603_6.3V6M
VR_SVID_ALRT#
PCZ72
22U_0603_6.3V6M
VR_SVID_CLK
<12>
PCZ71
22U_0603_6.3V6M
<12>
PCZ18
0.1U_0402_25V6
PCZ70
22U_0603_6.3V6M
VR_HOT#
PCZ69
22U_0603_6.3V6M
+1.05VS_VTT
PCZ64
22U_0603_6.3V6M
+CPU_CORE
2@
VR_SVID_CLK
VR_SVID_ALRT#
VR_SVID_DAT
Issued Date
Compal Secret Data

Title
Deciphered Date
Custom
Date:
CSN1
PRZ28
10_0603_1%
CSP1
PCZ21
0.15U_0402_10V6K
+5VS
PCZ20
0.15U_0402_10V6K
2
1
PRZ33
2.55K_0402_1%
PCZ19
1U_0603_10V6K
PCZ63
22U_0603_6.3V6M
<36>
PCZ33
10U_0805_25V6K
2
1
PAD
33
CPU_B+
+3VS
1_0603_5%
@ PRZ32
CSD97374CQ4M_SON8_3P5X4P5 0_0402_5%
<12>
+CPU_CORE
PHZ02
10K_0402_1%_TSM0A103F34D1RZ
VGATE
2
2
2 SKIP#
CSP
PRZ11
6
5
PLZ03
0.15UH_FDUE0630-HR1_40A_20%
1
4
LX_CORE
4.7_1206_5%
2
PRZ01
2.2_0603_5%
4
3
2
1 SKIP#-1
1
EMI@PCZ36
2200P_0402_50V7K
2
1
3
2
+1.05VS_VTT
@EMI@ PCZ35
0.1U_0402_25V6
2
1
2
10K_0402_1%
PCZ34
10U_0805_25V6K
2
1
1
4
PGND2
PWM
BOOT VSW
PGND1
BOOT_R VDD
VIN
SKIP#
680P_0603_50V7K
PRZ12
EMI@ PCZ04
EMI@ PRZ04
2
1
2
1
PCZ11
1U_0603_10V6K
11
10
F-IMAX
O-USR
ALERT#
VCLK
PUZ01
9
8
7
PCZ01
0.1U_0402_25V6
1
2
PCZ62
22U_0603_6.3V6M
PRZ26
PCZ15
4.75K_0402_1% 1500P_0402_50V7K
+5VALW
PWM1
PWM1
PCZ61
22U_0603_6.3V6M
<12>
VR_SVID_DAT
VREF
PCZ16
0.33U_0603_10V7K
SKIP#
VR_SVID_ALRT#
1 PRZ25 2
10K_0402_5%
2
VR_ON
4.87K_0402_1%
100P_0402_50V8J
B-RAMP
12
OCP-I
14
13
IMON
SLEWA
PRZ27
@ PRZ07
0_0402_5%
1
2
PRZ35
3.01K_0402_1%
2
1
2
PRZ34
9.53K_0402_1%
2
1
@ PCZ14
1
2
VR_SVID_CLK
VDIO
32
VFB
VDD
31
24
PGOOD
GFB
VR_HOT#
VCCSENSE
N/C
30
VCC_SENSE
23
N/C
GND
<12>
VSSSENSE
PWM2
TPS51624RSM_QFN32_4X4
PU3
25
VSS_SENSE
CSP2
29
22
<12>
PWM1
V5A
21
+3VS
CSN2
VREF
20
SKIP#
COMP
19
VR_ON
CSN1
28
18
27
CSN1
CSP1
DROOP
17
26
CSP1
THERM
15
VBAT
PUZ00
16
CPU_CORE
Rev
1.0
Sheet
1
47
of
52
Function Field :
Close VGA chip
VCCSENSE_VGA

RT8880A_V1B.mdd for SW portion
UGATE1
46
BOOT1
PRV26
0_0402_5%
1
2
VCC
1
1
45
44
43
42
EMI@ PCV29
2200P_0402_50V7K
2
1
@EMI@ PCV28
@EMI@PCV28
0.1U_0402_25V6
2
1
PCV27
10U_0805_25V6K
2
1
PCV26
10U_0805_25V6K
2
1
@EMI@ PRV05
@EMI@PRV05
4.7_1206_5%
2
1
2
@EMI@PCV05
@EMI@
PCV05
680P_0603_50V7K
PRV27
10_0603_5%
VGA_B+
3
2
1
1
BOOT1-1
<10,20,45,9>
3
2
1
LGATE1
PXS_PWREN
PCV32
0.1U_0402_25V6
PRV01
PCV01
2.2_0603_1% 0.22U_0603_25V7K
+3VS
PRV20
124K_0402_1%
1
2
PRV29
2.61K_0402_1%
1
2
SNB_APU1
EMI@PCV23
EMI@
PCV23
2200P_0402_50V7K
2
1
@EMI@PCV22
@EMI@
PCV22
0.1U_0402_25V6
2
1
PQV01
AON7518_DFN8-5
PRV28
0_0603_5%
1
2
PHASE1
PQV02
AON7516_DFN8-5
DGPU_PWRGD
PCV21
10U_0805_25V6K
2
1
PCV20
10U_0805_25V6K
2
1
40
PRV25
100K_0402_5%
41
+5VS
PQV03
AON7518_DFN8-5
+5VS
PVCC
BOOT11
ISEN2N-1
PHASE1
47
PCV31
0.1U_0402_25V6
LGATE1
48
PVCC
49
PGOOD
ISENA1P
50
UGATE1
<18,9>
IBIAS
VCC
PCV30
.1U_0402_16V7K
PRV35
787_0402_1%
2
ISEN2N 1
38
37
27
LGATE2
<19>
PRV24
100K_0402_1%
2
1
@ PRV30
@PRV30
4.12K_0402_1%
1
2
ISEN1N-1
+5VS
+VGA_CORE
PC717
2.2U_0402_6.3V6M
1
+
1
+
PC701
560U_D2_2V_Y
PC700
330U_D2_2V_Y
PC729
10U_0603_6.3V6M
PC728
10U_0603_6.3V6M
2
1
PC727
10U_0603_6.3V6M
2
1
PC726
10U_0603_6.3V6M
2
1
PC725
10U_0603_6.3V6M
2
1
PC724
10U_0603_6.3V6M
2
1
PC723
10U_0603_6.3V6M
2
1
PC722
10U_0603_6.3V6M
2
1
10uF x 8pcs
PC721
1U_0402_6.3V6K
1
2
PC720
1U_0402_6.3V6K
2
1
PC719
0.1U_0402_25V6
PC718
0.1U_0402_25V6
2
1
1
2
+VGA_CORE
1uF x 2pcs
PC716
2.2U_0402_6.3V6M
2
1
PC715
2.2U_0402_6.3V6M
2
1
PC714
2.2U_0402_6.3V6M
2
1
PC713
2.2U_0402_6.3V6M
2
1
PC712
2.2U_0402_6.3V6M
2
1
PC711
2.2U_0402_6.3V6M
2
1
PC710
2.2U_0402_6.3V6M
2
1
PC709
2.2U_0402_6.3V6M
2
1
PC708
2.2U_0402_6.3V6M
2
1
PC707
2.2U_0402_6.3V6M
2
1
PC706
2.2U_0402_6.3V6M
2
1
PC705
2.2U_0402_6.3V6M
2
1
PC704
2.2U_0402_6.3V6M
2
1
PC703
2.2U_0402_6.3V6M
2
1
PC702
2.2U_0402_6.3V6M
2
1
1
2
+VGA_CORE
PCV25
0.1U_0402_25V6
PRV31
787_0402_1%
2
ISEN1N 1
2.2uF x 16pcs
SET2
PRV22
124K_0402_1%
1
2
+VGA_CORE
PLV03
0.22UH_PCME064T-R22MS0R985_28A _20%
PCV24
.1U_0402_16V7K
ISEN1P
PRV23
470_0402_1%
1
2
+VGA_CORE
PLV04
0.22UH_PCME064T-R22MS0R985_28A _20%
@PRV34
@
PRV34
4.12K_0402_1%
1
2
@EMI@ PRV04
@EMI@PRV04
4.7_1206_5%
TONSETA
PCV17
0.47U_0402_6.3V6K
PRV21
20.5K_0402_1%
1
2
SET1
@EMI@ PCV04
@EMI@PCV04
680P_0603_50V7K
SET2
Pull high at HW side
SNB_APU2
PWMA2
51
PCV18
2.2U_0603_10V7K
SET1
EN
BOOTA1
PHASE2
PCV19
2.2U_0603_10V7K
2
1
UGATEA1
OFSA
52
B+
D
PRV33
2.61K_0402_1%
1
2
53
1
1
OCP_L
VREF_VGA
3
2
1
3
2
1
OFS
PRV19
21K_0402_1%
PQV04
AON7516_DFN8-5
UGATE2
BOOT2
BOOT2
UGATE2
TONSET
TONSET
PWM3
ISEN2P
ISEN2N
ISEN2P
ISEN1N
ISEN2N
ISEN1P
ISEN1N
9
ISEN3P
ISEN3N
ISEN1P
10
FB
11
PHASEA1
36
26
SVT
ISENA1N
SET2
LGATEA1
35
25
BOOT1
SVD
OCP_L
SET1
UGATE1
PUV00
RT8880BGQW_WQFN52_6X6
SVC
ISENA2N
24
PWROK
34
23
PHASE1
ISENA2P
22
VDDIO
VSENA
SVI2_SVT
21
LGATE1
33
<19>
20
PVCC
IMONA
FBA
SVI2_SVD
19
V064
COMPA
SVI2_SVC
<19>
DGPU_PWROK
18
32
<19>
EMI@ PLV02
HCB2012KF-121T50_0805
1
2
ISEN2P
GND
LGATE2
31
17
VDDIO
+5VS
IMON
30
VREF_VGA 16
+1.8VGS
PCV02
0.22U_0603_25V7K
LGATE2
PHASE2
PRV18
3.6K_0402_1%
1
2
PHV01
100K_0402_1%_TSM0B104F4251RZ
2
1
PRV17
30K_0402_1%
2
1
DGPU_PWRGD
PRV36
<18>
0_0402_5%
1
2
2 BOOT2-11
PRV02
2.2_0603_1%
RGND
IBIAS
PCV16
1U_0402_6.3V6K
1
2
C
+5VS
VSEN
COMP_VGA
13
COMP
IMON_VGA 15
BOOT2 1
VGA_B+
PRV11
100K_0402_1%
PCV11
68P_0402_50V8J
1
2
14
PHASE2
12
PCV12
560P_0402_50V7K
1
2
PRV32
0_0603_5%
1
2
UGATE2
PRV12
240K_0402_1%
1
2
PGOODA
PRV14
10K_0402_1%
1
2
39
@PCV15
@
PCV15
330P_0402_50V7K
FB
@ PCV13
680P_0402_50V7K
2
1
VGA_B+
+VGA_CORE
PRV15
10_0402_5%
VCC
28
PRV16
10_0402_5%
PRV13
2K_0402_1%
1
D
EMI@ PLV01
HCB2012KF-121T50_0805
1
2
RT8880A_V1A.mdd for IC portion
PCV14
0.01U_0402_50V7K
29
VSSSENSE_VGA<19>
<19>
Regulator 43.1
Support 43.2
Output Cap 43.9
EMI Part 47.1
VGA_CORE
TDC 24A
EDC 36A
OCP current > 43.2A
Load line -1mV/A
FSW=450kHz
DCR 0.98mohm +/-5%
TYP
MAX
H/S Rds(on) : 27mohm , 34mohm
L/S Rds(on) : 5.3mohm , 6.5mohm
0.1uF x 2pcs
Issued Date
Compal Secret Data

Deciphered Date
Title

VGA_CORE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date:
Rev
1.0
Sheet
1
48
of
52
PWR PIR (Product Improve Record)
ZSWAA LA-B301P SCHEMATIC CHANGE LIST

REVISION CHANGE: 0.2
PVT GERBER_OUT DATE: 2013/12/02
----------------------------------------------------------------------------------------------------------------------------------------------------------------Item
Date
Page
Action
Component
Request
----------------------------------------------------------------------------------------------------------------------------------------------------------------1)
11/21
48
Change
PRZ12 change to 10K and pull high +1.05VS_VTT
For design change
2)
11/21
48
Delete
PRZ29 removed
HW portion pull high
5)
11/25
41,48
Change
PH1,PHZ01 part number change to SL200002H00
change for common PN
6)
11/25
48
Change
PHZ02 part number change to SL200002F00
change for common PN
7)
11/25
42
Change
change PQB03 to SB00000NW00 AON6414AL
change for allocation
8)
12/03
48
Change
PRZ27 change to 4.87K
change for compensation
9)
12/03
41
Change
PF2 change to 1206 footprint component SP040005P00
for ME limitation
10)
12/03
44
Change
change PQW02 to SB00000GW00 SI7716 at UMA SKU
change for allocation
11)
12/03
48
Change
PRZ19 change to 316K
for CPU core conversation fine tune
12)
12/03
48
Change
PRZ20 change to 56K

PV REGRESSION GERBER_OUT DATE: 2014/01/06
----------------------------------------------------------------------------------------------------------------------------------------------------------------Item
Date
Page
Action
Component
Request
----------------------------------------------------------------------------------------------------------------------------------------------------------------13)
01/03
40
Change
change DC in jack footprint
for customer request
14)
01/03
43
Add
Add PR312 0ohm 0402
for HW 5V drop fine tune
15)
01/08
43
Change
change PR312 to 15ohm
for HW 5V drop fine tune
16)
01/08
47
Change
change PRZ19 to 442kohm
17)
01/15
41
Delete
PCB10 2200p
for B2B fine tune
18)
01/15
41
Change
PCB11 0.1u change to 0.01u
for B2B fine tune
19)
01/16
43
Add
PR302,PC302 mount and PC302 change to 470p
for EMI request
20)
01/16
42
change
PCB16 2200p change to 0.047u
for decoupling cap fine tune
21)
01/22
47
Add
PRZ04,PCZ04 mount
for EMI request
22)
01/22
41
Add
PRB02,PCB02 mount
for EMI request
23)
01/22
47
change
PCZ31 100u change to 33u
for sourcer request

Pre-MP GERBER_OUT DATE: 2014/02/10
----------------------------------------------------------------------------------------------------------------------------------------------------------------Item
Date
Page
Action
Component
Request
----------------------------------------------------------------------------------------------------------------------------------------------------------------24)
02/07
42
Delete
remove PR312 15ohm
for HW request
25)
02/07
48
Change
change net name from VREF to VREF_VGA
resolve duplicate net name
change net name from VREF to IMON_VGA
change net name from VREF to COMP_VGA
26)
02/10
42,44,46 Change
change PR311,PRH05,PRM04 footprint to 0ohm shortpad
common design rule
2010/09/03
Issued Date
Compal Secret Data
2012/12/31
Deciphered Date
Title
Custom
Date:
Power-PIR
Rev
1.0
Sheet
1
49
of
52
HW PIR (Product Improve Record)

ZSWAA LA-B301P Schematic Change List
REVISION: 0.1
Gerber-out date: 2013/10/29
Item
Date
Page
Action
Component
Request
---------------------------------------------------------------------------------------------------------------------------------------------1)
10/15
37
Add
CB14 on SUSP#
For ESD request
2)
10/15
16,17
Change
Swap DDR data of JDIMM1 & JDIMM2
For common module layout
3)
10/15
08
Add
RH91 on CLK_REQ_VGA#
For follow AMD GPU reference schematic
4)
10/15
34
Reserve
CR6 to +5VALW
For power switch common design
5)
10/15
35
Add
CR2,CR3,CR5 to +USB_VCCB
For power switch common design
6)
10/16
37
Add
RB11,RB12
For colay EC 9022
7)
10/16
37
Add
RB13,RB14
For colay Normal pad & Click pad
8)
10/17
38
Add
R8,R9
For colay Normal pad & Click pad
9)
10/17
27
Add
R15,C29 on LCD_ENVDD
For tune LCD_VDD sequence
10)
10/18
34
Swap
LR9
For smooth USB signal
11)
10/18
37
Change
DFAN1 to Pin 70
For EC request
12)
10/20
34
Remove
RT2, RT3
For no need
13)
10/22
39
Change
RM5,RM6,RM7 to 0_0805
For max current design
14)
10/22
10
Add
Test point on GPIO10
For SW debug
15)
10/22
07
Add
Test point on GPIO34
For SW debug
16)
10/23
16
Reserve
0_0805
For DQA's experiment
17)
10/23
05
Change
R23 to 121_0402_1%
For Intel check list
18)
10/23
38
Remove
SW2
For layout space concern
19)
10/23
30
Reserve
RD11, RD12
For Intel check list
20)
10/24
08
Change
Y2 to 4 pin
For common part
21)
10/24
10
Add
RH4, RH6, RH9, RH10
For SW request
22)
10/24
26
Change
RT1 from 0603 to 0805
For current concern
23)
10/24
09
Add
RH7, RH8
For SW request
24)
10/24
27
Change
JTOUCH from 4pin to 6pin
For module pin define
25)
10/27
20
Change
QV5 to AO4354
For sourcer request
26)
10/27
34
Change
UT1 P/N to SA00007IO00
For TPM2.0
2010/09/03
Issued Date
Compal Secret Data
2012/12/31
Deciphered Date
Title
Size
Date:
HW-PIR
Document Number
Rev
1.0
Sheet
1
50
of
52

REVISION: 0.2
Item
Date
Page
Action
Component
Request
---------------------------------------------------------------------------------------------------------------------------------------------01)
11/22
36
Delete
RA22
For audio codec
02)
11/22
36
Add
Add a reserve 0ohm resistor RA25
For EMI request
03)
11/22
27
Change
Change D15 P/N from SCS00002G00 to SCS00000Z00
For material shortage
04)
11/22
27,29,34,35 Change
Change L10,L11,L62,L71,L72,L8,L9,LR7,LR8,LR9 P/N
from SM070003Y00 to SM070003K00
For material shortage
05)
11/22
05
Change
Change R184 from SD013470080 to SD028470080
The same as CRB board
06)
11/26
26
Change
Change RT14 config. from @ to LVDS@
For BKOFF circuit
07)
11/26
09
Change
Change RH19 config. to IEDP@
For BKOFF circuit
08)
11/26
09
Connect
Connect EC_ENBKL_R_CPU to AND GATE U50.1
For BKOFF circuit
09)
11/26
27
Change
Change U50.1 from EC_ENBKL_R to EC_ENBKL_R_CPU
For BKOFF circuit
10)
11/26
27
Change
Change U50 and R433 config. from IEDP@ to always mount For BKOFF circuit
11)
11/26
27
Change
Change D15 and R436 config. from LVDS@ to @
For BKOFF circuit
12)
11/26
36
Change
Change UB1.26 (EC GPIO12) from NC to TRANS_PRSNT
For BKOFF circuit
13)
11/26
36
Add
Add a pull high 10Kohm (RB23) to +3VL and a pull down
10Kohm (RB22) to GND on TRANS_PRSNT
For BKOFF circuit
14)
11/27
27
Change
Change D15 P/N from SCS00000Z00 to SCS0340L010
For BOM reduce
15)
11/27
29
Change
Change UD1.25, UD1.31, UD1.22, UD1.32 from
+1.8VS_RXVCC to +1.8VS_CRT
For DP to CRT translator
16)
11/27
29
Change
UD1.45 pull high from +3VS to +3VS_6513
17)
11/27
29
Add
Add test point on UD1.37
18)
11/27
29
Add
Add RPD2 symbol for 150ohm
19)
11/27
33
Change
Change LAN/USB Small board Connector pin
(JLAN.3 to JLAN.6) define
For LAN/USB Small board
20)
11/27
35
Change
Change UA1 all analog outpout net name to PR_L/PR_R
Unify net name
21)
11/27
35
Change
Change CA15 0.1u cap from 16V4Z to 10V7K
Don't need to use 16V4Z
22)
11/27
35
Change
Add net name Line1-L_C & Line1-L_R on UA1 pin 21.22
For trace length table
23)
11/27
35
Detete
Delete ALC233 co-lay component RA6, RA30, UA1
Change to ALC233VB Only
24)
11/27
35
Change
Swap RA21 & RA22 BOM structure
Balance caps alignment
25)
11/28
29
Change
Change test point T2 to a pull high 10Kohm (RD13)
to +3VS_6513
26)
11/28
27
Add
Add a reserved ESD diode (D92) for JTOUCH
For ESD requeset
27)
11/28
07
Change
Change Dual ESD diode (D13) to two single diodes
(D16,D17)
For RTC circuit
28)
11/28
07
Change
Change R437.1 connecting from +RTCBATT to +RTCVCC
For RTC circuit
29)
11/29
07
Change
Change R437 from 0ohm to 1kohm
For RTC circuit
30)
11/29
33,37
Change
Change L56,L57 from SM070001U00 to SM070003K00
For EMI request
31)
11/29
33,37
Change
Change L56,L57 from @EMI@ to EMI@
For EMI request
32)
11/29
33,37
Change
Change R4,R5,R6,R7 from EMI@ to @EMI@
For EMI request
33)
11/29
34
Change
Change CR2,CR3,CR5 from 22U_0603 to 22U_0805
For droop issue
34)
11/29
35
Change
Change CA15 from SE076104K80 to SE102104K00
For BOM change
35)
11/29
07
Change
Change R277.2 net name from N113579902 to +RTCBATT_R
For RTC circuit
36)
12/01
33,37
Change
Swap L56,L57 pin define
For layout request
37)
12/01
27
Add
Add R9,R11 on EMI camera choke
For EMI request
38)
12/01
27
Change
Change L62 from CAM_EMI@ to @CAM_EMI@
For EMI request
2010/09/03
Issued Date
Compal Secret Data
2012/12/31
Deciphered Date
Title
Size
Date:
HW-PIR-2
Document Number
Rev
1.0
Sheet
1
51
of
52

REVISION: 0.3
Item
Date
Page
Action
Component
Request
---------------------------------------------------------------------------------------------------------------------------------------------01)
12/12
09
Change
Change RH19 BOM structure from IEDP@ to always mount
For LVDS & eDP cost down plan
02)
12/12
26
Change
Change RT14 BOM structure from LVDS@ to @
03)
12/12
27
Delete
Delete U50,R433
04)
12/12
27
Change
Change D15,R436 BOM structure from @ to always mount
05)
12/12
36
Change
Change RB22 BOM structure from @ to IEDP@
06)
12/12
36
Change
Change RB23 BOM structure from @ to LVDS@
07)
12/12
07
Change
Change R277,D17 BOM structure from always mount to @
For RTC circuit
08)
12/12
07
Change
Change R437 BOM structure from @ to always mount
For RTC circuit
09)
12/30
11
Add
Add two reserved resistors R167,R168
For no use USB over current
10)
12/30
11
Change
Change UC1.AL3 connect to USB_OC#0_R
11)
12/30
11
Change
Change UC1.AH2 connect to USB_OC#2_R
12)
01/03
34
Add
Add a reserved capacitor CR7 on +USB_VCCB
For USB
13)
01/03
13
Add
Add a jumper PJ2 between +3VALW to +3VALW_PCH
For +3VALW to +3VALW_PCH
14)
01/06
38
Add
Add C549 and C550
For ESD's request
15)
01/06
37
Change
Change JLED footprint from E-T_6916K-Q06N-00L_6P
to ACES_51524-0060N-001_6P
For DFX's request
16)
01/06
37
Change
Change JPWR footprint from E-T_6916K-Q04N-03R_4P
to ACES_50504-0040N-001_4P
For DFX's request
17)
01/06
35
Change
Change UA1 Compal PN from SA00007BF00 to SA00007BF10
For audio codec
18)
01/07
13
Change
Change CH111,CH112,CH113,Q10,RH3 BOM structure
from always mount to @
For +3VALW to +3VALW_PCH
19)
01/14
27
Change
Change D29 BOM structure from @ESD@ to ESD@
For ESD's request

REVISION: 1.0
Item
Date
Page
Action
Component
Request
---------------------------------------------------------------------------------------------------------------------------------------------01)
01/21
07,09,27
Change
Change D90,D91,D15,D16,D21,D17 from SCS0340L010
to SCS00003500.
For X code
02)
01/21
31
Change
Change JHDD footprint from SANTA_191503-1_22P-T
to LCN_ASF98-2231S10-0002_22P.
For DFX's request
03)
01/21
37
Change/Add
Change CPU R1 BOM config and add R3 BOM config
For CPU BOM config
04)
01/29
33,36
Add
Add a GPIO pin LAN_OFF# for UB1.25 and connected to
JLAN.3
For Disable/Enable LAN chip
05)
01/29
36
Add
Add a GPIO pin PCH_RTCRST#_R for UB1.18 and connected
to a 0ohm resistor (RB29) and connected to PCH_RTCRST#. For RTC reset
06)
01/29
34
Add
Add a reserved capacitor 100uF (CR14) for +USB_VCCB.
For USB droop
07)
02/05
07,09,27,35 Change
Change 0ohm resistor (RH19,R436,R32,R431,R432,RA11,
RA1,RA2,RA10,R106) footprint to 0ohm short pad.
For 0ohm short pad
08)
02/05
35
Delete/Change
Delete RA13,RA18 and change UA1.18 to EXT_MIC
and UA1.20 to +3VALW
For audio codec
09)
02/05
37
Change
Change SW3 BOM config from mount to un-mount.
For Pre-MP phase
10)
02/06
26,27,29,35 Change
Change 0ohm resistor (RT1,RD1,LD2,RA20,RA21,R4280,
R4281,R11,R9) footprint to 0ohm short pad,
and BOM config to Rshort@.
For 0ohm short pad
11)
02/07
07,09,12,27 Change
,35,16,17,36
12)
13)
02/07
02/07
34
38
14)
02/10
37
Change 0ohm resistor (RH19,R65,R178,R235,R174,R211,

R212,R231,R436,LA1,LA3,RB34,RB1,R32,R431,R432,RA32,
RA33,RA34,RA35,RA11,RA1,RA2,RA10,R106) BOM config
to Rshort@.
Delete CR7.
Change 0ohm resistor (RM3,RM5) footprint to 0ohm
short pad, and BOM config to Rshort@.
Change screw hole size for H1,H2,H3.
Delete
Change
Change
2010/09/03
Issued Date
For 0ohm short pad

For USB droop
A
For 0ohm short pad

For ME's request
Compal Secret Data
2012/12/31
Deciphered Date
Title
Size
Date:
HW-PIR-3
Document Number
Rev
1.0
Sheet
1
52
of
52

Toshiba Satellite C55 Compal LA-B301P r1.0

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Toshiba Satellite C55 Compal LA-B301P r1.0

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A

AMD GPU Jet Pro/Topaz XT S3 (Single Rank)

LA-B301P REV 1.0 Schematic

Intel Processor (Haswell ULT/Broadwell U)

Compal Electronics, Inc.

Compal Secret Data

Monday, February 10, 2014

Intel Haswell ULT/Broadwell U

PCI-Express 4X Gen3 8GT/s

1.35V DDR3L 1333/1600 MT/s

Memory BUS(DDR3L) 204pin DDR3-SO-DIMM X2

Lynx Point - LP/

SATA Gen3 port 0

SATA Gen3 port 1

DC/DC Interface CKT.

Power Circuit DC/DC

Power On/Off CKT.

Compal Electronics, Inc.

Compal Secret Data

Ipeak=8A, Imax=5.6A, Iocp=9A

DESIGN CURRENT 10.81A

DESIGN CURRENT 4.98A

DESIGN CURRENT 1.1A

DESIGN CURRENT 0.025A

DESIGN CURRENT 1.555A

DESIGN CURRENT 253mA

DESIGN CURRENT 0.37A

DESIGN CURRENT 0.468A

DESIGN CURRENT 0.35A

Ipeak=3A, Imax=2.1A, Iocp=4A

DESIGN CURRENT 1.93A

Ipeak=10A, Imax=7A, Iocp=12A

DESIGN CURRENT 10.2A

Ipeak=5A, Imax=3.5A, Iocp=6A

Ipeak=1A, Imax=0.7A, Iocp=2.5A

DESIGN CURRENT 1.5A

DESIGN CURRENT 5.66A

Ipeak=5A, Imax=3.5A, Iocp=6A

DESIGN CURRENT 24A

Compal Secret Data

Compal Electronics, Inc.

Monday, February 10, 2014

BTO Option Table

S5 S4/ Battery only

S5 S4/AC & Battery

CPU (R1 PN)

CPU (R3 PN)

PCH SM Bus Address

Zero Power ODD

Non-Zero Power ODD XDP

0 ohm short pad

SLP_S3# SLP_S4# SLP_S5#

Compal Electronics, Inc.

Compal Secret Data

Monday, February 10, 2014

2 10K_0402_5% H_CPUPW RGD

DDR3 Compensation Signals

Trace width=20 mils,Spacing=25mil,Max length=100mils

PU/PD for JTAG signals

Compal Electronics, Inc.

Compal Secret Data

HSW MCP(1/11) DDI,MSIC,XDP

Monday, February 10, 2014

Compal Electronics, Inc.