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# (3349) - 2004

Operational Amplifiers

Ching-Yuan Yang
National Chung-Hsing University
Department of Electrical Engineering

Overview
B. Razavi Chapter 9.
z Introduction
Operational amplifiers (op amps) are an integral part of many analog and
mixed-signal systems. Op amps with vastly different levels of complexity are
used to realize functions ranging from dc bias generation to high-speed
amplification or filtering.
This lecture deals with the analysis and design of CMOS op amps.
Following a review of performance parameters, we describe simple op amps
such as telescopic and folded cascode topologies. Next, we study two-stage
and gain-boosting configurations and the problem of common-mode
feedback. Finally, we introduce the concept of slew rate and analyze the
effect of supply rejection and noise in op amps.

Analog-Circuit Design

9-1

## Ching-Yuan Yang / EE, NCHU

Performance parameters
n Gain

## Example: the circuit is designed for a nominal of 10, i.e.,

1 + R1/R2 =10.
The close-loop gain:

Vout
=
Vin 1 +

R + R2
A1
A1
= 1

R1 + R 2
R2
R
2
+ A1
A1
R2
R1 + R2

## If A1 >> (R1 + R2)/R2, then

Vout
R R + R2 1

1 + 1 1 1
Vin R2
R2 A1

The term (R1 + R2)/(R2 A1) = (1 + R1/R2)/ A1 represents the relative error.
To achieve a gain error less than 1%, we must have A1 > 1000.

Discussion
Simple CS stage an open-loop implementation:

Vout
= gm R D = 10
Vin
However, it is difficult to guarantee an error less than 1%.
The variations in the mobility and gate oxide thickness of the transistor and
the value of the resistor typically yield an error greater than 20%.
Analog-Circuit Design

9-2

## Performance parameters (contd)

o Small-signal bandwidth

dB

unity-gain

## p Large-signal bandwidth slew rate

Analog-Circuit Design

9-3

## Performance parameters (contd)

q Output swing Most systems employing op
amps require large voltage swings to
accommodate a wide range of signal amplitudes.

## r Linearity Open-loop op amps suffer from

substantial nonlinearity. For example, the input
pair M1 M2 exhibits a nonilinear relationship
between its differential drain current and input
voltage. In many feedback circuits, the linearity
requirement, rather than the gain error
requirement, governs the choice of the open-loop
gain.

## s Noise and offset The input noise and offset of

op amps determine the minimum signal level that
can be processed with reasonable quality.

## t Supply rejection Op amps are often employed

in mixed-signal systems and sometimes
connected to noise digital supply lines. Thus, the
performance of op amps in the presence of supply
noise is quite important. For this reason, fully
differential topologies are preferred.
Analog-Circuit Design

9-4

## Ching-Yuan Yang / EE, NCHU

One-stage op amps
Simple op amp topologies

## Differential input & differential output

For small-signal:
Low frequency gain = gmN (roN || roP). In general, this value hardly
exceeds 20 in submicron devices with typical current levels.

## The circuits suffer from noise contributions of M1-M4. In all op amp

topologies, at least four devices contribute to the input noise: two
input transistors and two load transistors.

Analog-Circuit Design

9-5

## Ching-Yuan Yang / EE, NCHU

Unit-gain buffer
Input common-mode voltage range
Vin,min = VCSS + VGS1
Vin,max = VDD |VGS3| + VTH1
If each device has a threshold voltage of 0.7V and an overdrive
of 0.3V, then Vin,min = 1.3V, and Vin,max = 2.7V. Thus, the input
CM range equals 1.4V with a 3-V supply.

Output impedance
Rout =

Rout ,open
1 + Av ,open

roP roN
1

## The close-loop output impedance is relatively

independent of the open-loop output impedance.
Allowing us to design high-gain op amps by increasing
the open-loop output impedance while still achieving a
relatively low close-loop output impedance.

Analog-Circuit Design

9-6

VCSS

## Telescope cascode op amps

In order to achieve a high gain, the differential cascode topologies can be used.
Low-frequency gain Av = gmN [(gmN roN2) || (gmP roP2)], but at the cost of output
swing and adding poles.

Analog-Circuit Design

9-7

## Ching-Yuan Yang / EE, NCHU

(a): The circuit providing a single-ended output suffers from a mirror pole at
node X, creating stability issues.
(b): Fully differential topology, the output swing is given by
2[VDD (VOD1 + VOD3 + VCSS + |VOD5| + |VOD7|)]
where VODj denotes the overdrive voltage of Mj.
Another drawback of telescopic cascodes is the difficult in shorting their inputs
and outputs, e.g., to implement a unity-gain buffer.

Analog-Circuit Design

9-8

## Telescope cascode op amps (contd)

Cascode op amp with input and output shorted
unit gain feedback topology
Output swing: M2 and M4 in saturation:

Vout V X + VTH 2
Vb VTH 4 Vout Vb VGS 4 + VTH 2

Vout Vb VTH 4
the voltage range Vmax Vmin = VTH4 (VGS4 VTH2)
Since the op amp attempts to force Vout to be equal to
Vin, for Vin < Vb VTH4, we have Vout Vin and M4 is in
triode region while others are saturated. Under this
condition, the open-loop gain of the op amp is reduced.
As Vin and Vout hence exceed Vb VTH4, M4 enters
saturation and the open-loop gain reaches a maximum.
For Vb VTH4 < Vin < Vb (VGS4 VTH2), both M2 and
M4 are saturated and for Vin > Vb (VGS4 VTH2), M2
and M1 enter the triode region, degrading the gain. Thus,
a cascode op amp is rarely used as a unit-gain buffer.
Analog-Circuit Design

9-9

## Design of fully differential telescope op amp

Specifications:
VDD = 3V, differential output swing = 3V,
power dissipation = 10mW, voltage gain = 2000.
Assume nCox = 60 A/V2, pCox = 30 A/V2, n = 0.1V1, p = 0.2V1 (for an
effective channel length of 0.5 m), = 0, VTHN = |VTHP| = 0.7V.
z
z

Power budget:
IM9 = 3mA, IMb1 + IMb2 = 330A
Output swing:
Node X(Y) swing = 1.5V, M3-M6 in saturation.
For M9,
|VOD7| + |VOD5| + VOD3 + VOD1 + VOD9 = 1.5V
Since M9 carrying largest current,
VOD9 0.5V is chosen. |VOD5| = |VOD7| 0.3V,
VOD1 = VOD3 0.2V.
W/L
By ID = (1/2)Cox(W/L)(VGS VTH )2, we have
(W/L)14 = 1250, (W/L)58 = 1111, (W/L)9 = 400.

Analog-Circuit Design

9-10

## Ching-Yuan Yang / EE, NCHU

z Gain:
Av gm1[(gm3ro3ro1)|| (gm5ro5ro7)]. In order to Increase the gain,
we recognize g mro = 2C ox (W / L )I D /(I D ) WL / I D
where 1/L. We can therefore increase the width or length.
Choose (W/L)58 = 1111m/1m,
then Av 4000.
z CM level & bias:
Min. allowable input CM level
= VGS1 + VOD9 = 1.4V.
Vb1,
Vb2,

min
max

## = VGS3 + VOD1 + VOD9 = 1.6V.

= VDD (|VGS5 |+ |VOD7|) = 1.7V.

Analog-Circuit Design

9-11

## Folded cascode op amps

In order to alleviate the drawbacks
of telescopic cascode op amps. The
primary advantage of the folded
structure lies in the choice of the
voltage levels because it does not
stack the cascode transistor on the
top of the input device.

Analog-Circuit Design

9-12

## Two important differences between the two circuits:

In Fig.(a), one bias current, ISS, provides the drain current of both the input
transistors and the cascode devices.
In Fig.(b), the input pair requires an additional bias current, ISS1 = ISS/2 + ID3.

## In Fig.(a), the input CM level cannot exceed Vb1 VGS3 + VTH1,whereas in

Fig.(b), it cannot be less than Vb1 VGS3 + |VTH1|.

In Fig.(b), it is possible to tie the n-well of M1 and M2 to their common source point.

Analog-Circuit Design

9-13

## Folded cascode op amps (contd)

Folded cascode op amp with cascode PMOS loads

Max. output voltage swing: With proper choice of Vb1 and Vb2,
Peak-peak swing = [VDD (|VOD7| + |VOD9|)] (VOD3 + VOD5 ) for one side.
The swing is lager by the overdrive of the tail current source in the telescopic
cascode.M5 and M6 may require a high overdrive voltage if their capacitance
contribution to nodes X and Y is to be minimized.
Analog-Circuit Design

9-14

## Folded cascode op amps (contd)

Small-signal voltage gain

Half circuit

|Av| = Gm Rout

## Equivalent circuit with

output shorted to ground

## Since (gm3+gmb3)1||ro3 << ro1||ro5 ,

Iout ID1. That is Gm gm1.

output open

## ROP (gm7 + gmb7) ro7 ro9

Rout ROP || [(gm3+gmb3)ro3(ro1||ro5)]

## Thus, |Av| gm1{[(gm3+gmb3)ro3(ro1||ro5)] || [(gm7 + gmb7) ro7 ro9]}

The gain is usually two or three times lower than of a comparable telescopic cascode.
Analog-Circuit Design

9-15

## Folded cascode op amps (contd)

Effect of device capacitance on the nondominant pole in telescopic and folded cascode
op amps

## Ctot = CGS3 + CSB3 + CDB1 + CGD1 + CGD5 + CDB5

The pole at the folding point, i.e., the sources of M3 and M4, is quite closer to the
origin than that associated with the source of cascode devices in a telescopic
topology.

Analog-Circuit Design

9-16

## A high-gain folded cascode op amp

The circuit provides a higher gain because of the greater mobility of NMOS
devices, but at the cost of lowering the pole at the folding point,
p,X (gm3 + gmb3) / Ctot,X.
Analog-Circuit Design

9-17

## Telescopic- & folded-cascode op amps: Discussion

z

The overall voltage swing of a folded-cascode op amp is only slightly higher than that of a
telescopic configuration. This advantage comes at the cost of higher power dissipation,
lower voltage gain, lower pole frequencies, and higher noise.

Folded-cascode op amps are used quite widely, even more than telescopic topologies,
because the input and outputs can be shorted together and the choice of the input
common-mode level is easier.
In a telescopic op amp, three voltages must be defined carefully: the input CM level
and the gate bias voltages of the PMOS and NMOS cascode transistors, whereas in
folded-cascode configurations only the latter two are critical.
In folded-cascode op amps, the capability of handling input CM levels are close to
one of the supply rails.

Analog-Circuit Design

9-18

## Design of folded-cascode op amp

Specifications:
VDD = 3V, differential output swing = 3V,
power dissipation = 10mW, voltage gain = 2000.
Assume nCox = 60 A/V2, pCox = 30 A/V2, n = 0.1V1, p = 0.2V1 (for an
effective channel length of 0.5 m), = 0, VTHN = |VTHP| = 0.7V.

Analog-Circuit Design

9-19

## Ching-Yuan Yang / EE, NCHU

10

Power budget: IM11 = 1.5mA, IM9 + IM10 = 1.5mA, IMb1 + IMb2 + IMb3 = 330A.

## Output swing: one side o/p swing = 1.5V, M3-M10 in saturation.

Choose |VOD5,6| 0.5V, |VOD3,4| 0.4V, VOD7,8 = VOD9,10 0.3V.

## W/LBy ID = (1/2)Cox(W/L)(VGS VTH )2, we have

(W/L)5,6 = 400, (W/L)3,4 = 313, (W/L)710 = 555.

## O/p CM level: CMmin = 0.6V, CMmax = 2.1V, thus CMopt = 1.35V.

Analog-Circuit Design

9-20

## Determine (W/L)1,2: min. input CM level = VGS1 + VOD11.

If input and output are shorted, then VGS2 + VOD11 = 1.35V,
and VGS1 = 0.95V VOD1,2 = 0.25V (W/L)1,2 = 400.
The maximum dimensions of M1,2 are determined by the tolerable input
capacitance at nodes X and Y.

## Gain: gm = 2ID/(VGS VTH), we have

gm1,2 = 0.006 A/V, gm3,4 = 0.0038 A/V, gm7,8 = 0.05 A/V.
For L = x m, find ro.
Note |Av| gm1{[(gm3 + gmb3)ro3(ro1 || ro5)] || [(gm7 + gmb7) ro7ro9]}

Analog-Circuit Design

9-21

11

## Cascode op amps with single-ended output

Fig(a): VX = VDD |VGS5| |VGS7|,
limiting the maximum value of
Vout to VDD |VGS5| |VGS7|
|VTH6| and wasting one PMOS
threshold voltage in the swing.
Fig(b): To solve above issue, M7 and
M8 are biased at the edge of
the triode region.

## (1) it provides only half the output voltage swing.

(2) it contains a mirror pole at node X, thus limiting the speed
of feedback systems employing such an amplifier.

## z It is preferable to use the differential topology, although it requires a feedback

loop to define the output CM level.
Analog-Circuit Design

9-22

9-23

## Ching-Yuan Yang / EE, NCHU

Triple-cascode op amp

## The triple cascode topology provides

a gain on the order of (gmro)3/2 but
further limits the output swings. With
six overdrive voltages subtracted from
VDD in this circuit, it is difficult to
operate the amplifier from a supply
voltage or lower while obtaining
reasonable output swings.

Analog-Circuit Design

12

Two-stage op amps

## z The gain of one-stage topologies is limited to the input pair transconductance

and the output impedance.
z Two-stage op amps consist of first stage providing a high gain and the second
providing large swing. The first stage incorporates various amplifier topologies,
but the second stage is typically configured as a simple common- source
stage to allow maximum output swings.
z Can we cascade more than two stages to achieve a higher gain?
Each gain stage introduces at least one pole in the open-loop transfer function,
making it difficult to guarantee stability in a feedback system using such an op
amp. For this reason, op amps having more than two stages are rarely used.
Analog-Circuit Design

9-24

Gain:

## Av,1st stage = gm1,2(ro1,2 || ro3,4)

Av,2nd stage = gm5,6(ro5,6 || ro7,8)
Overall gain Av = Av,1st

stage

Av,2nd

stage

## Output swing = VDD |VOD5,6| VOD7,8

Analog-Circuit Design

9-25

13

## Two-stage op amp employing cascoding

To obtain a higher, the first stage incorporate cascode devices. The overall voltage gain is
Av {gm1,2[(gm3,4 + gmb3,4)ro3,4ro1,2] || (gm5,6 + gmb5,6)ro5,6ro7,8]} [gm9,10(ro9,10 || ro11,12)]

Analog-Circuit Design

9-26

## Note that if the gate of M1 is shorted to Vout to form a unity-gain buffer,

then the minimum allowable output level is equal to VGS1 + VISS, severely
limit the output swing.

Analog-Circuit Design

9-27

## Ching-Yuan Yang / EE, NCHU

14

Gain boosting
Increasing the output impedance by feedback

Rout = gm2ro2ro1
M1 operates as a degeneration resistor.

## The voltage variations at the drain of M2 effect VX to a

lesser extent because A1 regulates this voltage. (VX = Vb)
With smaller variations at X, the current through ro1 and
hence the output current remains more constant,
yielding a higher output impedance.
Rout A1gm2ro2ro1,
Rout is booted substantially without stacking more
cascode devices on top of M2.
Analog-Circuit Design

9-28

Gain:

## Min. output swing:

Since VX = VGS3, the min.value of
Vout is VOD2 + VGS3. The auxiliary
amplifier limits the output swing.
Note: Min. output swing is VOD2 +
VOD1 in a simple cascode.
regulated cascode

Analog-Circuit Design

9-29

15

## z The minimum level at the drain of M3 is

equal to VOD3 + VGS5 + VISS2.
z The voltage swing limitation results the fact
that the gain-boosting amplifier incorporates
an NMOS differential pair.

Analog-Circuit Design

9-30

## Folded-cascode circuit used as auxiliary amplifier

Half circuit

z If nodes X and Y are sensed by a PMOS pair, the minimum value of VX and
VY is not dictated by the gain-boosting amplifier.
z The minimum allowable level of VX and VY is given by VOD1,2 + VISS1.
z Output impedance: Since

VP
= gm 5Rout1
VX

## where Rout1 [gm7ro7(ro9||ro5)] || (gm11ro11ro13), Rout gm3ro3ro1gm5Rout1.

Analog-Circuit Design

9-31

16

## Gain boosting applied to both signal path and load devices

Regulated cascodes can also be utilized in the load current sources of a
cascode op amp.

Analog-Circuit Design

9-32

## Comparison of performance of various op amp topologies

Gain

Output
Swing

Speed

Power
Dissipation

Noise

Low

Low

Telescopic

Medium

Medium

Highest

Folded-Cascode

Medium

Medium

High

Medium

Low

Medium

Two-stage

High

Highest

Gain-Boosted

High

Medium

Analog-Circuit Design

9-33

Medium

High

Medium
Low
Medium

17

## Common-mode feedback (CMFB)

z Full differential circuits have many advantages over their single-ended
counterparts such as greater output swings, avoiding mirror poles, higher
closed-loop speed. However, high-gain differential circuits require commonmode feedback.
z Simple differential pair

## Input & output common-mode

level is equal to VDD ISS RD /2

Analog-Circuit Design

9-34

## z What is the common-mode level at nodes X and Y?

Since each of the input transistors carries a current ISS /2, the CM level depends on
how close ID3 and ID4 are to this value.
z Effect of current mismatches: Mismatches in the PMOS and NMOS current mirrors
defining ISS and ID3,4 create a finite error between ID3,4 and ISS /2.
If ID3,4 > ISS /2, then both M3 and M4 must enter the triode region so that their drain
currents fall to ISS /2. Conversely, If ID3,4 < ISS /2, then both VX and VY must drop so
that M5 enters the triode region, thereby producing only 2ID3,4.
Analog-Circuit Design

9-35

18

## Simplified model of high-gain amplifier

In high-gain amplifiers, we wish a p-type current source to balance an n-type current
source.

V = (I P I N )(RP RN )

Since the current error depends on mismatches and RP||RN is quite high, the voltage
error may be large, thus driving the p-type or n-type current source into triode region.
As a general rule, if the output CM level cannot be determined by visual inspection
and requires calculations based on device properties, then it is poorly defined.
In high-gain amplifiers, the output CM level is quite sensitive to device properties and
mismatches and it cannot be stabilized by means of differential feedback. Thus a
CMFB network must be added to sense the CM level of the two outputs and
accordingly adjust one of the bias currents in the amplifier.
Analog-Circuit Design

9-36

## Conceptual topology for CMFB

In high-gain amplifiers, the output CM level is quite sensitive to device properties and
mismatches and it cannot be stabilized by means of differential feedback. Thus a CMFB
network must be added to sense the CM level of the two outputs and accordingly adjust
one of the bias currents in the amplifier.

Analog-Circuit Design

9-37

19

## z Output CM level: Vout,CM = (Vout1 + Vout2)/2

z Resistive divider level: Vout,CM = (R1Vout2 + R2Vout1)/(R1 + R2)
= (Vout1 + Vout2)/2, if R1 = R2.
z R1 and R2 must be much larger than the output impedance of the op amp
so as to avoid lowering the open-loop gain.
Analog-Circuit Design

9-38

## CMFB using source followers

Current starvation of source followers for large swings

## z This technique produces a CM level

that is lower than the output CM
level by VGS7,8, but this shift can be
taken into account in the
comparison operation.
z R1 and R2 or I1 and I2 must be large
enough to ensure that M7 or M8 is
not starved when a large differential
swing appears at the output.
Analog-Circuit Design

## must sink both IX (Vout2 Vout1)/(R1 + R2)

and ID7. Consequently, if (R1 + R2) or I1 is
not sufficiently large, ID7 drops to zero
and Vout,CM no longer represents the true
output CM level.

## z This sensing method limits the differential

output swings. The swing at each output is
reduced by approximately VTH, a significant
value in low-voltage design.
9-39

20

## CMFB using MOSFET operating in deep triode region

z Identical transistors M7 and M8 operate in deep triode region,
RP = Ron 7 Ron 8
1
1
W
W
nCox (Vout1 VTH ) nCox (Vout 2 VTH )
L
L
1
=
W
nCox (Vout1 + Vout 2 2VTH )
L

## RP is a function of Vout1 + Vout2 but independent of

Vout2 Vout1.
The use of M7 and M8 limits the output voltage swings, Vout,min = VTH7,8, which is
relatively close to two overdrive voltages, but the difficulty arises from the assumption
above that both M7 and M8 operate in deep triode region. If Vout1drops from the
equilibrium CM level to one threshold voltage above ground and Vout2 rises by the same
amount, then M7 enters the saturation region, thus exhibiting a variation in its onresistance that is not counterbalanced by that of M8.
Analog-Circuit Design

9-40

## Sensing and controlling output CM level

We employ a simple amplifier to detect the difference between Vout,CM and a reference
voltage, VREF, applying the result to the NMOS current sources with negative feedback.
If the loop gain is large, the feedback network forces the CM level of Vout1 and Vout2 to
approach VREF.

Also, the feedback may control only a fraction of the current to allow optimization of the
settling behavior. For example, each M3 and M4 can be decomposed into two parallel
devices, one biased at a constant current and the other driven by the error amplifier.

Analog-Circuit Design

9-41

21

## z In a folded-cascode op amp, the CM feedback may control the tail current

of the input differential pair. This method increases the tail current if Vout1
and Vout2 rise, lowering the drain currents of M5M6 and restoring the output
CM level.

Analog-Circuit Design

9-42

## CMFB using triode devices

z The output CM level sets Ron7 || Ron8 such that
ID5 and ID6 exactly balance ID9 and ID10, respectively.
z Assuming ID9 = ID10 = ID,
RP = Ron7|| Ron8 = (Vb VGS5)/(2ID ), and also

RP =

1
W
nCox (Vout 2 + Vout1 2VTH )
L 7,8

where VGS 5 =

2I D

nCox (W / L )5

+ VTH 5

z Drawbacks:
1.The value of the output CM level is a function of device
parameters.
2.The voltage drop across Ron7||Ron8 limits the output voltage swing.
3.To minimize this drop, M7 and M8 are usually quite wide devices, introducing
substantial capacitance at the output.
Analog-Circuit Design

9-43

22

## Alternative method of controlling output CM level

z If Vb is higher than expected, the tail current of M1 and
M2 increases and the output CM level falls. Since the
feedback through M7 and M8 attempts to correct this
error, the overall change in Vout,CM depends on the loop
gain in the CMFB network.
z Determine the sensitivity dVout,CM/dVb:
M7,8 in triode region: gm7,8 = nCox(W/L)7,8VDS7,8
Feedback factor:

V2
V1

Thus,

= ( g m 7 + g m8 )(Ron 7 Ron8 ) =
I 2 =0

dVout ,CM
dVb

VDS 7,8
VGS 7 ,8 VTH

VDS 7,8

## Since VGS7,8 (i.e., the output CM level) is typically

in the vicinity of VDD/2, the above equation
suggests that VDS7,8 must be maximized.
Analog-Circuit Design

9-44

## Modification of CMFB for more accurate definition of output MC level

z The idea is to define Vb by a current mirror arrangement such that ID9 tracks I1 and IREF.
z Suppose (W/L)15 = (W/L)9 and (W/L)16 = (W/L)7 + (W/L)8.
Thus, ID9 = I1 only if Vout,CM = VREF.
The circuit produces an output CM level equal to a reference but it requires no resistors in
sensing Vout,CM.
z In practice, since VDS15 VDS9, channel-length modulation results in a finite error.
Analog-Circuit Design

9-45

23

## Modification to suppress error due to channel-length modulation

z Transistors M17 and M18 reproduce at the drain of M15 a voltage equal to the
source voltage M1 and M2, ensuring that VDS15 = VDS9.

Analog-Circuit Design

9-46

z

## Differential pair using diode-connected loads

The input CM level, VDD VGS3,4, is relatively
well-defined, but the voltage gain is quite low.

Resistive CMFB
To increase the differential gain, the PMOS
device must operate as current sources for
differential signals.
For differential change at Vout1 and Vout2, node
P is a virtual ground and the gain can be
expresses as
Av = gm1,2(ro1,2||ro3,4||RF)
For CM levels, M3 and M4 operate as diodeconnected devices.

Analog-Circuit Design

9-47

24

## Input range limitations

z
z

Limitation: While the differential input swings are usually much smaller, the input
common-mode level may need to vary over a wide range in some applications.
Unity-gain buffer

The voltage swings are limited by the input differential pair rather than the
output cascode branch. Specifically, Vin,min Vout,min = VGS1,2 + VISS, approximately
one threshold voltage higher than the allowable minimum provided by M5-M8.
If Vin < Vin,min: The MOS transistor operating as ISS enters the triode region,
decreasing the bias current of the differential pair and hence lowering the
transconductance.
Analog-Circuit Design

9-48

## Extension of input CM range

z A simple approach to extending the
input CM range is to incorporate
both NMOS and PMOS differential
pairs such that when one is dead,
the other is alive. This idea is to
combine two folded-cascode op amps
with NMOS and PMOS input
differential pairs.
z As the input CM level approaches the
ground potential, the NMOS pairs
transconductance drops, eventually
falling to zero. Nonetheless, the PMOS
pair remains active, allowing normal
operation. Conversely, if the input CM
level approaches VDD, M1P and M2P
begin to turn off but M1 and M2 function
properly.
Analog-Circuit Design

9-49

## Variation of equivalent transconductance with

the input CM level.

25

Slew rate
z

step

## dVout/dt: Since Vout = V0[1 exp(t/)], where = RC, we have

dVout V0
t
= exp

dt

dVout/dt V0; if we apply a larger input step, the output rises more rapidly.

Analog-Circuit Design

9-50

z

## Response of a linear op amp to step response

Assume op amp is linear,

1
Vout
R2
A Vout
=
+ Vout C L s
Vin Vout
R
R
R
R
+
1
2
1 + R2

out
Assume R1 + R2 >> Rout, we have

Vout
A
(s )
Vin

R2
Rout CL
1+
1 + A
s
R1 + R2 1 + AR2 (R1 + R2 )

## The step response is given by

Vout

t
1 exp
u (t )
= V0
R2
C L Rout

1+ A

R1 + R2
1 + AR2 (R1 + R2 )
A

## indicating that the slope is proportional to the final value.

This type of response is called linear settling.
Analog-Circuit Design

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26

z

## Slewing in an op amp circuit

Vout = V0

t
1 exp
u (t )
R2
C L Rout

1+ A
R1 + R2
1 + AR2 (R1 + R2 )
A

..(A)

The response to sufficiently small inputs follows the exponential of Eq.(A), but
with large input steps, the output displays a linear ramp having a constant slope.
Under this condition, we say the op amp experiences slewing and call the slop of
the ramp the slew rate.
Analog-Circuit Design

9-52

## z Assuming that R1 + R2 is quite large.

If Vin experiences a change of V, the total small-signal current provided
by the op amp equals gmV. This current begins to change CL, but as Vout
rises, so does VX, reducing the difference between VG1 and VG2 and hence
the output current of the op amp.
Analog-Circuit Design

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27

## Slewing during large signal transition

z Slewing during low-to-high transition
M1 absorbs all of ISS and M2 turns off.
So long as M2 remains off, the feedback
loop is broken and the current charging
CL is constant and independent of the
input level.
z Slewing during high-to-low transition

Analog-Circuit Design

9-54

## z While the small-signal bandwidth of a circuit may suggest a fast time-domain

response, the large-signal speed may be limited by the slew rate simply
because the current available to charge and discharge the dominant
capacitor in the circuit is small.
z Since the input/output relationship during slewing is nonlinear, the output of
a skewing amplifier exhibits substantial distortion.
For example, if a circuit is to amplify a sinusoid V0sin0t (in the steady
state), then its slew rate must exceed V00.

Analog-Circuit Design

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28

## Slewing in telescopic op amp

Vout1 and Vout2 appear as a ramps with slopes equal to ISS /(2CL), and
consequently Vout1 Vout2 exhibits a slew rate equal to ISS /CL.

Analog-Circuit Design

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z

## If IP ISS, the slew rate is equal to ISS /CL, independent of IP.

Analog-Circuit Design

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29

## Slewing in folded-cascode op amp (contd)

z

If ISS > IP, then during slewing M3 turns off and VX falls to a low level such that M1
and the tail current source enters the triode region. Thus, for the circuit to return to
equilibrium after M2 turns on, VX must experience a large swing, slow down the
settling.

Analog-Circuit Design

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z

## The difference between ISS and IP flows through

M11, or M12, requiring only enough drop in VX or
VY to return on one of these transistors.

## M11 and M12 clamp the two nodes directly to VDD.

Since the equilibrium value VX and VY is usually
higher than VDD VTHN, M11 and M12 are off
during small signal-signal operation.

Analog-Circuit Design

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30

## Power supply rejection

z If the circuit in the figure is perfectly symmetric, Vout = VX.
Since the diode-connected device clamps node X to VDD
VX and hence Vout experience approximately the same
change as does VDD. In other words, the gain from VDD to
Vout is

Vout
1
VDD
z The power supply rejection ratio (PSRR) is defined as
the gain from the input to the output divided by the gain
from the supply to the output. At low frequencies:

PSRR =

Vout Vin
g mN (roP roN )
Vout VDD

Analog-Circuit Design

9-60

## Noise in a telescopic op amp

z

Guide: With many transistors in an op amp, it may seem difficult to intuitively identify
the dominant sources of noise. A simple rule for inspection is to change the gate
voltage of each transistor by a small amount and predict the effect at the output.

## The input-referred noise voltage per unit bandwidth is given by

At relatively low frequency, the
cascode devices contribute negligible
noise, leaving M1-M2 and M7-M8 as the
primary noise sources.

Analog-Circuit Design

2g
g2
KN
KP
2
Vn2 = 4kT 2
+2
m2 7,8
+ 2 m2 7 ,8 + 2

3 g m1, 2
WL
C
f
WL
C
f
(
)
(
)
g
3
g m1, 2
1, 2 ox
7 ,8 ox
m1, 2

## where KN and KP denote the 1/f noise coefficients of NMOS

and PMOS devices, respectively.

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31

## Noise in a fold-cascode op amp

z The noise of the cascode devices is negligible at low frequencies,
leaving M1-M2, M7-M8, and M9-M10 as potentially significant sources.
z Thermal noise:

Vn2,out

M 7 ,8 =

2
2
, (uncorrelated noise)
g m2 7 ,8 Rout
2 4kT

g
3
m 7 ,8

## where the factor 2 accounts for noise of M7 and M8, and

Rout denotes the open-loop output resistance of the op
amp.
Vn2,out

M 9,10 =

Vn2,out

M 1, 2

2
2

g m2 9,10 Rout
2 4kT

g
3
m
9
,
10

2
2

g m2 1, 2 Rout
= 2 4kT

g
3
m
1
,
2

and Av = gm1,2Rout.
Total input-referred thermal noise:

Vn2,in =

Vn2,out ,tot
Av2

2
2 g m 7,8 2 g m9,10
= 8kT
+
+
2
2

3
g
m1, 2 3 g m1, 2 3 g m1, 2

Analog-Circuit Design

9-62

z Flicker noise:

KP
1 2
2
g m 7 ,8 Rout
2

C
WL
f
(
)
7 ,8
ox

Vn2,out

M 7 ,8 =

Vn2,out

M 9 ,10 =

Vn2,out

M 1, 2 =

KN
1 2
2
2
g m9,10 Rout

KN
1 2
2
g m1, 2 Rout
2

## Cox (WL )1, 2 f

and Av = gm1,2Rout.
Total input-referred flicker noise:
Vn2,in =
=

Vn2,out ,tot
Av2
2K N
Cox f

2
1
g m2 9,10 2 K P
1
1 g m 7 ,8

+
2
(WL ) + (WL )

Cox f (WL )7 ,8 g m2 1, 2
1, 2
9 ,10 g m1, 2

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32

## Noise in a fold-cascode op amp (contd)

z The overall noise:
2
2 g m 7 ,8 2 g m 9,10
+
+
Vn2,in = 8kT
3
3 g m2 1, 2 3 g m2 1, 2
g
1
,
2
m
2
g m2 9,10 2 K P
2 K N 1
1
1 g m 7 ,8
+
+
+
2

## Cox f (WL )1, 2 (WL )9,10 g m1, 2 Cox f (WL )7 ,8 g m2 1, 2

z Discussion:
The noise contribution of the PMOS and NMOS
current sources increases in proportion to their
transconductance. This trend results in a trade-off
between output voltage swings and input-referred
noise: for a given current, as implied by
gm = 2ID /(VGS VTH), if the overdrive voltage of
the current sources is minimized to allow large
swings, then their transconductance is maximized.

Analog-Circuit Design

9-64

## Noise in a two-stage op amp

z Total voltage gain: Av = gm1(ro1||ro3) gm5(ro5||ro7).
z In the 2nd stage: The noise current of M5 and M7 flows through ro5||ro7.

Vn2

M 58

= 2 4kT

## z In the 1st stage:

2
( g m5 + g m7 )(ro5 ro7 )2 12 = 16kT 2 g m25 + g m 7 2
3
3 g m1 g m5 (ro1 ro3 )
Av
Vn2

M 14

= 2 4kT

## z Total input-referred thermal noise:

2 g m1 + g m3
3 g m2 1
Vn2,tot =

g + g m7
16kT 1
g m1 + g m3 + 2 m5
2
3 g m2 1
g m5 (ro1 ro3 )

## Note the noise resulting from the second

stage is usually negligible because it is
divided by the gain of the first stage when
referred to the main input.

Analog-Circuit Design

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33