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Operational Amplifiers

Ching-Yuan Yang

National Chung-Hsing University

Department of Electrical Engineering

Overview

z Reading

B. Razavi Chapter 9.

z Introduction

Operational amplifiers (op amps) are an integral part of many analog and

mixed-signal systems. Op amps with vastly different levels of complexity are

used to realize functions ranging from dc bias generation to high-speed

amplification or filtering.

This lecture deals with the analysis and design of CMOS op amps.

Following a review of performance parameters, we describe simple op amps

such as telescopic and folded cascode topologies. Next, we study two-stage

and gain-boosting configurations and the problem of common-mode

feedback. Finally, we introduce the concept of slew rate and analyze the

effect of supply rejection and noise in op amps.

Analog-Circuit Design

9-1

Performance parameters

n Gain

1 + R1/R2 =10.

The close-loop gain:

Vout

=

Vin 1 +

R + R2

A1

A1

= 1

R1 + R 2

R2

R

2

+ A1

A1

R2

R1 + R2

Vout

R R + R2 1

1 + 1 1 1

Vin R2

R2 A1

The term (R1 + R2)/(R2 A1) = (1 + R1/R2)/ A1 represents the relative error.

To achieve a gain error less than 1%, we must have A1 > 1000.

Discussion

Simple CS stage an open-loop implementation:

Vout

= gm R D = 10

Vin

However, it is difficult to guarantee an error less than 1%.

The variations in the mobility and gate oxide thickness of the transistor and

the value of the resistor typically yield an error greater than 20%.

Analog-Circuit Design

9-2

o Small-signal bandwidth

dB

unity-gain

Analog-Circuit Design

9-3

q Output swing Most systems employing op

amps require large voltage swings to

accommodate a wide range of signal amplitudes.

substantial nonlinearity. For example, the input

pair M1 M2 exhibits a nonilinear relationship

between its differential drain current and input

voltage. In many feedback circuits, the linearity

requirement, rather than the gain error

requirement, governs the choice of the open-loop

gain.

op amps determine the minimum signal level that

can be processed with reasonable quality.

in mixed-signal systems and sometimes

connected to noise digital supply lines. Thus, the

performance of op amps in the presence of supply

noise is quite important. For this reason, fully

differential topologies are preferred.

Analog-Circuit Design

9-4

One-stage op amps

Simple op amp topologies

For small-signal:

Low frequency gain = gmN (roN || roP). In general, this value hardly

exceeds 20 in submicron devices with typical current levels.

topologies, at least four devices contribute to the input noise: two

input transistors and two load transistors.

Analog-Circuit Design

9-5

Unit-gain buffer

Input common-mode voltage range

Vin,min = VCSS + VGS1

Vin,max = VDD |VGS3| + VTH1

If each device has a threshold voltage of 0.7V and an overdrive

of 0.3V, then Vin,min = 1.3V, and Vin,max = 2.7V. Thus, the input

CM range equals 1.4V with a 3-V supply.

Output impedance

Rout =

Rout ,open

1 + Av ,open

roP roN

1

independent of the open-loop output impedance.

Allowing us to design high-gain op amps by increasing

the open-loop output impedance while still achieving a

relatively low close-loop output impedance.

Analog-Circuit Design

9-6

VCSS

In order to achieve a high gain, the differential cascode topologies can be used.

Low-frequency gain Av = gmN [(gmN roN2) || (gmP roP2)], but at the cost of output

swing and adding poles.

Analog-Circuit Design

9-7

(a): The circuit providing a single-ended output suffers from a mirror pole at

node X, creating stability issues.

(b): Fully differential topology, the output swing is given by

2[VDD (VOD1 + VOD3 + VCSS + |VOD5| + |VOD7|)]

where VODj denotes the overdrive voltage of Mj.

Another drawback of telescopic cascodes is the difficult in shorting their inputs

and outputs, e.g., to implement a unity-gain buffer.

Analog-Circuit Design

9-8

Cascode op amp with input and output shorted

unit gain feedback topology

Output swing: M2 and M4 in saturation:

Vout V X + VTH 2

Vb VTH 4 Vout Vb VGS 4 + VTH 2

Vout Vb VTH 4

the voltage range Vmax Vmin = VTH4 (VGS4 VTH2)

Since the op amp attempts to force Vout to be equal to

Vin, for Vin < Vb VTH4, we have Vout Vin and M4 is in

triode region while others are saturated. Under this

condition, the open-loop gain of the op amp is reduced.

As Vin and Vout hence exceed Vb VTH4, M4 enters

saturation and the open-loop gain reaches a maximum.

For Vb VTH4 < Vin < Vb (VGS4 VTH2), both M2 and

M4 are saturated and for Vin > Vb (VGS4 VTH2), M2

and M1 enter the triode region, degrading the gain. Thus,

a cascode op amp is rarely used as a unit-gain buffer.

Analog-Circuit Design

9-9

Specifications:

VDD = 3V, differential output swing = 3V,

power dissipation = 10mW, voltage gain = 2000.

Assume nCox = 60 A/V2, pCox = 30 A/V2, n = 0.1V1, p = 0.2V1 (for an

effective channel length of 0.5 m), = 0, VTHN = |VTHP| = 0.7V.

z

z

Power budget:

IM9 = 3mA, IMb1 + IMb2 = 330A

Output swing:

Node X(Y) swing = 1.5V, M3-M6 in saturation.

For M9,

|VOD7| + |VOD5| + VOD3 + VOD1 + VOD9 = 1.5V

Since M9 carrying largest current,

VOD9 0.5V is chosen. |VOD5| = |VOD7| 0.3V,

VOD1 = VOD3 0.2V.

W/L

By ID = (1/2)Cox(W/L)(VGS VTH )2, we have

(W/L)14 = 1250, (W/L)58 = 1111, (W/L)9 = 400.

Analog-Circuit Design

9-10

z Gain:

Av gm1[(gm3ro3ro1)|| (gm5ro5ro7)]. In order to Increase the gain,

we recognize g mro = 2C ox (W / L )I D /(I D ) WL / I D

where 1/L. We can therefore increase the width or length.

Choose (W/L)58 = 1111m/1m,

then Av 4000.

z CM level & bias:

Min. allowable input CM level

= VGS1 + VOD9 = 1.4V.

Vb1,

Vb2,

min

max

= VDD (|VGS5 |+ |VOD7|) = 1.7V.

Analog-Circuit Design

9-11

In order to alleviate the drawbacks

of telescopic cascode op amps. The

primary advantage of the folded

structure lies in the choice of the

voltage levels because it does not

stack the cascode transistor on the

top of the input device.

Analog-Circuit Design

9-12

In Fig.(a), one bias current, ISS, provides the drain current of both the input

transistors and the cascode devices.

In Fig.(b), the input pair requires an additional bias current, ISS1 = ISS/2 + ID3.

Fig.(b), it cannot be less than Vb1 VGS3 + |VTH1|.

In Fig.(b), it is possible to tie the n-well of M1 and M2 to their common source point.

Analog-Circuit Design

9-13

Folded cascode op amp with cascode PMOS loads

Max. output voltage swing: With proper choice of Vb1 and Vb2,

Peak-peak swing = [VDD (|VOD7| + |VOD9|)] (VOD3 + VOD5 ) for one side.

The swing is lager by the overdrive of the tail current source in the telescopic

cascode.M5 and M6 may require a high overdrive voltage if their capacitance

contribution to nodes X and Y is to be minimized.

Analog-Circuit Design

9-14

Small-signal voltage gain

Half circuit

|Av| = Gm Rout

output shorted to ground

Iout ID1. That is Gm gm1.

output open

Rout ROP || [(gm3+gmb3)ro3(ro1||ro5)]

The gain is usually two or three times lower than of a comparable telescopic cascode.

Analog-Circuit Design

9-15

Effect of device capacitance on the nondominant pole in telescopic and folded cascode

op amps

The pole at the folding point, i.e., the sources of M3 and M4, is quite closer to the

origin than that associated with the source of cascode devices in a telescopic

topology.

Analog-Circuit Design

9-16

The circuit provides a higher gain because of the greater mobility of NMOS

devices, but at the cost of lowering the pole at the folding point,

p,X (gm3 + gmb3) / Ctot,X.

Analog-Circuit Design

9-17

z

The overall voltage swing of a folded-cascode op amp is only slightly higher than that of a

telescopic configuration. This advantage comes at the cost of higher power dissipation,

lower voltage gain, lower pole frequencies, and higher noise.

Folded-cascode op amps are used quite widely, even more than telescopic topologies,

because the input and outputs can be shorted together and the choice of the input

common-mode level is easier.

In a telescopic op amp, three voltages must be defined carefully: the input CM level

and the gate bias voltages of the PMOS and NMOS cascode transistors, whereas in

folded-cascode configurations only the latter two are critical.

In folded-cascode op amps, the capability of handling input CM levels are close to

one of the supply rails.

Analog-Circuit Design

9-18

Specifications:

VDD = 3V, differential output swing = 3V,

power dissipation = 10mW, voltage gain = 2000.

Assume nCox = 60 A/V2, pCox = 30 A/V2, n = 0.1V1, p = 0.2V1 (for an

effective channel length of 0.5 m), = 0, VTHN = |VTHP| = 0.7V.

Analog-Circuit Design

9-19

10

Power budget: IM11 = 1.5mA, IM9 + IM10 = 1.5mA, IMb1 + IMb2 + IMb3 = 330A.

Choose |VOD5,6| 0.5V, |VOD3,4| 0.4V, VOD7,8 = VOD9,10 0.3V.

(W/L)5,6 = 400, (W/L)3,4 = 313, (W/L)710 = 555.

Analog-Circuit Design

9-20

If input and output are shorted, then VGS2 + VOD11 = 1.35V,

and VGS1 = 0.95V VOD1,2 = 0.25V (W/L)1,2 = 400.

The maximum dimensions of M1,2 are determined by the tolerable input

capacitance at nodes X and Y.

gm1,2 = 0.006 A/V, gm3,4 = 0.0038 A/V, gm7,8 = 0.05 A/V.

For L = x m, find ro.

Note |Av| gm1{[(gm3 + gmb3)ro3(ro1 || ro5)] || [(gm7 + gmb7) ro7ro9]}

Analog-Circuit Design

9-21

11

Fig(a): VX = VDD |VGS5| |VGS7|,

limiting the maximum value of

Vout to VDD |VGS5| |VGS7|

|VTH6| and wasting one PMOS

threshold voltage in the swing.

Fig(b): To solve above issue, M7 and

M8 are biased at the edge of

the triode region.

z Disadvantages:

(2) it contains a mirror pole at node X, thus limiting the speed

of feedback systems employing such an amplifier.

loop to define the output CM level.

Analog-Circuit Design

9-22

9-23

Triple-cascode op amp

a gain on the order of (gmro)3/2 but

further limits the output swings. With

six overdrive voltages subtracted from

VDD in this circuit, it is difficult to

operate the amplifier from a supply

voltage or lower while obtaining

reasonable output swings.

Analog-Circuit Design

12

Two-stage op amps

and the output impedance.

z Two-stage op amps consist of first stage providing a high gain and the second

providing large swing. The first stage incorporates various amplifier topologies,

but the second stage is typically configured as a simple common- source

stage to allow maximum output swings.

z Can we cascade more than two stages to achieve a higher gain?

Each gain stage introduces at least one pole in the open-loop transfer function,

making it difficult to guarantee stability in a feedback system using such an op

amp. For this reason, op amps having more than two stages are rarely used.

Analog-Circuit Design

9-24

Gain:

Av,2nd stage = gm5,6(ro5,6 || ro7,8)

Overall gain Av = Av,1st

stage

Av,2nd

stage

Analog-Circuit Design

9-25

13

To obtain a higher, the first stage incorporate cascode devices. The overall voltage gain is

Av {gm1,2[(gm3,4 + gmb3,4)ro3,4ro1,2] || (gm5,6 + gmb5,6)ro5,6ro7,8]} [gm9,10(ro9,10 || ro11,12)]

Analog-Circuit Design

9-26

then the minimum allowable output level is equal to VGS1 + VISS, severely

limit the output swing.

Analog-Circuit Design

9-27

14

Gain boosting

Increasing the output impedance by feedback

Rout = gm2ro2ro1

M1 operates as a degeneration resistor.

lesser extent because A1 regulates this voltage. (VX = Vb)

With smaller variations at X, the current through ro1 and

hence the output current remains more constant,

yielding a higher output impedance.

Rout A1gm2ro2ro1,

Rout is booted substantially without stacking more

cascode devices on top of M2.

Analog-Circuit Design

9-28

Gain:

Since VX = VGS3, the min.value of

Vout is VOD2 + VGS3. The auxiliary

amplifier limits the output swing.

Note: Min. output swing is VOD2 +

VOD1 in a simple cascode.

regulated cascode

Analog-Circuit Design

9-29

15

equal to VOD3 + VGS5 + VISS2.

z The voltage swing limitation results the fact

that the gain-boosting amplifier incorporates

an NMOS differential pair.

Analog-Circuit Design

9-30

Half circuit

z If nodes X and Y are sensed by a PMOS pair, the minimum value of VX and

VY is not dictated by the gain-boosting amplifier.

z The minimum allowable level of VX and VY is given by VOD1,2 + VISS1.

z Output impedance: Since

VP

= gm 5Rout1

VX

Analog-Circuit Design

9-31

16

Regulated cascodes can also be utilized in the load current sources of a

cascode op amp.

Analog-Circuit Design

9-32

Gain

Output

Swing

Speed

Power

Dissipation

Noise

Low

Low

Telescopic

Medium

Medium

Highest

Folded-Cascode

Medium

Medium

High

Medium

Low

Medium

Two-stage

High

Highest

Gain-Boosted

High

Medium

Analog-Circuit Design

9-33

Medium

High

Medium

Low

Medium

17

z Full differential circuits have many advantages over their single-ended

counterparts such as greater output swings, avoiding mirror poles, higher

closed-loop speed. However, high-gain differential circuits require commonmode feedback.

z Simple differential pair

level is equal to VDD ISS RD /2

Analog-Circuit Design

9-34

Since each of the input transistors carries a current ISS /2, the CM level depends on

how close ID3 and ID4 are to this value.

z Effect of current mismatches: Mismatches in the PMOS and NMOS current mirrors

defining ISS and ID3,4 create a finite error between ID3,4 and ISS /2.

If ID3,4 > ISS /2, then both M3 and M4 must enter the triode region so that their drain

currents fall to ISS /2. Conversely, If ID3,4 < ISS /2, then both VX and VY must drop so

that M5 enters the triode region, thereby producing only 2ID3,4.

Analog-Circuit Design

9-35

18

In high-gain amplifiers, we wish a p-type current source to balance an n-type current

source.

V = (I P I N )(RP RN )

Since the current error depends on mismatches and RP||RN is quite high, the voltage

error may be large, thus driving the p-type or n-type current source into triode region.

As a general rule, if the output CM level cannot be determined by visual inspection

and requires calculations based on device properties, then it is poorly defined.

In high-gain amplifiers, the output CM level is quite sensitive to device properties and

mismatches and it cannot be stabilized by means of differential feedback. Thus a

CMFB network must be added to sense the CM level of the two outputs and

accordingly adjust one of the bias currents in the amplifier.

Analog-Circuit Design

9-36

In high-gain amplifiers, the output CM level is quite sensitive to device properties and

mismatches and it cannot be stabilized by means of differential feedback. Thus a CMFB

network must be added to sense the CM level of the two outputs and accordingly adjust

one of the bias currents in the amplifier.

Analog-Circuit Design

9-37

19

z Resistive divider level: Vout,CM = (R1Vout2 + R2Vout1)/(R1 + R2)

= (Vout1 + Vout2)/2, if R1 = R2.

z R1 and R2 must be much larger than the output impedance of the op amp

so as to avoid lowering the open-loop gain.

Analog-Circuit Design

9-38

Current starvation of source followers for large swings

that is lower than the output CM

level by VGS7,8, but this shift can be

taken into account in the

comparison operation.

z R1 and R2 or I1 and I2 must be large

enough to ensure that M7 or M8 is

not starved when a large differential

swing appears at the output.

Analog-Circuit Design

and ID7. Consequently, if (R1 + R2) or I1 is

not sufficiently large, ID7 drops to zero

and Vout,CM no longer represents the true

output CM level.

output swings. The swing at each output is

reduced by approximately VTH, a significant

value in low-voltage design.

9-39

20

z Identical transistors M7 and M8 operate in deep triode region,

RP = Ron 7 Ron 8

1

1

W

W

nCox (Vout1 VTH ) nCox (Vout 2 VTH )

L

L

1

=

W

nCox (Vout1 + Vout 2 2VTH )

L

Vout2 Vout1.

The use of M7 and M8 limits the output voltage swings, Vout,min = VTH7,8, which is

relatively close to two overdrive voltages, but the difficulty arises from the assumption

above that both M7 and M8 operate in deep triode region. If Vout1drops from the

equilibrium CM level to one threshold voltage above ground and Vout2 rises by the same

amount, then M7 enters the saturation region, thus exhibiting a variation in its onresistance that is not counterbalanced by that of M8.

Analog-Circuit Design

9-40

We employ a simple amplifier to detect the difference between Vout,CM and a reference

voltage, VREF, applying the result to the NMOS current sources with negative feedback.

If the loop gain is large, the feedback network forces the CM level of Vout1 and Vout2 to

approach VREF.

Also, the feedback may control only a fraction of the current to allow optimization of the

settling behavior. For example, each M3 and M4 can be decomposed into two parallel

devices, one biased at a constant current and the other driven by the error amplifier.

Analog-Circuit Design

9-41

21

of the input differential pair. This method increases the tail current if Vout1

and Vout2 rise, lowering the drain currents of M5M6 and restoring the output

CM level.

Analog-Circuit Design

9-42

z The output CM level sets Ron7 || Ron8 such that

ID5 and ID6 exactly balance ID9 and ID10, respectively.

z Assuming ID9 = ID10 = ID,

RP = Ron7|| Ron8 = (Vb VGS5)/(2ID ), and also

RP =

1

W

nCox (Vout 2 + Vout1 2VTH )

L 7,8

where VGS 5 =

2I D

nCox (W / L )5

+ VTH 5

z Drawbacks:

1.The value of the output CM level is a function of device

parameters.

2.The voltage drop across Ron7||Ron8 limits the output voltage swing.

3.To minimize this drop, M7 and M8 are usually quite wide devices, introducing

substantial capacitance at the output.

Analog-Circuit Design

9-43

22

z If Vb is higher than expected, the tail current of M1 and

M2 increases and the output CM level falls. Since the

feedback through M7 and M8 attempts to correct this

error, the overall change in Vout,CM depends on the loop

gain in the CMFB network.

z Determine the sensitivity dVout,CM/dVb:

M7,8 in triode region: gm7,8 = nCox(W/L)7,8VDS7,8

Feedback factor:

V2

V1

Thus,

= ( g m 7 + g m8 )(Ron 7 Ron8 ) =

I 2 =0

dVout ,CM

dVb

VDS 7,8

VGS 7 ,8 VTH

VDS 7,8

in the vicinity of VDD/2, the above equation

suggests that VDS7,8 must be maximized.

Analog-Circuit Design

9-44

z The idea is to define Vb by a current mirror arrangement such that ID9 tracks I1 and IREF.

z Suppose (W/L)15 = (W/L)9 and (W/L)16 = (W/L)7 + (W/L)8.

Thus, ID9 = I1 only if Vout,CM = VREF.

The circuit produces an output CM level equal to a reference but it requires no resistors in

sensing Vout,CM.

z In practice, since VDS15 VDS9, channel-length modulation results in a finite error.

Analog-Circuit Design

9-45

23

z Transistors M17 and M18 reproduce at the drain of M15 a voltage equal to the

source voltage M1 and M2, ensuring that VDS15 = VDS9.

Analog-Circuit Design

9-46

z

The input CM level, VDD VGS3,4, is relatively

well-defined, but the voltage gain is quite low.

Resistive CMFB

To increase the differential gain, the PMOS

device must operate as current sources for

differential signals.

For differential change at Vout1 and Vout2, node

P is a virtual ground and the gain can be

expresses as

Av = gm1,2(ro1,2||ro3,4||RF)

For CM levels, M3 and M4 operate as diodeconnected devices.

Analog-Circuit Design

9-47

24

z

z

Limitation: While the differential input swings are usually much smaller, the input

common-mode level may need to vary over a wide range in some applications.

Unity-gain buffer

The voltage swings are limited by the input differential pair rather than the

output cascode branch. Specifically, Vin,min Vout,min = VGS1,2 + VISS, approximately

one threshold voltage higher than the allowable minimum provided by M5-M8.

If Vin < Vin,min: The MOS transistor operating as ISS enters the triode region,

decreasing the bias current of the differential pair and hence lowering the

transconductance.

Analog-Circuit Design

9-48

z A simple approach to extending the

input CM range is to incorporate

both NMOS and PMOS differential

pairs such that when one is dead,

the other is alive. This idea is to

combine two folded-cascode op amps

with NMOS and PMOS input

differential pairs.

z As the input CM level approaches the

ground potential, the NMOS pairs

transconductance drops, eventually

falling to zero. Nonetheless, the PMOS

pair remains active, allowing normal

operation. Conversely, if the input CM

level approaches VDD, M1P and M2P

begin to turn off but M1 and M2 function

properly.

Analog-Circuit Design

9-49

the input CM level.

25

Slew rate

z

step

dVout V0

t

= exp

dt

dVout/dt V0; if we apply a larger input step, the output rises more rapidly.

Analog-Circuit Design

9-50

z

Assume op amp is linear,

1

Vout

R2

A Vout

=

+ Vout C L s

Vin Vout

R

R

R

R

+

1

2

1 + R2

out

Assume R1 + R2 >> Rout, we have

Vout

A

(s )

Vin

R2

Rout CL

1+

1 + A

s

R1 + R2 1 + AR2 (R1 + R2 )

Vout

t

1 exp

u (t )

= V0

R2

C L Rout

1+ A

R1 + R2

1 + AR2 (R1 + R2 )

A

This type of response is called linear settling.

Analog-Circuit Design

9-51

26

z

Vout = V0

t

1 exp

u (t )

R2

C L Rout

1+ A

R1 + R2

1 + AR2 (R1 + R2 )

A

..(A)

The response to sufficiently small inputs follows the exponential of Eq.(A), but

with large input steps, the output displays a linear ramp having a constant slope.

Under this condition, we say the op amp experiences slewing and call the slop of

the ramp the slew rate.

Analog-Circuit Design

9-52

If Vin experiences a change of V, the total small-signal current provided

by the op amp equals gmV. This current begins to change CL, but as Vout

rises, so does VX, reducing the difference between VG1 and VG2 and hence

the output current of the op amp.

Analog-Circuit Design

9-53

27

z Slewing during low-to-high transition

M1 absorbs all of ISS and M2 turns off.

So long as M2 remains off, the feedback

loop is broken and the current charging

CL is constant and independent of the

input level.

z Slewing during high-to-low transition

Analog-Circuit Design

9-54

response, the large-signal speed may be limited by the slew rate simply

because the current available to charge and discharge the dominant

capacitor in the circuit is small.

z Since the input/output relationship during slewing is nonlinear, the output of

a skewing amplifier exhibits substantial distortion.

For example, if a circuit is to amplify a sinusoid V0sin0t (in the steady

state), then its slew rate must exceed V00.

Analog-Circuit Design

9-55

28

Vout1 and Vout2 appear as a ramps with slopes equal to ISS /(2CL), and

consequently Vout1 Vout2 exhibits a slew rate equal to ISS /CL.

Analog-Circuit Design

9-56

z

Analog-Circuit Design

9-57

29

z

If ISS > IP, then during slewing M3 turns off and VX falls to a low level such that M1

and the tail current source enters the triode region. Thus, for the circuit to return to

equilibrium after M2 turns on, VX must experience a large swing, slow down the

settling.

Analog-Circuit Design

9-58

z

M11, or M12, requiring only enough drop in VX or

VY to return on one of these transistors.

Since the equilibrium value VX and VY is usually

higher than VDD VTHN, M11 and M12 are off

during small signal-signal operation.

Analog-Circuit Design

9-59

30

z If the circuit in the figure is perfectly symmetric, Vout = VX.

Since the diode-connected device clamps node X to VDD

VX and hence Vout experience approximately the same

change as does VDD. In other words, the gain from VDD to

Vout is

Vout

1

VDD

z The power supply rejection ratio (PSRR) is defined as

the gain from the input to the output divided by the gain

from the supply to the output. At low frequencies:

PSRR =

Vout Vin

g mN (roP roN )

Vout VDD

Analog-Circuit Design

9-60

z

Guide: With many transistors in an op amp, it may seem difficult to intuitively identify

the dominant sources of noise. A simple rule for inspection is to change the gate

voltage of each transistor by a small amount and predict the effect at the output.

At relatively low frequency, the

cascode devices contribute negligible

noise, leaving M1-M2 and M7-M8 as the

primary noise sources.

Analog-Circuit Design

2g

g2

KN

KP

2

Vn2 = 4kT 2

+2

m2 7,8

+ 2 m2 7 ,8 + 2

3 g m1, 2

WL

C

f

WL

C

f

(

)

(

)

g

3

g m1, 2

1, 2 ox

7 ,8 ox

m1, 2

and PMOS devices, respectively.

9-61

31

z The noise of the cascode devices is negligible at low frequencies,

leaving M1-M2, M7-M8, and M9-M10 as potentially significant sources.

z Thermal noise:

Vn2,out

M 7 ,8 =

2

2

, (uncorrelated noise)

g m2 7 ,8 Rout

2 4kT

g

3

m 7 ,8

Rout denotes the open-loop output resistance of the op

amp.

Vn2,out

M 9,10 =

Vn2,out

M 1, 2

2

2

g m2 9,10 Rout

2 4kT

g

3

m

9

,

10

2

2

g m2 1, 2 Rout

= 2 4kT

g

3

m

1

,

2

and Av = gm1,2Rout.

Total input-referred thermal noise:

Vn2,in =

Vn2,out ,tot

Av2

2

2 g m 7,8 2 g m9,10

= 8kT

+

+

2

2

3

g

m1, 2 3 g m1, 2 3 g m1, 2

Analog-Circuit Design

9-62

z Flicker noise:

KP

1 2

2

g m 7 ,8 Rout

2

C

WL

f

(

)

7 ,8

ox

Vn2,out

M 7 ,8 =

Vn2,out

M 9 ,10 =

Vn2,out

M 1, 2 =

KN

1 2

2

2

g m9,10 Rout

KN

1 2

2

g m1, 2 Rout

2

and Av = gm1,2Rout.

Total input-referred flicker noise:

Vn2,in =

=

Vn2,out ,tot

Av2

2K N

Cox f

2

1

g m2 9,10 2 K P

1

1 g m 7 ,8

+

2

(WL ) + (WL )

Cox f (WL )7 ,8 g m2 1, 2

1, 2

9 ,10 g m1, 2

Analog-Circuit Design

9-63

32

z The overall noise:

2

2 g m 7 ,8 2 g m 9,10

+

+

Vn2,in = 8kT

3

3 g m2 1, 2 3 g m2 1, 2

g

1

,

2

m

2

g m2 9,10 2 K P

2 K N 1

1

1 g m 7 ,8

+

+

+

2

z Discussion:

The noise contribution of the PMOS and NMOS

current sources increases in proportion to their

transconductance. This trend results in a trade-off

between output voltage swings and input-referred

noise: for a given current, as implied by

gm = 2ID /(VGS VTH), if the overdrive voltage of

the current sources is minimized to allow large

swings, then their transconductance is maximized.

Analog-Circuit Design

9-64

z Total voltage gain: Av = gm1(ro1||ro3) gm5(ro5||ro7).

z In the 2nd stage: The noise current of M5 and M7 flows through ro5||ro7.

Vn2

M 58

= 2 4kT

2

( g m5 + g m7 )(ro5 ro7 )2 12 = 16kT 2 g m25 + g m 7 2

3

3 g m1 g m5 (ro1 ro3 )

Av

Vn2

M 14

= 2 4kT

2 g m1 + g m3

3 g m2 1

Vn2,tot =

g + g m7

16kT 1

g m1 + g m3 + 2 m5

2

3 g m2 1

g m5 (ro1 ro3 )

stage is usually negligible because it is

divided by the gain of the first stage when

referred to the main input.

Analog-Circuit Design

9-65

33

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