Design and Simulation of 32 Bit Floating Point FFT Processor Using VHDL

IPASJ International Journal of Electronics & Communication (IIJEC)
Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

Email: editoriijec@ipasj.org
ISSN 2321-5984
A Publisher for Research Motivation........
Volume 4, Issue 6, June 2016
Design and Simulation of 32 bit Floating Point

FFT Processor Using VHDL
Mr.Roshan Pahune1, Dr.Mrs.AnaghaRathkanthiwar2
1
M.Tech Student [VLSI] ,Dept. of Electronics Engg , PCE, Nagpur, India

2
Associate Professor , Dept. of Elect & Tele. Engg ,PCE, Nagpur,India
ABSTRACT
FFT & IFFT algorithms has gainedlot of importance since use of OFDM technology in communication system. OFDM
technology is implemented using FFT & IFFT. We are here with presenting thedesign of a 32 bit floating point FFT
processor. For design and implementation of FFT processor we have consider radix-2 DITFFT algorithm. The floating point
number can support wide range of values. It is represented using three fields: sign, exponent and mantissa. In this paper
floating point addition, subtraction and multiplication algorithms for IEEE-754 (single precision)is used. The IEEE-754
converter is used to convert decimal floating point number into IEEE Binary floating point format and it is also used to verify
the results. For performance measurement of this design, various parameters like number of flip flops, number of LUTs, delay
and complexity are obtained. The results are compared with existing design and are presented in this paper.
KEYWORDS :-Floating Point Number, FFT, DIT, Radix-2, VHDL.
I. INTRODUCTION
This paper describes a methodology to design floating point Fast Fourier Transform (FFT) processor using VHDL.
This Design follows 32 bit single precision IEEE -754 standards. Floating point number can be represented using three
fields sign, exponent and mantissa. The memory requirement and power consumption is more for floating point
algorithms.
1.1 Floating Point Number Representation
The IEEE-754 single precision and double precision format is used to represents the floating point numbers. The
floating point numbers can support the wide range of values. The IEEE-754 floating point format have three basic field:
sign, exponent, and mantissa.
a) Sign
The sign bit is one bit field. If this bit is 1 then it denotes positive number and if it is 0 then it denotes a negative
number.
b) Exponent
The exponent is 8 bit field for IEEE-754 single precision format and 11 bit for IEEE-754 double precision format. For
single precision format the bias value of exponent is 127 and for double precision format the bias value of exponent is
1023.
c) Mantissa
The mantissa is 23 bit field for IEEE-754 single precision and 52 bit for IEEE double precision format. Mantissa is
also known as significant.
Table 1. IEEE-754 Single Precision Format
S
1
E
8
M
23
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Table2. IEEE-754 Double Precision Format

S
1
E
11
M
52
1.2 IEEE-754 Converter

The IEEE -754 Converter is used to convert decimal floating point number into IEEE binary format and IEEE binary
format to decimal floating point number .This converter is also used to convert decimal floating point number into
hexadecimal and hexadecimal to decimal floating point number.
Fig 1: IEEE- 754 Converter

1.3 Fast Fourier Transform
To compute the Discrete Fourier Transform (DFT) the Fast Fourier Transform (FFT) is widely used in the field of
digital signal processing (DSP) such as filtering, spectral analysis etc. For various applications such as image
processing, speech, audio, radar and biomedical signal processing the FFT is widely used. The general formula for
FFT is
In this paper the input is taken as floating point number. The FFT can be compute using two methods: Decimation in
Time (DIT) and Decimation in Frequency .In DIT-FFT method we take the data from bit reversal order to normal
order and in DIF-FFT we take its converse. The computation of FFT using DIT method is easy as compare to DIF
method. By using the radix-2 or radix-4 algorithm we can design FFT Processor. In this paper we used the radix-2
algorithm. The radix-2 algorithm is divide the N-point FFT into smaller ones until two point FFT is obtained. This
algorithm divide the N- point FFT into two point FFT therefore it is called as a radix-2 algorithm.The FFT processor
have very fast execution speed and low power consumption when it is used in wireless communication systems. The
floating point FFT is a time consuming and it consumes a larger amount of area and power. When we design 8 point
floating point FFT then it increases complexity.
2. RESULTS ANDSIMULATION
2.1 Flow Diagram of 8 PointDITFFT
To design the 8 Point FFT processor we have use Decimation in Time method (DIT). In DIT method we have to take
input in the form of odd & even numbers . First 4 input is taken as odd & next 4 input is taken as even. The final FFT
output is taken from serially X(1) to X(8).
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Fig 2: Flow Diagram of 8 Point DITFFT
Input : Each input of FFT is represented as a real & imaginary values

x(1) = 16.5 - 10.5j
x(2) = 16.5 - 10.5j
x(3) = 16.5 - 10.5j
x(4) = 16.5 - 10.5j
x(5) = 16.5 - 10.5j
x(6) = 16.5 - 10.5j
x(7) = 16.5 - 10.5j
x(8) = 16.5 - 10.5j
Real input values
={ 16.5, 16.5, 16.5, 16.5, 16.5, 16.5, 16.5, 16.5 }
Imaginary input values
={-10.5,-10.5,-10.5, -10.5, -10.5, -10.5, -10.5,-10.5 }
Using IEEE-754 converter, the decimal floating point value is converted into binary IEEE-754 format.
The IEEE-754 binary representation of 16.5 &- 10.5 is
16.5 = 01000001100001000000000000000000
-10.5 = 11000001001010000000000000000000
Output : We get output values which in the form also real & imaginary values.
X(1) = 132 -84 j
X(2) = 0 0 j
X(3) = 0 0 j
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X(4) = 0 0 j
X(5) = 0 0 j
X(6) = 0 0 j
X(7) = 0 0 j
X(8) = 0 0 j
Real output values

= { 132, 0, 0, 0, 0, 0, 0, 0, }
Imaginary output values
= { -84, 0, 0, 0, 0, 0, 0, 0, }
The IEEE-754 binary representation of this output values are

132 = 01000011000001000000000000000000
-84=11000010101010000000000000000000
0 = 00000000000000000000000000000000
All these output values can be calculate using MATLAB tools and verify the result using IEEE-754 converter.
2.2 RTL View of 8 Point Floating Point FFT
The RTL view of 8 Point Floating Point FFT consist of inputs and output values . Each input and output is 32 bit.
There are 16 input and 16 output . Out of 16 input 8 input are real and 8 input are imaginary, same for 16 output
output ,8 output are real and 8 output are imaginary.
Fig 3:RTL view of 8 Point Floating Point FFT
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Fig 4: Internal RTL view of 8 Point Floating Point FFT

2.3 Simulation Result of 8 Point Floating Point FFT
The output of FFT in the form of IEEE-754 binary floating point format. There are total 16 output in which 8
output are real & 8 output are imaginary
Fig 5 : Simulation Result of 8 Point Floating Point FFT (inputs)
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Fig 6: Simulation Result of 8 Point Floating Point FFT (outputs)

2.4 ComparisonTableof Floating Point FFT For 8 Point
1) Design-A: It is a design presented by the Author in this paper.
2) Design-B:It isa design presented by the HilalKaptan , Ali Tangel , SuhapSahin in FPGA Implementation of FFT
Algorithms Using floating Point Numbers.
Table 3. Complete Design of Floating Point FFT
Selected Device
Number of Slices
Number of Slice
Flip-Flops
Number of 4 Inputs
LUTs
Number of Bonded
IOBs
Number of GLKs
Design A
FFT
Vertex-2P
56277 out of 13696
1564 out of 27392
%
410
5
Design- B
FFT
Vertex-2P
1989 out of 13696
896 out of 27392
105953 out of
27392
1026 out of 416
387
3627 out of 27392
13
246
33 out of 416
1 out of 16
1 out of 16
14
3
3.CONCLUSION
In this paper, the 8 Point floating point FFT Processor is synthesized and simulated using VHDL tools. The VHDL
code has been successfully synthesized using Xilinx ISE 9.2i tools and Simulated using ISE Simulator. The output
values of FFT are verified using MATLAB tool and IEEE-754 converter. The Minimum period required for
computation of FFT is 80.976 ns. The Floating point FFT achieved the maximum frequency of 12.349 MHz with delay
80.976 ns and area of 56277slices. The total memoryrequirement is 1360812 kilobytes. The Result are compared with
existing design (design-B) in table 3 which shows the comparable performance of our design.
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4.FUTURE SCOPE
The floating point support the wide range of values. The floating point FFT Processor for double precision (64 bit) can
also be designed and simulated. Also the design can be implemented using suitable hardware platform. In this paper,
we have presented design & simulation of 8 point floating point FFT processor and the same design can be extended to
16 point & 32 point.
REFERENCES
[1] B. Tharanidevi and R. Jayaprakash Implementation of double precision floating point radix-2 FFT using
VHDL.International Journal of Advanced Research in Electrical,Electronics and Instrumentation Engineering
(An ISO 3297: 2007 Certified Organization) Vol. 2, Issue 10, October 2013.
[2] Hilal Kaptan1, Ali Tangel1 ,Suhap Sahin2,FPGA Implementation of FFT Algorithm Using Floating Point
Numbers Kocaeli University, College of Engineering, Department of Electronics and Communication
Engineering,VezirogluYerleskesi, 41040, Izmit, Turkey.
[3] Neha V. Mahajan, Dr. J. S. Chitode Simple Computation of DIT FFTInternational Journal of Advanced
Research in Computer Science and Software Engineering Volume 4, Issue 5, May 2014 ISSN: 2277 128X .
[4] Afreen Fatima Designing and Simulation of 32 Point FFT using Radix-2 algorithm for FPGA,IOSR Journal of
Elecrical and Electronics Engineering (IOSR0JEEE) e-ISSN:2320-3331, Volume9, Issue1 Ver,III (Jan 2014), PP
42-50.
[5] PrasannaPalsodkar, Ajay Gurjar Fused Floating Point Add-Subtract and Multiply-Add Unit for FFT
Implementation 2014 2nd International Conference on Devices, Circuitand Systems (ICDCS).
[6] P S Raja Kumar, G. Surya Narayana Reddy Implementation of FFT algorithm using floating point numbers in
wimax communication system.International Journal of VLSI and Embedded Systems-IJVES ISSN: 2249 6556
Vol 04, Article 07133; July 2013
[7] ChenluWu , Wei Cao, Xuegong Zhou, Lingli Wang , Fang Wang , Baodi Yuan A Reconfigurable Floating-Point
FFT Architecture.978-1-4673-6417-1/13/$31.00 2013 IEEE.
[8] Sukhvir Kaur , Parminder Singh Jassal Synthesis of Double Precision Float-ing Point Multiplier using VHDL
Journal of Research in Electrical and Electronics Engineering (ISTP-JREEE) . Vol 3, Issue 2, March 2014.
[9] AddankiPurna Ramesh, Rajesh Pattimi High Speed Double Precision Floating Point Multiplier International
Journal of Advanced Research in Computer and Communication EngineeringVol. 1, Issue 9, November 2012.
[10] VeeraKamatDhakankar, Prof. Sonia Kuwelkar Design and Implementation of Pipelined Floating Point Fast
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[11] W. B. Ligon, S. McMillan, G. Mpnn, F. Stivers, and K. D Underwood A Re-evelation of the Practicality of
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[12] S. ahin, A. Kavak., Implementation of Floating Point Arithmetic Using an FPGA,Mathematical Methods in
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[13] J. G. Proakis, Digital signal processing: principles, algorithms, and applications, Prentice-Hall Intemational,
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[14] J.Bhaskar, A VHDL PRIMER,Third Edition.
AUTHORS BIOGRAPHY
Mr. Roshan N. Pahune received the B.E degree in Electronics and Telecommunication
Engineering in the year 2014 from SGBAU,Amravati, India. He is currently doing M.Tech
degree in (VLSI) from PCE, Nagpur, under RTMNU, Nagpur, India. He has published two
paper in international journal ( IJCA ) and ( IJAREEIE ) and one paper in national
conference (NCRTCSIT-16) held at PCE, Nagpur. His research focuses on the Floating Point
FFT Processor based on Radix-2 using VHDL. He was Class Representative in department of
Electronics and Telecommunication Engineering in IBSS college, Amravati . His area of interest are Digital Signal
Processing, Fast Fourier Transform (FFT), Communication and VLSI.
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Anagha Rathkanthiwar did her BE (ElectronicsEngg) and M.Tech. (Electronics) in 1992

and 2003 respectively from RTMNU ,Nagpur (Nagpur University). She has completed her
Ph.D. fromVesvesvaraya National Institute of Technology (VNIT), Nagpur in 2015.
Currently, she is working as Associate Professor in Electronics & Telecommunication
Engineering Department, Priyadarshini College of Engineering, Nagpur, Maharashtra,
India and have total teaching experience of 19 years. She has published 30 research papers
in international conferences and journals. She has received best paper award for the paper
presented in GWS-13 at Atlantic City NJ, USA. Her research interests include signal processing, wireless
communication. She has reviewed several research papers of International and National conferences. Also she has
chaired sessions at International and National Conferences. E-mail:
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Design and Simulation of 32 Bit Floating Point FFT Processor Using VHDL

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IPASJ International Journal of Electronics & Communication (IIJEC)

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

A Publisher for Research Motivation........

Volume 4, Issue 6, June 2016