An Improved Zero-Voltage and Zero-Current-Switching PWM

Full-Bridge DC-DC Converter

A. Jangwanitlert * ,K. J. Olejniczak **, J. C. Balda *
* Electrical Engineering D e p a r t m e n t , University of Arkansas ,Fayetteville, AR
**College of Engineering , Valpariso University, Indiana
Email: ajangwa@uark.edu

Abshoef- An improved isolated Zero-Voltage and ZeroCurrent Switching Full-Bridge Pulse Width Modulation
(ZVZCS-FB-PWM) DC-DC converter having dual voltage
outputs of 42 V and 5 V is presented. The leading leg
achieves zero voltage switching, and the lagging leg with a
series diode and active snubber .circuit achieves zero
current switching. A Phase-Shifted (PS) PWM technique is
used to obtain ZVZCS by equalizing the small dead times.
Also, PS-PWM strategy with a robust average currentmode control can regulate the output voltage to obtain
stability and reliability. Furthermore, the active snubber
circuit is replaced with a flyback converter operated in the
ZVS discontinuous conduction mode due to the ringing
voltage of the fast recovery diodes in the secondary side.
The steady-state analysis of the topology is illustrated. In
this paper, simulated and experimental results are shown to
verify the validity of the proposed concept. Moreover, this
configuration and results in lower conduction losses in the
primary side are well-suited for applications above a few
kilowatts
1. Introduction

Recently, many new techniques such as soft-switching

have been proposed for high frequency power conversion
to reduce the component stress of voltage and current and
the switching losses in traditional pulsewidth-modulation
(PWM) converters. The zero-voltage and zero currentswitching phase-shifted full-bridge pulsewidth modulation
(ZVZCS PS-FB-PWM) converters are one of the most
desirable since they can reduce switching loss remarkably
without the penalty of a significant increase in conduction
loss. Moreover, the converter operates with a fixed
frequency, which enables the design optimization of the
circuit with little trouble [ 1-31. However, the phase-shifted
PWM control in FB converter has a disadvantage because a
relatively large circulating current makes the switching
devices and/or the transformer during the freewheeling
interval loss power [3]. Also, this circulating current makes
the conduction losses of the switching devices and
transformer high compared to those of hard-switching
PWM converters.
Furthermore, in most PS-PWM
switching converters, the dead time of the lagging-leg
switches is much smaller than that of the leading-leg
switches to maintain soft-switching. To solve these
problems, ZVZCS-PS-FB-PWM converters using a simple
auxiliary circuit and blocking capacitor have been

0-7803-7906-3/03/$17.0002003 IEEE.

presented [I-51. Nevertheless, the use of those methods to

reduce the circulating current and dead time has
disadvantages such as ringing voltage and spike in the
secondary side of the transformer.
This paper proposes an improved ZVZCS PS-FB-PWM
DC-DC converter with the leading leg operating in the ZVS
mode, and the lagging leg operating in the ZCS mode. The
leading-leg switches are power MOSFETs with internal
diodes and capacitors to reduce the current of the tailing
edge and spike voltage, and the ZVS is achieved in the
same manner as that of the ZVS-FB-PWM converter [6,7],
whereas the lagging-leg switches are IGBTs [SI and the
ZCS is achieved by resetting the primary current during the
freewheeling period using a blocking capacitor voltage in
the primary side. Moreover, the dead time during the
lagging-leg operating should be equal to the dead time of
leading-leg operating in order to easily design.
Furthermore, the voltage of the secondary-side active
snubber circuit, which is less than the dc link voltage, is
also applied for resetting the primary current. In addition,
the active snubber circuit can reduce the voltage stress and
ringing voltage of the fast recovery diodes in the secondary
side. The active snubber can generate voltage to support
another output as well.
11. System Configuration

Fig. I shows the system configuration of the proposed

ZVZCS-FB-PWM switching converter. The power circuit
of the high-frequency inverter consists of a single-phase
voltage-source inverter using IGBTs and MOSFETS. The
source voltage is 300 Vm. In this paper, a primary side
assisted ZVZCS DC-DC converter is proposed using a
blocking capacitor Cbo on the primary side and an active
snubber on the secondary side. The power rating of the
active snubber is equal or less than I% of that of the main
circuit because the snubber circuit is used for reducing
ringing in the fast recovery diodes, which causes excessive
power loss in the switching devices. This loss results in
lower converter efficiencies [9]. In addition, the active
snubber also supports the lagging leg of the inverter circuit
in order to achieve ZCS mode and provides 5 V,C using a
flyback converter under ZVS operation. Moreover, to
obtain stability and reliability, the robust average current
mode control strategy is used together with PS-PWM
control.

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111. Operational Principles

The basic operation of the proposed ZVZCS-FB-PWM

switching converter is the same as that of the ZVS-FBPWM converter using phase-shifted PWM control. The
new converter has fourteen intervals of operation for each
operating cycle. The operational waveforms and equivalent
circuits are shown in Figs. 2 and 3, respectively. To
illustrate the steady-state operation, several assumptions arc
made:

* components are ideal;

output filter inductor Lf is lar;:e enough to be treated as a

constant current source during a switching interval;
capacitors C, and C, are identical ( CI=Cl =C,).
Throughout the switching of each leg, switches SI and
S1 (or S2 and Sq ) turn on and tum off alternately with
nearly 50% duty cycle ratio, and the phase shift introduced
by the two legs determines the operating duty cycle of the
converter. A brief description of the different intervals of
operation follows:

Fig. 1 ZVZCS-FB-PWM system configuration

Interval I (b-tl) : At time b, S I and S2 are conducting,
and the primary current ip charges the capacitor Cbo.Ss is
also conducting. Cbl is charged and Cb2is discharged in the
secondary side. Cbois the blocking capacitor, and Cbi and
Cbl are used for resetting the primary current. Cbl and Cb2
allow to use a Cm that is not large enough and block the
voltage in the primary side. In addition, they are used in the
active snubber circuit, which can reduce ringing voltage
due to the fast recovery diodes. ln this interval, the input
power is delivered to the output. The primary current at
time to, and capacitor Cbovoltage are given by:

where
and

lor, Io2 are the output currents.

T,, , Tr2 arc the turn ratios of the transformers T,,
TA respectively.

Interval 2 (tl-t,) : SI and S, arc still turned on. Cbl and

Cb2are still charged, and S, is hirned off
Interval 3 (t2-tl) : SI is turned off at t,. The primary
current ip charges C, and discharges C,. The voltage across
CI rises linearly, and the voltage across C, decreases
linearly. Subsequently, the diode D, (the anti-parallel diode
of S3) will conduct.
S, can be turned on with complete ZVS. On the other
hand, SI can be turned off. For this leading leg, the ZVS is
achieved exactly in the same manner as that of the ZVSFB-PWM converter. For the secondary side, the operation
is the same as in Interval 2. The primary current ip and
capacitor Cbovoltagearc given by:

where

I, 5

t3.

Interval 4 (t&) : After 11, starts conducting, the

voltage vABis clamped to zero, and the voltage across the
blocking capacitor CbOis applied to the primary winding.
Because the blocking capacitors Cbl and Cb2 arc large
enough to be treated as a constant voltage source during
this interval, the primary cun-ent ip decreases almost
linearly. For the secondary side,, the operation is still the
same as in Interval 3. The primary current ip and capacitor
Cbovoltageare given by:
Fig. 2 The operational waveforms

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-.__... .

-..,..:

.,.

-2

I"lsr*al I

..............
. . ,........

Fig. 3 Intervals of operation.

i,

(1) = -

'CbO

('1 =

v C h U ( f - f , ) + ~ p o

L i*

(I

,1

'Chop

(5)
(6)

where Vapo is the peak voltage across capacitor Cw.

; During this interval, D, and S2
Interval 5 )&t(
conduct. The primary current i, will attempt to go negative
when it reaches zero. The primary current stays at zero
because D2 blocks the primary current ip from going
negative. The blocking capacitor voltage stays constant
during this time. S2 is still turned on, but no current flows
through it. Subsequently, the minority carries can be
removed if S2 is an IGBT. For the secondary side, the
capacitor Cbl is discharged, and Cbz is charged via diode
D,.
In this interval, the active snubber and blocking
capacitor Stan to reset the primary current. The effect of
the active snubber is less than that of the blocking capacitor
C ~ because
O
its capacitance is large.

Interval 6 (ti&) : SZ is turned off at the end of the

freewheeling period, and the remaining minority carriers
are removed during this dead time. Finally, the primary
circuit is open. However, fast recovery diodes conduct in
the power circuit, equally sharing the load current; Dg is
turned off, but the capacitor CO>is discharged.
Interval 7 (I&) : At k, S , is turned off with ZCS before
Sq is turned on for a short time period. This turn-on process
is also ZCS because the leakage inductor L. limits the
diddt during this short switching time. After tuming on S4,
the primary current i p increases linearly in the negative
direction since the secondaly fast diode rectifiers conduct
clamping of both the primary voltage and secondary
voltage of the transformer at zero. So, Vs+Vcbo is applied
on 4 r and the primary winding. For the secondary side,
Co2is discharged through the load.

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Interval 8 (I&) : S4 and S, are turned on. The primary

current charges Cw on the other side. D, and DR are
reversed biased turning off, and Ds and D6are forward
biased turning on. While Cbl is charged, Cb, is discharged
at the same time. After Cbz is discharged, S, begins to turn
an under the ZVS mode again due to the fact that SI has
twice the switching frequency of S&
Intervals 9-14 (tx-tlr) : These intervals are similar to
Intervals 2-8, respectively. Nevertheless, they operate on
the second half of the cycle. Interval 15 repeats Interval I

T 12

Fig. 4 The maximum duty cycle.

In the case of CbObeing small, not large enough to be
treated as a constant voltage scItuce, the equation for Cbo
should be:

IV. Design Considerations

The maximum duty cycle of the ZVZCS-FB-PWM
converter is limited by the parameters as illustrated in Fig.
4. The maximum duty cycle can be expressed as follows:

where T,,,, is the primary current reset time, T,, is defined

by the tum off time of the power devices, and T is the
switching period.
If the blocking capacitor Cbo is large enough to be
considered as a constant voltage source during Interval 4,
T,,,, is given by:
T,*.<, =

IP"L,'

When Canis small, the primary current can also

be reset by discharging Cbl and charging Cbzvia D, during
Interval 4 to achieve ZCS. In Fig. 5 , the vABvoltage does
not have voltage blocking from CbO. The amplitude of
primary current will be decreased. Therefore, while the
converter is starting, it can lie used for soft-start.
Additionally, when the frequency changes to a higher
valne than the normal frequency, the amplitude of the
primary current will also decrease. In this case, it can be
soft-started as well. However, the effect from this case
makes the phase lag between the primaly current ip and
primary voltage vAB. Also, the effect cannot reset the
primary current to reach zero for a while. Therefore, the
valne of C b O should be optimally designed.

(IO)

"a",

Vcbopis the peak blocking voltage determined as follows:

From (IO) and (I I), TESt is inversely proportional to

the duty cycle. To minimize Treset, the duty cycle should
be maximized, and the leakage inductor sbonld be
minimized. The blocking capacitor cannot be reduced
without limitations because its peak voltage is increased.
During TZcs, the leakage inductor maintains the primary
current at zero, so the required volt-second balance for the
leakage inductor($,k) is given by:

For this condition, the volt-second balance should be

very small, meaning that the leakage inductor should also
be very small, so the leakage inductance of the transformer
should be reduced by making the duty cycle loss negligible.

Fig. 5 The effect of a small value for CbO.

V. Experimental Results

To verify the operatiorial principles and steadystate characteristics of the proposed switching converter,
PSpice simulation results and experimental results will be
shown in Fig.6-12. The experimants will be carried out on
a I kW (Vo = 42 V, Io = 24 A) 30 kHz switching converter
prototype to illustrate the feasibility of the proposed ideas.
The circuit parameters in Table I are as follows (see Fig.1):

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Table.1: Circuit Parameters.

Model

Model

IRFP460

IRG4PH40U

IRG4BC3OU

30ETH06

UFB120FA40

16CTU04

410pF

1 PF

1 PF

0.1 pF

4700 pF

1000 pF

EE80 3:l

ETD49 9:l

the leakage

30 pH

inductance of

IC2

the transformer

1.76 C2

IO pH

".

..
.I_

Fig. 6 secondary voltage without active snubber

(experiment).

Fig. 7 secondary voltage with active snubber (experiment).

.-

Fig. IO Output voltage and current waveforms at

primary side with active snubber when Cbo is small
(Pspice).

Fig. I 1 Output voltage (top) and current (center)

waveforms at primary side with active snubber when Cbo
is small (experiment).

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spike voltage. The dead times in the lagging and leading

legs should be identical in order to obtain safety time
margin and make phaseshifted control simpler. Finally,
the active snubber on the seconcky side minimized voltage
ringing due to the diode reverfse currents and allowed to
suppon another output voltage ( 5 Vdc in this case).

References

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J.G. Cho, J.W. Baek, C:Y. Jeong, and G.H. Rim,

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Fig. 12 ZVS for switch SI
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When Fig. 6 and Fig.7 are compared, Fig.7 showing
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[3] S. Hamada and M. Nakaoka, A novel zero-voltage
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those in Figs. 8 and 10 because the simulation did not
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converter with reduced (:onduction losses, IEEE
Transactions on Power Eiecrronics, 2002, pp. 413in wires. Fig. 12 shows ZVS of switch S5 in active snubber
419.
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voltage and zero-current-switching full- bridge
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zero-current-switching PWM full-bridge converter
using two diodes in series with the lagging leg,
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~ ~ . . ~ ~ . _ ~ ~ [6]
~ J:A.
_
. ~
~ ~
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. ~
Sabat6,
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R.B.
F.C.~
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and . .
.~...~._.~~_..~~
.~~
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~_._
_..
B.H..Cho,
Design
for~
high-.
- - l ..--.I.
~~-. L -.
II ~ . . - A - .
voltage
high-power
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I6
20
25
1s
OlPYl
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The prototype can be tested at 42 V,
I kW output and 5
considerations, and experimental results at 1.5 kW,
V,, IO W output. Furthermore, the converter can obtain
100 kHz, Proceedings of the IEEE Power
92 % efficiency at rated power shown in Fig. 13.
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voltage and zero-current-switching full bridge
PWM converter for high power applications,
The improved ZVZCS FB-PWM converter employed
Proceedings of the IEEE Power Electronics
three blocking capacitors for resetting the primary current:
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one on the primary side and two on the secondary side.
[9] R. Liu, Comparaive study of snubber circuits of dc-dc
Soft-starting of the converter was possible using the two
converters utilized in high power off-line power
blocking capacitors on the secondag side. Another
supply applications, Proceedings of the IEEE
advantages of this converter were equal dead times for
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Exposition, 1999, pp. 821-826.
capacitors in the leading leg (as compared to IGBTs used in
the lagging leg) to minimize the tailing current effect and
~~

--$-

rYn.,

1690

~ _ ~ .