IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO.

12, DECEMBER 2009

4915

Efficient FPGA Realization of CORDIC With

Application to Robotic Exploration
Leena Vachhani, Student Member, IEEE, K. Sridharan, Senior Member, IEEE, and
Pramod Kumar Meher, Senior Member, IEEE

AbstractWe present an area-efficient method and fieldprogrammable gate array (FPGA) realization for two common
operations in robotics, namely, the following: 1) rotating a vector
in 2-D and 2) aligning a vector in the plane with a specific axis. It
is based on a new coordinate rotation digital computer (CORDIC)
algorithm that is designed to work with a small set of elementary
angles. Unlike conventional CORDIC, the proposed algorithm
does not require a ROM and a full-fledged barrel shifter. The
proposed CORDIC algorithm is used to design hardware-efficient
solutions for two mobile robotic tasks in an indoor environment
without employing division and floating-point calculations. Experiments with a sole low-end FPGA-based robot in static as well as
dynamic environments validate the power of the approach.
Index TermsArea-efficient algorithm, coordinate rotation digital computer (CORDIC), field-programmable gate array (FPGA)
implementation, robotic exploration.

I. I NTRODUCTION

EDICATED and reconfigurable hardware-directed solutions are of tremendous interest in robotics for a variety
of reasons. For online computations, speed is paramount. There
are also scenarios where area- and power-efficient solutions are
valuable. These include robots in hospitals and home automation systems that are battery-driven and can accommodate only
a small payload. Hardware-based solutions also have an impact
on the size and cost of the overall system. Our interest is broadly
in field-programmable gate array (FPGA)-based solutions for
robotic exploration of indoor environments.
This paper considers a core element of many robotic algorithms, namely, the rotation of vectors in a plane (and update
of coordinates for a reference point on a mobile robot) and
develops an area-efficient hardware-directed solution. A classic
algorithm for handling rotations is based on the coordinate
rotation digital computer (CORDIC) [1]. The CORDIC is a
shift-and-add technique for computing a large class of mathematical functions in a hardware. CORDIC-related research has
focused on speed and accuracy improvement [2][4]. There are

Manuscript received December 23, 2007; revised June 15, 2009. First
published June 30, 2009; current version published November 6, 2009.
L. Vachhani is with the Indian Institute of Information Technology,
Design and Manufacturing Kancheepuram, Chennai 600036, India (e-mail:
leena@iiitdm.ac.in).
K. Sridharan is with the Electrical Engineering Department, Indian Institute
of Technology Madras, Chennai 600036, India (e-mail: sridhara@iitm.ac.in).
P. K. Meher is with the Institute for Infocomm Research, Singapore 138632
(e-mail: pkmeher@i2r.a-star.edu.sg).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2009.2026225

several applications that employ CORDIC. A very large scale

integration processor for collision detection is proposed in [5].
Development of a fuzzy-logic controller on an FPGA using the
CORDIC algorithm has been reported in [6].
Considerable research has also been done on development
of FPGA-based adaptive control strategies for motor control
and other applications. A review of the state of the art of
FPGA design methodologies with focus on industrial controlsystem applications is presented in [7]. Rodriguez-Andina et al.
[8] present a detailed discussion of advanced features, design
tools, and application domains for FPGAs. An implementation
of a bilateral control system using FPGA for an endoscopicsurgery robot is described in [9]. An embedded digital-signalprocessor-based fuzzy controller for autonomous mobile robots
is presented in [10]. An intelligent recharging system for a
mobile robot with focus on power aspects is presented in [11],
while a fast robot-motion-generation scheme has been proposed
in [12] with the objective of reducing power consumption.
Some CORDIC designs have been evaluated on FPGAs [13],
[14]; however, very little is known on area-efficient designs.
The contributions of this paper are as follows. An areaefficient solution to CORDIC is proposed with the number of
iterations required (in the worst case) that is less than the word
size (12 b here) and with an angular resolution of 1 . The
proposed method works in rotation as well as vectoring modes
and, further, rotation angles need not be known in advance.
Another feature of the proposed work is that it covers the
entire range of angles (required in robotic applications) instead
of the restricted range of [99.7 , 99.7 ] for the conventional
CORDIC. Moreover, the proposed solution uses a substantially
lower percentage of FPGA components than other existing
implementations [14].
Another contribution of this paper is on addressing challenges in performing high-level tasks when a robot is equipped
with a sole low-end FPGA (and has no external memory or
dedicated peripheral interfaces). We show how the CORDIC
approach facilitates a hardware-efficient solution for two highlevel tasks, namely, generalized Voronoi diagram (GVD) construction and wall following, without the need for operations
such as division and floating-point calculations that are not
amenable for digital hardware. The power of the CORDICbased approach is further demonstrated by an extension to
GVD construction in a dynamic environment. The proposed
hardware-efficient approaches are validated through experiments on a sole low-end FPGA-based mobile robot.
The remainder of this paper is organized as follows.
Section II examines the area requirements of conventional

0278-0046/$26.00 2009 IEEE

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 12, DECEMBER 2009

A. Issues in Conventional CORDIC

Fig. 1. Word-serial architecture of conventional CORDIC.

CORDIC and identifies the need to develop the new

algorithm. Section III presents the proposed algorithm and architecture along with the FPGA implementation results. Comparisons with some prior CORDIC designs are also presented.
Section IV presents the applications of the new CORDIC.
Conclusions are presented in Section V.
II. C ONVENTIONAL CORDIC AND A REA C ONSUMPTION
The CORDIC algorithm provides an iterative method of
vector rotations by predefined angles using only shift and add
operations. The iterative rotations of a vector are expressed by
Xi+1 = Ki (Xi Yi di 2i )
Yi+1 = Ki (Yi + Xi di 2i )
Zi+1 = Zi di tan1 (2i )

(1)



Ki = cos tan1 (2i )

(2)

where

Ki is a scale factor
can be accumulated. The vector is
 that
scaled by Kn = n (1/ 1 + 22i ).
The CORDIC rotator can work in two modes, namely, rotation and vectoring. In the rotation mode, the angle accumulator
is initialized with the desired angle denoted by Z0 . At each
iteration, the direction of rotation (counterclockwise/clockwise)
denoted by di is given by

+1, if Zi 0
di =
1, otherwise.
The vectoring mode accumulates the angles needed to rotate
a given vector (X0 , Y0 ) for minimizing Yi . The value of Z0 is
initialized to zero in vectoring mode.
A word-serial architecture for the conventional CORDIC is
shown in Fig. 1. The barrel shifters are implemented using
multiplexers whose inputs are wired values that are shifted right
by different amounts. The sel line selects the correct shifted
input. The input mode selects the mode of operation (a mode
of zero indicates rotation mode, while a mode of one indicates
vectoring mode). Section II-A discusses the issues that arise in
implementation of the conventional CORDIC algorithm.

1) Range of angles: The conventional CORDIC handles

angles in a [99.7 , 99.7 ] range. To cover the entire
range of angles, the angles have to be converted into
the CORDIC domain, and this accounts for extra multiplexers in the design. While other solutions have been
proposed for handling the extended range, there are some
difficulties with respect to design of an area-efficient solution. For example, [3] defines domains of size 180 /8.The
entire [0 , 360 ] range is folded to the [0 , 180 /8] range;
doing so allows for scaling-free CORDIC operations.
However, the folding itself requires extra multiplexers.
2) Area consumption: The size of the ROM in Fig. 1 is
proportional to 2log2 (no. of iterations) since it is directly
related to the number of address lines. Further, the barrelshifter size has an exponential dependence on the logarithm of the number of iterations.
III. P ROPOSED A LGORITHM AND A RCHITECTURE
A. Overview
In many mobile-robotic applications, there is a need to
handle the complete range of angles, namely, [180 , 180 ),
since the robot may have to rotate by any angle and advance
appropriately to reach a specific location in space. Also, an
accuracy of one degree would be adequate. It turns out that for
this accuracy and range of angles, the elements needed for a
conventional CORDIC implementation, particularly the ROM
and a full-fledged barrel shifter (which permits a large number
of shifts), consume considerable FPGA resources.
Our approach is directed toward minimizing resource
consumption on an FPGA by the rotation as well as
the vectoring module. The proposed algorithm (named as
AREA_EFFICIENT_CORDIC) avoids a large barrel shifter
and a ROM. This is accomplished by a design that does not
use the same set of angles, namely, tan1 (2j ), j = 0, 1, 2, . . .,
as the conventional CORDIC algorithm. Further, the complete
range of angles is handled directly (without approaching it
as an extension of the [99.7 , 99.7 ] range), and this allows
reduction in the complexity of multiplexers in comparison with
conventional CORDIC [extended to [180 , 180 )].
In particular, in AREA_EFFICIENT_CORDIC, we choose
a small set of angles for which area efficiency is achieved,
while the desired performance (in terms of number of iterations
required to converge with 1 accuracy) is also obtained. The set
of angles chosen is {tan1 21 , tan1 23 , (tan1 (23 )/2k )
for 1 k 3}. The manner in which these five angles are used
is presented next. The architecture is based on multiplexers of
small size (four to one, in particular), and this contributes to
considerable savings in FPGA implementation.
We assume that the desired rotation angle z is in the range
[180 , 180 ). Rotation by angles less than tan1 23 does
not contribute significantly to the CORDIC correction constant
Kn . Also, tan1 (2j ) is almost linear for j 3 and can be
expressed as follows [15]:
tan1 (2j ) 2j ,

for large values of j.

(3)

VACHHANI et al.: EFFICIENT FPGA REALIZATION OF CORDIC WITH APPLICATION TO EXPLORATION

In AREA_EFFICIENT_CORDIC, the rotation (at each

stage) is valid only if it does not change the sign of the angle z.
For example, if the angle z is positive, the rotation is valid
only if the angle after rotation is also positive. In particular,
rotations in only one (starting) direction are permitted. The
process begins with a sequence of rotations of tan1 (21 ).
The first invalid rotation of tan1 (21 ) is the starting point
of sequence of rotations of tan1 (23 ). Further, the first invalid rotation of tan1 (23 ) starts the sequence of rotations
of tan1 (23 )/2k for 1 k 3. It is worth noting that each
rotation in [(tan1 (23 )/2k ) for 1 k 3] is used at most
once. Finally, the angle z 0. The algorithm stops if z < 
(where  is a small positive constant), or k = 3.
The iterative equations for AREA_EFFICIENT_CORDIC
are given by
Xi+1 = Kj (Xi + di 2j Yi )
j

Yi+1 = Kj (Yi di 2

Xi )

Zi+1 = Zi + di tan1 (2j )

(4)
(5)
(6)

where



d0 , if sgn Zi + d0 tan1 (2j ) = sgn(Zi )

for rotation mode and

di =
(sgn(Yi d0 2j Xi ) = sgn(Yi )

for vectoring mode

0, otherwise
d0 {1, 1} and j {1, 3, 4, 5, 6}.
To start the iterative process given by (4)(6), X0 and Y0 can
be taken to be one and zero, respectively, in the rotation mode,
while Z0 is the desired angle of rotation. The implementation
of the iterative equation for Zi+1 uses the relationship


tan1 (2j ) = 21 tan1 2(j1)
for large values of j. The scale factor Kj is given by
(1/ 1 + 22 ) = 0.8944 for j = 1. Further, for j 3, we have
1 > Kj 0.992, and, therefore, scaling for rotations less than
(or equal to) tan1 23 is ignored. The exact value of Kj does
not have a bearing on the rotation accuracy (of 1 ).
In the vectoring mode, given (Xin , Yin ), multiple clockwise
rotations of tan1 21 are effected if (Xin , Yin ) happens to be
in the second quadrant (equivalently, multiple counterclockwise
tan1 21 rotations if (Xin , Yin ) is in the third quadrant). This
may be followed by multiple rotations of tan1 23 and smaller
angle rotations. Termination is determined by the magnitude of
the second coordinate (in particular, when all but the least two
significant bits become zero).
Remark 1: Wang and Swartzlander [16] present a critically
damped CORDIC algorithm which uses microrotations in one
direction. However, the scheme in [16] uses a ROM, and,
further, ours does not require an explicit multiplier. More details
are presented in the architecture section.
Remark 2: The use of tan1 21 along with an angle larger
than tan1 23 brings in the need of hardware for an additional
scaler. Further, the barrel shifter will no longer have low width.

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Remark 3: Unlike the conventional CORDIC with fixed

number of iterations where the scale factor K accumulated over
several iterations is known beforehand, the number of iterations
is variable in the proposed algorithm and is dependent on the
input angle. As a consequence, the scale factor, denoted here
by K1 , needs to be handled in each iteration with K1 being
0.8944. Its realization is discussed in the architecture section.
Lemma 1: AREA_EFFICIENT_CORDIC converges in a finite number of iterations for rotation as well as vectoring mode.
Proof: The iterations required are finite for the rotation
mode as a consequence of the following: 1) Rotation happens
only in one direction at each stage, and 2) an angle of smaller
magnitude is chosen whenever the difference between the accumulated angle and the desired angle of rotation is more than
the initial angle (of large magnitude).
For the vectoring mode, the convergence is straightforward
to establish when the vector (Xin , Yin ) is in the first or fourth
quadrants. While a vector is rotated from second/third quadrant
(to align with positive X-axis), the magnitude of Y does not
monotonically decrease. However, there is at most one maximum for |Y |. This ensures the convergence in a finite number
of iterations.

We now show that in the range [0, 180 ], at most ten
iterations are required to arrive within 1 given any input angle.
The proof for [0 , 180 ] is omitted since the arguments for the
former can be used for the latter with merely a change of sign
for the elementary angles.
Lemma 2: Using AREA_EFFICIENT_CORDIC, for a 12-b
representation, if m1 denotes the number of iterations of
tan1 21 , m3 denotes the number of iterations of tan1 23 ,
and nk denotes the number of iterations of tan1 (23 )/2k for
1 k 3, then

max m1 + m3 +


nk

10

k=1

to converge within 1 for any input angle in the range [0, 180 ].
Proof: In a 12-b representation, 9 b are required for the
integer part to represent all angles in [180 , 180 ), so, we
obtain 3-b approximations for the fractional parts of tan1 21 ,
tan1 23 , tan1 23 /2k , k = 1, 2, 3. The decimal representation in degrees is used for all five angles since it facilitates a
simple proof. The closest representations for the five angles are
26.625 , 7.125 , 3.5 , 1.75 , and 0.875 .
The proof is based on splitting the entire range [0 , 180 ]
into seven parts determined by the representation for tan1 21 .
Suppose we denote the parts by Ri , i = 1, . . . , 7; then it is
clear that the maximum number of iterations (for angles) in
R2 is just one more than the maximum number in R1 (similarly for R3 , R4 , and so on). One can therefore concentrate
on [0 , 26.625 ]. In [0 , 26.625 ], the angles that require
the maximum number of iterations (5) are 21 and 26 (this
has been determined by hand calculations for all angles in
this subrange). In particular, 21 can be expressed as (2
7.125) + 3.5 + 1.75 + 0.875, while 26 can be expressed as
(3 7.125) + 3.5 + 0.875, given the maximum allowable error
of one degree.

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Given that the maximum number of iterations is five in the

first subrange, it is clear that angles up to 159.75 do not
require in excess of ten iterations (permitting a maximum of
1 error). It is therefore adequate to focus on [159.75 , 180 ].
Reaching any angle in this range requires a minimum of six
iterations. However, the interval [159.75 , 180 ] spans only
20.25 , and, from the discussion earlier, we know that there
does not exist any angle in [0 , 20 ] which requires in excess of
four iterations. Hence, the total number of iterations for angles
in [159.75 , 180 ] does not exceed ten. It turns out that 154
and 180 require ten iterations each.

B. Accuracy Analysis
The accuracy of sine and cosine computations can be analyzed with respect to the following: 1) deviation in computed
value of sin and cos due to permitted angle deviation of 1
and 2) deviation in computed value of sin and cos due to
approximation of scale factor. The approach for error analysis
of the former is similar to the one in [3].
1) Error Due to Difference of 1 in Target Angle: An error
of 1 corresponds to an error of /180 rad. Suppose is the
target angle, then the computed angle is given by ( + /180)
(this applies for negative values of ; for positive values of
, this would be /180). The representation in radians
simplifies error analysis. Since the rotation of a vector [X Y ]T
in the Cartesian coordinate system can be described using
 
  
X
cos() sin() X
=
(7)
sin() cos() Y
Y
we have, for the computed angle
= X cos( + /180) + Y sin( + /180)
X

Y = X sin( + /180) + Y cos( + /180).

(8)
(9)

The error in cosine and sine computations can then be obtained

using (8) and (9) and the computed value of the angle, namely,
( + /180) as given in
Xerror = (X cos + Y sin ) (1 cos(/180))
+ (Y cos X sin ) sin(/180)
(10)
Yerror = (X sin + Y cos ) (1 cos(/180))
(X cos + Y sin ) sin(/180).
(11)
Since [1 cos(/180)] and sin(/180) are 1.52 104 and
0.01745, respectively, the maximum error is approximately 1.7%.
2) Error Due to Approximation of Scale Factor: Using the
iterative equations for the proposed algorithm, namely, (4) and
(5), the error can be obtained for different approximations of
the scale factor. Considering the true K1 and the architectural
approximation, we have, for one iteration
Xi+1
Yi+1
i+1
X
Yi+1

= 0.8944(Xi + di 2j Yi )
= 0.8944(Yi di 2j Xi )
= 0.890625(Xi + di 2j Yi )
= 0.890625(Yi di 2j Xi ).

(12)
(13)
(14)
(15)

Using (12)(15) when Xi = 1, Yi = 1, di = 1, and j = 1,

we have Xerror = 0.0056 and Yerror = 0.0018875 leading to a
maximum error of 0.56%.

The analysis of error due to approximation of K3 is similar

to the one for K1 . The error for one iteration using true and
approximated values of K3 along with Xi = 1, Yi = 1, d = 1,
and j = 3 is as follows: Xerror = 0.86% and Yerror = 0.67%.
Since K1 is approximated on the lower side while K3
and scale factor for smaller angles are approximated on the
higher side, the outcome (in terms of sine and cosine values)
is favorable for angles that are represented as a combination of
tan1 21 and smaller angles.
Remark 4: Maharatna et al. [3] provide a detailed error
analysis and show that the final error due to angle approximation is dependent on the initial values of the vector components
X and Y , as well as on the ideal target angle . They also report
that conventional CORDIC, as well as their method may have
high errors when nonnormalized values of X and Y are used. In
conventional CORDIC, the scaling factor Kn is constant only
for a fixed (large) number of iterations. In the proposed method,
while 154 and 180 require the maximum number of iterations
(namely, ten), these angles are represented by a combination of
rotations of tan1 21 and smaller angles, and, therefore, the
errors in sine and cosine values are small. In particular, for a
rotation by 180 , the error in the cosine computation is roughly
0.79%.
Remark 5: Conventional CORDIC requires n + 1 iterations
for n-bit accuracy (since the iterative equations for X and Y
begin with tan1 20 ) when working in its range. For working
in the extended range, namely [180 , 180 ], multiplexers are
required for domain folding.
Further, for 1 accuracy required in robotics applications,
given an input angle of 100 , seven iterations are required
in conventional CORDIC (and are given by successive rotations of tan1 2i , i = 0, . . . , 6). The proposed CORDIC
algorithm also requires at most seven iterations for the range
of (100 , 100 ), as seen from the proof of Lemma 2.
Conventional CORDIC requires up to six iterations and
provides 5-b accuracy for X and Y (if scaling factor is ignored)
for many angles for convergence within 1 in the [90 , 90 ]
range (examples are 2 , 3 , 9 , 10 , 13 , 14 , 17 ,
20 , 23 , 24 , 30 , and so on). The proposed algorithm
also takes six or fewer iterations for angles in the [90 , 90 ]
range and provides 6-b accuracy for X and Y since the smallest
step is (tan1 23 )/8.
The algorithm in [3] provides 16-b accuracy. Further,
Maharatna et al. indicate that, in the worst case, their method
takes 15 iterations (when the input angle is 21.484 ; the authors
indicate their method takes close to eight iterations for most
other angles).
C. Architecture
The proposed architecture is shown in Fig. 2. The thick
lines show the word operations and the thin lines show the
bit operations unless specified in the figure. All the sequential
elements (shifter, registers, and flip-flops) are driven at the same
clock edge and reset signal.
In the design, mode = 0 is considered for rotation mode,
and mode = 1 for vectoring mode. The multiplexer M0 decides
di , the direction of rotation based on the mode and signs of

VACHHANI et al.: EFFICIENT FPGA REALIZATION OF CORDIC WITH APPLICATION TO EXPLORATION

Fig. 2.

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Architecture for the proposed algorithm.

Yi and Zi inputs. The multiplexer M1 selects the same input

that is used to select di . It selects either Z or Y for the sign
comparison with di . The value of di should not change for
successive iterations, or di should be equal to d0 according to
the algorithm. The output itself decides the direction of rotation
for the next iteration. Therefore, if the direction of rotation
for the next iteration is changing, this iteration is considered
invalid, and di is reset. The comparator output is zero when
the rotation is invalid or one when the rotation is valid. The
comparator output, load, enables the register to store new
iteration values.
The multiplexer M6 and the shifter S0 select the angles corresponding to j = 1, 3, 4, 5, 6. The shifter S0 is initialized with
tan1 (23 ). The shifted values give values of tan1 (23 )/2k ,
k = 1, 2, 3. The corresponding shifted Xi and Yi values are
obtained using fixed-width (barrel) shifters and multiplexers
M2 and M3 , respectively. One fixed-width shifter takes a wireshifted version of Xi , Xi /8 as its data input and shifts it to the
number of positions indicated by the counter output; the other
shifter does the same for Yi .
The scalers in the design can be realized as constant multipliers or shifted adder/subtractors. Since the algorithm needs
1 1
scaling whenever
tan (2 ) rotation is valid, the scaler for
2
scaling of (1/ 1 + 2 ) = 0.8944 1 (1/8) + (1/64) has
been realized by a shifted adder and subtractor.
D. Features of Proposed Design
All the angles in all four quadrants are covered without any
extra hardware. The accuracy of CORDIC correction constant
Kn is maintained. The area requirement is less than half of

that of conventional CORDIC covering all the four quadrants.

The requirement of an eight-to-one multiplexer in original
CORDIC (for handling the extended range directly) is brought
down to a four-to-one multiplexer. The ROM requirement for
storing tan1 values is replaced by a shifter and a two-to-one
multiplexer. Equation (3) is utilized to obtain the shift operation
as follows:


tan1 (2j ) = 21 tan1 2(j1)
as from (3)


tan1 2(j1) 2(j1) .

The remainder of the logic for comparison and multiplexing

is bitwise and consumes very little FPGA resources (exact data
is presented in Section III-F).
E. Area Complexity of Proposed Scheme and Comparisons
The complexity of the proposed algorithm (that is applicable
to rotation as well as vectoring modes) has been compared
with two recent CORDIC algorithms described in [3] and [17],
respectively. Comparisons with a Xilinx core [18] have also
been made.
The algorithm in [3] is designed to eliminate scale factor
compensation and the limited range of convergence of conventional CORDIC. It operates in rotation as well as vectoring
mode. The scheme in [17] is designed for rotation mode and
merges the microrotations and scaling phases in the CORDIC
algorithm. The Xilinx core described in [18] provides modules

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TABLE I
A REA C OMPLEXITY C OMPARISONS

TABLE II
C OMPARISON OF P ERFORMANCE OF D IFFERENT S CHEMES ON FPGA

Fig. 3.

that can operate in one of the two modes (rotation/vectoring).

Further the core can operate in word-serial or parallel mode. We
focus on the vectoring mode and the word-serial architecture.
Magnitude scaling is also taken into account for the Xilinx core.
The results are presented in Table I. The results in Table I are
for the iterative structure in all the designs. If the entire design is
taken into account, [17] indicates 21 adders are required, while
[3] indicates 96 adders are required.
The proposed algorithm also requires one 2-b counter, two
logic shifters (12 b), three XOR gates, and one 1-b comparator.
The scaling-free CORDIC algorithm [3] also requires two logic
shifters and a few comparators. Mixed-scaling rotation (MSR)CORDIC [17] requires, in addition, nine 512-to-1 multiplexers
and six logic shifters. The Xilinx core design uses word-serial
configuration hence there is a one adder-subtractor stage. The
Xilinx core requires, in addition, 32 shift registers. It can be
observed that the proposed algorithm shows significant savings
in combinational as well as sequential logic elements. FPGAdevice specific data are presented in Section III-F.

Plots of slice consumption versus word length in bits.

The algorithms can also be compared using the T A metric

measured in terms of the slice-delay product. As shown in
Table II, the proposed algorithm is very efficient and has the
least T A product of 2.511 (among the four methods). The
designs can also be compared in terms of the latency estimated
as the product of the number of iterations and the time for each
iteration. Considering the common range of [90 , 90 ] handled by all the algorithms, we note that the proposed method has
a latency of 0.108 s, while [3], [17], and [18] have a latency
of 0.148, 0.052, and 0.102 s, respectively. To substantiate the
advantages of the proposed CORDIC algorithm, plots of slice
consumption versus word length have been obtained for various
algorithms. The plots are shown in Fig. 3. The plots indicate
significant savings in slices for the proposed algorithm and also
indicate only a modest increase in the number of slices as the
word length grows.
IV. A PPLICATIONS OF P ROPOSED CORDIC

F. FPGA Implementation and Comparisons

The proposed algorithm has been coded in Verilog 2001
and implemented on a low-cost Xilinx Spartan XC2S200EPQ208-6 device. Xilinx ISE 9.2i has been used for synthesis.
The Xilinx XC2S200E device has a regular, flexible, and programmable architecture of 28 42 configurable logic blocks
(CLBs). Each CLB has two slices, and each slice has two
lookup tables (LUTs). The device has a total of 2352 slices,
4704 four-input LUTs, and 14 block RAMs (BRAMs) each
of size 4 kB. The details of slice consumption, frequency, and
slice-delay product for the full range of angles for the following: 1) the proposed algorithm; 2) the scaling-free CORDIC
scheme in [3]; 3) the MSR-CORDIC scheme in [17]; and
4) the Xilinx CORDIC core, are given in Table II.
The data given in Table II are for a 12-b word size since
the robotic applications use 12 b. From Table II, we can infer
that the proposed algorithm has high performance and saves
considerable area. In comparison with the requirements of
Xilinx core and other algorithms implemented (by us in Verilog
and synthesized for the same device), it saves roughly 50% area.

A challenge in mobile robotics is that of performing highlevel tasks when constraints are imposed on the processing component. In this section, we consider a mobile robot
equipped with a sole low-end FPGA for processing. We assume
that there is no external memory and no elaborate peripheral
interfaces so that the cost, area, and energy consumption are
small.
Hardware-efficient solutions based on the new CORDIC
algorithm are presented for: 1) construction of the generalized
Voronoi diagram (GVD) and 2) wall following. While GVD is
chosen in view of large memory requirements, wall following
presents a different type of trajectory for the robot to achieve.
Extensions to a dynamic environment are also presented. While
prior algorithms and implementations exist for Voronoi construction [19], these are limited to static environments for
implementation using general-purpose microprocessors.
A. Construction of GVD
The GVD is the locus of points which are equidistant from
two or more obstacle boundaries including the workspace

VACHHANI et al.: EFFICIENT FPGA REALIZATION OF CORDIC WITH APPLICATION TO EXPLORATION

Fig. 4.

4921

Three objects and the GVD.

Fig. 6. Direction of edges at node.

(x1 , y1 ) and (x2 , y2 ). Then, the nearest point from the origin
on the perpendicular bisector to the line joining (x1 , y1 ) and
(x2 , y2 ) is

Fig. 5.

Rectification using perpendicular to perpendicular bisector point.

boundary. The GVD serves as a good map in indoor environments. The GVD consists of Voronoi edges and meet points. A
Voronoi edge is the locus of points equidistant to two nearby
obstacles, while a meet point is equidistant to three or more
obstacles. A meet point determines termination of one edge
and start of another for the robot to explore. An environment
with three obstacles and its GVD (shown by dashed lines) is
presented in Fig. 4. The stretch from V1 to V2 is part of a
Voronoi edge.
For construction of a Voronoi edge by an FPGA, estimation
of the next point on the edge is performed in a hardwareefficient manner. The estimation is followed by rectification
using the distance values provided by the sensors. Consider
Fig. 4. V2 is the present location of the robot. The estimation
of next point Vest is based on the observation that V2 is the
midpoint of V1 and Vest . This is accomplished merely by shift
and subtract operations.
Since an estimated point may not necessarily be on the GVD,
two nearest points on distinct nearby obstacles (A and B)
are identified (based on sensor inputs), and these are used to
confirm an estimated point as being on the GVD or otherwise.
In the latter case, a rectified Voronoi point (denoted by V3
in Fig. 4) is obtained using the proposed CORDIC without
division operations.
The perpendicular bisector to the line joining closest points
on A and B is used to perform the rectification. The closest
point on the perpendicular bisector to the current point is
obtained as shown in Fig. 5.
The computation of the direction and the distance for the
robot to move for reaching the rectified point is based on
the following ideas. For ease of discussion, let the present
position of (a reference point on) the robot be the origin and
its heading direction be the positive X-axis. Further, let the
coordinates of nearest points on two different obstacles be

xp =

y22 y12 + x22 x21

(x2 x1 )

(y2 y1 )2 + (x2 x1 )2
2

yp =

y22 y12 + x22 x21

(y2 y1 )
.

(y2 y1 )2 + (x2 x1 )2
2

(16)

To facilitate hardware-efficient realization, (16) can be

rewritten as

 x1 +x2 

xp
 2 
yp = J L M N y1 +y2
(17)
2
1
1
where

1 0
J = 0 1
0 0

cos
L = sin
0

1 0
M = 0 1
0 0

x1 +x2
2
y1 +y2
2

1
sin
cos
0

0
0
1

cos

x1 +x2
2

+ sin
0
1

y1 +y2
2

N = (L1 )
where
1

= tan

y1 y2
x1 x2


.

The details of the architecture are presented in

Section IV-A1. The identification of meet points is based
on the following ideas.
Small steps are taken while moving toward the estimated next
point on an unexplored Voronoi edge, whereas, while moving
on an explored edge, the robot takes a direct (bigger) step. For
starting exploration of a new edge at a meet point, the midpoint
of the nearest points on two distinct nearby obstacles gives
the direction for the estimated next point on the new edge, as
shown in Fig. 6. If one of the midpoints is the meet point under
consideration, as shown in Fig. 7, the mirror image of the third

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 12, DECEMBER 2009

Fig. 7. Direction of edges at node when two closest points are at 180 .

closest point (point P here) gives the estimated point on the

third edge.
All the valid Voronoi points on the explored Voronoi edge are
pushed onto a stack. Whenever a new meet point is detected,
extra points corresponding to unexplored Voronoi edges are
pushed onto the stack along with a flag node. Points are popped
out of the stack when a boundary is reached. Each element of
the stack contains the (x, y) coordinates of the present point,
information on whether it is a node, and the coordinates of
unexplored edge(s). While backtracking (following an already
explored edge in the reverse direction), if the popped contents
have its node flag set, then the robot starts exploring the
unexplored edge in the forward direction. If in the exploration
process, a node is traversed again by making a round trip,
then its entry in the stack is changed with the coordinates
of unexplored as zero, so that when it is popped out while
backtracking, it does not explore this edge again.
An exploration trace for a T-shaped environment is shown in
Fig. 8. The actual GVD is shown in dashed lines. The robot
starts at the point marked as 1 and performs exploration as
shown.
The architectural elements for obtaining the meet points as
well as points on Voronoi edges are presented next.
1) CORDIC-Based Architecture for GVD: Fig. 9 shows the
overall architecture. The pulsewidth to distance-converter module produces a 10-b distance value taking input from each
ultrasonic sensor. The minimum-distance finder returns four
(minimum) distance values and the corresponding sensor IDs.
The content addressable memory module is used to store node
coordinates. Details of modules that explicitly use CORDIC
and are relevant for the dynamic case are presented next.
CORDIC-based rectification circuit: The realization of
(16) in hardware as such is not desirable since the equations
contain several multiplications and a division. The distance and
direction (for the robot) to reach the rectified point are obtained
using CORDIC in vectoring and rotation modes in this module.
The input consists of two minimum distance values and their
directions. The first step consists of finding points A(x1 , y1 )
and B(x2 , y2 ) in Fig. 5 using two minimum-distance values
(d1 , d2 ) and their corresponding sensor directions [namely,
(1 ) and (2 )]. This is accomplished by CORDIC in rotation
mode. The second step consists of finding the angle (denoted
by ) of line AB (in Fig. 5) with the X-axis. This involves
use of CORDIC in vectoring mode. The third step involves
translating the origin to [(x1 + x2 /2), (y1 + y2 /2)]. The new

coordinates (for computation, does not require robot movement) are [(x1 + x2 /2), (y1 + y2 /2)].
The rotations corresponding to matrices N and L in (17) are
accomplished using CORDIC. The translation component in M
does not require any multipliers since the extent to translate is
known after the rotation by corresponding to the matrix N .
Using the coordinates of rectified point, the distance and the
direction for the robot to reach this rectified point are also found
using CORDIC (in vectoring mode).
Estimation circuit: This module calculates the estimation
point using a shifter and a subtractor as shown in Fig. 10.
Midpoint generation logic: This module facilitates calculation of midpoints. The architecture is shown in Fig. 11.
Information about sensor IDs is used here: Starting from the
front sensor, the sensors are given unique IDs from zero to
seven in increasing order in the counterclockwise direction. In
Fig. 11, the variable mina corresponds to the sensor ID of ath
minimum-distance value (the arguments 2, 1, and 0 refer to the
MSB, middle bit, and LSB, respectively). a and b can be 1, 2,
3, or 4, but a = b. The variable oppositeab is set if mina and
minb are opposite to each other (for example, if min1 = 1 and
min2 = 5, then opposite12 is set to 1). Pa is the closest point on
the nearest obstacle (in the direction of mina ), while Pcurr is the
current position of the robot. Pmidab corresponds to a point on
the edges emanating from a node (If, for example, Pa , Pb , and
Pcurr are not in a straight line and, therefore, oppositeab is 0, it
is assigned as the midpoint of Pa and Pb , else it is assigned as
the mirror image of cth nearest point Pc over the current point
Pcurr ). The comparator and MUX block selects valid points on
each edge with Pmid1 corresponding to the edge from where the
node of interest is reached.
Motor control logic: The coordinates of next point are
converted into distance and direction using the CORDIC unit
in vectoring mode. The robot is first aligned with this direction
by calculating the turning angle with respect to the present
direction of the robot. Then the robot is moved by distance
centimeters. The control logic to drive the motors of the robot
counts the number of steps the motor should receive in order
to rotate by angle or translate by distance centimeters. The
logic drives two 2-phase bipolar stepper motors. These two
(termed as left and right) stepper motors of 1.8 /step are
connected through L297L298 controller-driver pairs to the
respective wheels. The translation movement of 1 cm requires
approximately 30 steps, while rotation by 1 needs seven steps.
The architecture to drive the motors is shown in Fig. 12. The
multiplication by 30 or 7 in the step calculation is achieved
by a subtractor and multiplexers. The multiplication by powers
of two is performed by wiring the shifted values. The down
counter counts the number of steps given to the stepper motor. The stepper-motor driver gets a clock input (denoted by
step_clk) via clock division of the 50-MHz signal on the FPGA
board.
2) FPGA Usage: The usage of the XC2S200E FPGA for
each module in the architecture is shown in Table III. It can be
observed that CORDIC-based rectification consumes roughly
one-third of the FPGA resources (in view of conversion of
(d1 , 1 ) to (x1 , y1 ), . . . , (d4 , 4 ) to (x4 , y4 ), and finally, conversion of rectangular coordinates of the next point to polar

VACHHANI et al.: EFFICIENT FPGA REALIZATION OF CORDIC WITH APPLICATION TO EXPLORATION

Fig. 8.

Illustration of an exploration trace.

Fig. 9.

CORDIC-based architecture for GVD.

Fig. 10. Estimation circuit.

coordinates). The proposed area-efficient CORDIC algorithm is

therefore valuable to accommodate the entire design in a lowend FPGA device.

4923

3) Experimental Results: The snapshots of an experiment

on GVD construction performed in a 5-m 4-m environment
are shown in Fig. 13(a)(d). The time to converge to the GVD is
only on the order of a few seconds. Each rectification step takes
at most 4.05 s. This includes collection of sensor data (0.32 s),
computations (requiring microseconds), and wheel movements
(taking a maximum of 3.73 s). For the chosen ST EP _SIZE
of 10 cm, the maximum rectification step of 10 cm would
be required. Hence, the robot can converge to the GVD in a
maximum of 4.05 s.

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 12, DECEMBER 2009

Fig. 11. Midpoint generation logic.

Fig. 12. Motor-control architecture.

TABLE III
X ILINX XC2S200E D EVICE U SAGE FOR M ODULES
IN CORDIC-BASED A RCHITECTURE

Fig. 13. Snapshots for the experiment on GVD construction. (a) Starting
point. (b) Estimated point (on the GVD). (c) Next estimated point (off the
GVD). (d) Rectified point.

Fig. 14 shows the experimental and ideal trajectories for

an environment having three obstacles C1 , C2 , and C3 . The
environment is the same as the one for which the snapshots are
presented earlier. The ideal trajectory is shown in solid lines,
whereas the experimental one is shown in dashed lines. The
dots on the experimental trajectory are points on the GVD.
The point a in the experimental trajectory corresponds to the
snapshot shown in Fig. 13(a). Similarly, point b corresponds
to Fig. 13(b) and point c to Fig. 13(d). The error between the

VACHHANI et al.: EFFICIENT FPGA REALIZATION OF CORDIC WITH APPLICATION TO EXPLORATION

Fig. 14. Solid lines: Ideal trajectory; Dashed lines: Experimental trajectory.

Fig. 15. Plot of the error between ideal and experimental trajectories.

ideal and experimental trajectories is plotted for the segment of

GVD, as shown in Fig. 15. It may be noted that the error after
the robot makes a correction (when it is off the GVD) is quite
small and is on the order of a few centimeters.
4) GVD Construction in Dynamic Environment: Hardwareefficient GVD construction in a dynamic environment presents
fresh challenges particularly when multiple objects move simultaneously in the vicinity of the robot. We consider an
environment consisting of humans moving simultaneously between specific blocks as shown in Fig. 22. The new CORDICbased approach facilitates a solution for the dynamic case as
well without use of external memory and at the same time
avoiding division and floating-point operations. The key idea
is capturing the dynamic activity accurately by processing data
from multiple ultrasonic sensors in parallel.
The GVD in a dynamic environment of the type outlined is
a subset of the one for an environment with merely the static
blocks, therefore, the design of circuits involves prediction of

4925

Fig. 16. Circuit for removal of an edge.

branches at nodes in advance. The robot explores the environment just once in the dynamic case as well. Branches declared
as occupied by a dynamic obstacle need to be pruned. The
robot waits at each node for a prespecified time (determined by
the sensor range and nominal object speeds). Multiple readings
are taken from each sensor to ascertain the direction of object
movement (based on variations in sensor values).
Modules for dynamic environment: In addition to the
modules for a purely static environment, the architecture for a
dynamic environment has modules to detect the movement and
appropriately adjust the properties of a node. The estimation
circuit requires some changes as well. Data on edges to be
removed is obtained using the architecture shown in Fig. 16.
In essence, sensor information is used to determine edges to be
eliminated. The circuit shown in Fig. 16 outputs the number
of edges to be removed in the case of a node with four edges
in adder4 and in the case of a node with three edges in
adder3 . opposite12 signifies if the sensors corresponding to
two minimum distance values (min1 and min2 ) are 180 apart
(opposite12 bit is one if two minimum sensor readings are
resulting from sensor IDs zero and four). If sensor IDs lying
between min1 and min2 are detecting movement, a flag named
move_btn12 is set.
Removal of edges implies a change in the properties of a
node. The circuit shown in Fig. 17 takes the value of adder4
to transform a node with four branches to one of the following:
node (three branches), boundary point, or a normal point on the
GVD (with just two equidistant objects). Similarly, a node with
three branches is converted using adder3 .
Using adder3 and adder4 , the properties of a node are
changed as shown in Fig. 17. In particular, the value of
dyn_node is used to determine if a node currently having
four branches should become merely a node (three branches).
Similarly, the value of dyn_boundary determines if the present
node should be converted to a boundary point. Conversion to a
normal point on the GVD (two equidistant objects) takes place
if all the three flags (dyn_node4, dyn_node, dyn_boundary) are
reset.

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 12, DECEMBER 2009

Fig. 21.

Moving back on the same edge.

Fig. 17. Circuit for conversion of a node.

Fig. 18. Coming to a node from an edge.

Fig. 22. Environment where humans simultaneously move along west, north,
and east of the robot located at node 4.

Fig. 19. In the vicinity of a node.

Fig. 23.

Fig. 20. Checking for dynamic activity at a node.

Experiments: Figs. 1821 shows the snapshots of an experiment performed in a 5-m 6-m environment with three
persons moving between three pairs of stations. Fig. 18 shows
the robot coming along an edge. The robot is very close to a
node as shown in Fig. 19. In the position shown in Fig. 20, the
robot takes multiple sensor readings to identify any movements

Different sensor readings when robot is misaligned with the wall.

along the unexplored edges. Since it detects movement along all

the three unexplored edges, it considers the node as boundary
and returns back to follow the same edge, as shown in Fig. 21.
Fig. 22 shows the analysis of the snapshots. When the robot
is at the node, the modules on the FPGA operating in parallel
determine three simultaneously moving humans, along east,
west, and north, respectively, by input of data from sensors
pointing along node 5, 8, and 11. Consequently, the edges at
node 4 in the direction of nodes 5, 8, and 11 are eliminated.
Since these three nodes are unreachable, boundary nodes 6, 7,
9, 10, 12, and 13 are also unreachable. Node 4 is considered as a
boundary node on the GVD, and the FPGA-based robot returns
back in the direction of the edge from which it reached node 4.

VACHHANI et al.: EFFICIENT FPGA REALIZATION OF CORDIC WITH APPLICATION TO EXPLORATION

4927

Fig. 24. Wall-following architecture using CORDIC.

The robot therefore successfully detects dynamic activity without external memory/buffer support.
The additional FPGA usage for the dynamic case is 744
(15.81%) LUTs and 438 (18.62%) slices. This considers the
edge removal, node conversion, changes in midpoint generation, and checking movement to update adder3 and adder4 .
B. Wall Following by FPGA-Based Robot
In this section, we present a second application of the areaefficient CORDIC. The application involves following a wall
by the FPGA-based robot. The problem of wall following is
a special case of boundary-following problems. The robot can
perform this task using touch sensors; however, the disadvantage is that the robot will then come into contact with the
obstacle/wall. Distance sensors are appropriate here, and the
robot maintains a predefined (constant) distance from the wall.
The trajectory followed is called as the offset path. Clearly,
the offset path is parallel to the wall. The offset path can be
constructed once the correct tangent direction to the wall or
normal to this tangent is known. The sensor is required to
provide information on this normal distance and direction with
respect to the present heading direction of the robot.
While considerable work has been done on wall following
in general, our interest is in hardware-efficient robotic wall
following, and an important element of the wall-following
solution is the CORDIC module. The scheme developed here
finds the exact normal direction to align the robot parallel to
the wall at the offset distance using information from adjacent
ultrasonic sensors placed far apart to avoid crosstalk. The core
is an alignment scheme presented next.
The position of the sensor that gives the minimum-distance
value can be used to determine the approximate direction of the
nearest obstacle (wall). The direction is then corrected using
adjacent sensor readings, which are assumed to give distance
values from the same obstacle (this assumption is valid for the
wall-following task). Fig. 23 shows a scenario and the sensor
readings when the heading direction of the robot is not aligned

with the wall. Let d1 be the minimum-distance value coming

from the sensor placed at 1 and df and dr be its adjacent front
and back sensor readings, respectively. df and dr will not be
equal when the robot is misaligned with the wall. The alignment
angle is 1 , where is given by


df dr
= tan1
.
(18)
df + dr
The robots offset is then corrected by calculating its present
distance to wall, Dwall = d1 cos(). The hardware architecture
for the wall-following scheme using repeated alignment correction is explained in the next section.
1) Wall-Following Architecture Using CORDIC: The block
diagram for the architecture is shown in Fig. 24.
CORDIC-based alignment circuit: The new area-efficient
CORDIC is used first in vectoring mode to find defined by
(18). The inputs x and y to the CORDIC are initialized to
df + dr and df dr , respectively. Next, the CORDIC is used
in rotation mode to find Dwall with x, y and z initialized to d1 ,
0 and , respectively.
Next-move decision logic: The next move is based on two
steps executed alternately: the ALIGN_DISTANCE step and the
ALIGN_ANGLE step. The ALIGN_DISTANCE step takes the
sensor readings and calculates the normal direction with respect
to the present heading direction of the robot as well as the
offset error in distance. The outputs of this step, AN GLE and
DIST AN CE, are given to the motors such that the motor first
turns by AN GLE and then translates by DIST AN CE cm.
Step: ALIGN_DISTANCE
If (Dwall > Doset )
AN GLE = 1 ; DIST AN CE = Dwall Doset
else
If (1 < 0)
AN GLE = 180 + 1
else
AN GLE = 180 + 1 ;
DIST AN CE = Doset Dwall

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 12, DECEMBER 2009

involves alignment with the wall and moving along the wall.
The maximum turn required in the alignment phase is 90
which takes roughly 1.53 s for our robot. The step size to move
along the wall is 10 cm, and this takes approximately 0.73 s.
Therefore, wall following at each step requires a maximum of
2.58 s (0.32 s for sensor reading, +1.53 s for turning, +0.73 s
for translating).
V. C ONCLUSION
Fig. 25. Architecture for next-move-decision logic.

This paper has presented an area-efficient CORDIC algorithm. The algorithm is shown to use 50% fewer FPGA resources than a conventional CORDIC implementation. Using
the new CORDIC, this paper has also presented hardwareefficient solutions for two high-level mobile robotic tasks.
R EFERENCES

Fig. 26. Take-sensor ID 2s distance value.

Fig. 27. Move parallel to wall.

The ALIGN_ANGLE step involves taking a 90 turn to align

the robot parallel to the wall and move by a step in the forward
direction.
Step: ALIGN_ANGLE
If (AN GLE < 0)
AN GLE = 90
else
AN GLE = 90 ; DIST AN CE = ST EP _SIZE
The hardware architecture for finding normal direction used
in ALIGN_DISTANCE step is shown in Fig. 25.
Control unit: The sequence of events generated by the
control unit will be in the following order to enable individual blocks: sensors, minimum-distance finder, CORDICbased alignment circuit, next-move-decision logic, and motors.
The motors are given commands twice, one for each step
(ALIGN_DISTANCE and ALIGN_ANGLE) in the next-movedecision logic.
2) FPGA Usage: For the wall-following task, the CORDICbased alignment circuit requires 455 LUTs (in the XC2S200EPQ208) and is the dominant user of the device. The control unit
requires 198 LUTs.
3) Experiment on Wall Following: The snapshots of the
experiment are shown in Figs. 26 and 27. Wall following

[1] J. E. Volder, The CORDIC trigonometric computing technique, IRE

Trans. Electron. Comput., vol. 8, no. 3, pp. 330334, Sep. 1959.
[2] T. Srikanthan and B. Gisuthan, A novel technique for eliminating
iterative based computation of polarity of micro-rotations in CORDIC
based sinecosine generators, Microprocess. Microsyst., vol. 26, no. 5,
pp. 243252, Jun. 2002.
[3] K. Maharatna, A. Troya, S. Banerjee, and E. Grass, Virtually scaling-free
adaptive CORDIC rotator, Proc. Inst. Elect. Eng.Comput. Digit. Tech.,
vol. 151, no. 6, pp. 448456, Nov. 2004.
[4] M. G. B. Sumanasena, A scale factor correction scheme for the CORDIC
algorithm, IEEE Trans. Comput., vol. 57, no. 8, pp. 11481152,
Aug. 2008.
[5] M. Hariyama and M. Kameyama, Collision detection VLSI processor
for intelligent vehicles based on efficient coordinate transformation
scheme, in Proc. IEEE Int. Conf. Ind. Electron., Control, Instrum., 1996,
pp. 755760.
[6] T. Lund, M. Aguirre, and A. Torralba, Making use of CORDIC and
distributed arithmetic to produce a field-programmable fuzzy logic controller in an FPGA, in Proc. Int. Conf. Ind. Electron., Control, Instrum.
(IECON), 2002, pp. 32053208.
[7] E. Monmasson and M. N. Cirstea, FPGA design methodology for industrial control systemsA review, IEEE Trans. Ind. Electron., vol. 54,
no. 4, pp. 18241842, Aug. 2007.
[8] J. J. Rodriguez-Andina, M. J. Moure, and M. D. Valdes, Features, design
tools, and application domains of FPGAs, IEEE Trans. Ind. Electron.,
vol. 54, no. 4, pp. 18101823, Aug. 2007.
[9] H. Tanaka, K. Ohnishi, H. Nishi, T. Kawai, Y. Morikawa, S. Ozawa, and
T. Furukawa, Implementation of bilateral control system based on acceleration control using FPGA for multi-DOF haptic endoscopic surgery
robot, IEEE Trans. Ind. Electron., vol. 56, no. 3, pp. 618627, Mar. 2009.
[10] J. Baturone, F. J. Moreno-Velo, V. Blanco, and J. Ferruz, Design of
embedded DSP-based fuzzy controllers for autonomous mobile robots,
IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 928936, Feb. 2008.
[11] R. C. Luo and K. L. Su, Multilevel multisensor-based intelligent recharging system for mobile robot, IEEE Trans. Ind. Electron., vol. 55, no. 1,
pp. 270279, Jan. 2008.
[12] S. Kim and F. C. Park, Fast robot motion generation using principal
components: Framework and algorithms, IEEE Trans. Ind. Electron.,
vol. 55, no. 6, pp. 25062516, Jun. 2008.
[13] F. Angarita, A. Perez-Pascual, T. Sansaloni, and J. Valls, Efficient FPGA
implementation of CORDIC algorithm for circular and linear coordinates, in Proc. IEEE Int. Conf. Field Program. Logic Appl., 2005,
pp. 535538.
[14] J. Valls, M. Kuhlmann, and K. K. Parhi, Evaluation of CORDIC
algorithms for FPGA design, J. VLSI Signal Process., vol. 32, no. 3,
pp. 207222, Nov. 2002.
[15] S. Wang, V. Piuri, and E. E. Swartzlander, Hybrid CORDIC algorithms,
IEEE Trans. Comput., vol. 46, no. 11, pp. 12021207, Nov. 1997.
[16] S. Wang and E. Swartzlander, Critically damped CORDIC algorithm,
in Proc. MWSCAS, 1994, pp. 253256.
[17] C. H. Lin and A. Y. Wu, Mixed-scaling-rotation CORDIC
(MSR-CORDIC) algorithm and architecture for high performance
vector rotational DSP applications, IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 52, no. 11, pp. 23852396, Nov. 2005.

VACHHANI et al.: EFFICIENT FPGA REALIZATION OF CORDIC WITH APPLICATION TO EXPLORATION

[18] Xilinx CORDIC V3.0, Product Specification No. DS249, San Jose, CA,
Apr. 2005. [Online]. Available: http://japan.xilinx.com/support/
documentation/ip_documentation/cordic.pdf
[19] R. Mahkovic, Construction of the generalized Voronoi diagram of the
unknown environment, in Proc. IEEE ISIE, 1999, pp. 984989.

Leena Vachhani (S05) received the B.Eng. degree

in electronics from Bhilai Institute of Technology,
Durg, India, in 1996, the M.Eng. degree in microprocessors from Maharaja Sayajirao University
of Baroda (MSU), Vadodara, India, in 2000, and
the Ph.D. degree from the Department of Electrical
Engineering, Indian Institute of Technology Madras,
Chennai, India.
She was a Lecturer with the Department of Electrical Engineering, MSU, for four years. She is currently an Assistant Professor with the Indian Institute
of Information Technology, Design and Manufacturing Kancheepuram, Chennai. Her research interests include reconfigurable architectures, robotics, and
hardware/software codesign.

K. Sridharan (S84M96SM01) received the

Ph.D. degree from Rensselaer Polytechnic Institute,
Troy, NY, in 1995.
From 1996 to 2001, he was an Assistant Professor
with the Indian Institute of Technology Guwahati,
Guwahati, India. He was a visiting Staff Member
with Nanyang Technological University, Singapore,
from 2000 to 2001 and from 2006 to 2008. He is
currently a Professor with the Electrical Engineering
Department, Indian Institute of Technology Madras,
Chennai, India. He has supervised three Ph.D. students and is the holder of two patents. He is the author of a book on
robotics published by Springer in 2008. He is also the author of approximately
65 papers.
Prof. Sridharan is a member of the IEEE Industrial Electronics Society.
He was the recipient of the Computer Engineering Division Prize for a paper
published in the Journal of the Institution of Engineers (India) in 2002. He was
also a joint recipient of the IEEE Vincent Bendix Award.

4929

Pramod Kumar Meher (SM03) received the B.Sc.

(first-class honors) and M.Sc. degrees in physics and
the Ph.D. degree in science from Sambalpur University, Sambalpur, India, in 1976, 1978, and 1996,
respectively.
From 1981 to 1993, he was a Lecturer in physics
with various government colleges (in India). From
1993 to 1997, he was a Reader in electronics with
Berhampur University, Berhampur, India. From 1997
to 2002, he was a Professor of Computer Applications with Utkal University, Bhubaneswar, India.
He was a Senior Fellow with the School of Computer Engineering, Nanyang
Technological University, Singapore. He is currently a Senior Scientist with the
Institute for Infocomm Research, Singapore. He is the author of nearly 140
papers. He is an Associate Editor for the Journal of Circuits, Systems, and
Signal Processing. He has a wide scientific and technical background, covering
physics, electronics, and computer engineering. His research interests include
the design of dedicated and reconfigurable architectures for computationintensive algorithms pertaining to signal processing, image processing, secure
communication, and bioinformatics.
Dr. Meher is a Fellow of the Institution of Electronics and Telecommunication Engineers of India and the Institution of Engineering and Technology
(formerly Institution of Electrical Engineers). He is a Chartered Engineer of
the Engineering Council of the United Kingdom. He was the recipient of the
Samanta Chandrasekhar Award for excellence in research in engineering and
technology for the year 1999. He is currently an Associate Editor for the IEEE
T RANSACTIONS ON C IRCUITS AND S YSTEMS II: E XPRESS B RIEFS, and
IEEE T RANSACTIONS ON V ERY L ARGE S CALE I NTEGRATION S YSTEMS .