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FIR-filter
Christian Sderbacka
s92696
List of contents
1.PDSP vs. FPGA
2.Some common implementations
3.A (very) simple example in VHDL
4.Another example
5.Using software to generate the coefficients
Appendices:
MAC
(Meyer-Baese, p.12-13)
FPGA
tap(0)*(-1)
tap(1)*(2+1+0.5+0.25)
tap(2)*(2+1+0.5+0.25)
tap(3)*(-1)
Simulation results
Example:
Filter information
References
-- Define a "Blackbox"
entity fir_srg is
port( clk: in std_logic;
x: in byte;
y: out byte);
end fir_srg;
p1: process
begin
wait until clk = '1'; -- wait for rising edge of clock
-- Compute output y with the filter coefficients weight
-- The coefficients are [-1 3.75 3.75 -1]
-- Division only allowed for powers-of-two values!
y <= 2 * tap(1) + tap(1) + tap(1)/2 + tap(1)/4
+ 2 * tap(2) + tap(2) + tap(2)/2 + tap(2)/4
- tap(3) - tap(0);
-- Tapped delay line: shift one left
for i in 3 downto 1 loop
tap(i) <= tap(i-1);
end loop;
tap(0) <= x; -- Input inserted to register, overwrites old value
end process p1;
end flex;
entity fir_test is
end fir_test;
begin
fir: entity work.fir_srg(flex)
port map(x => Xin, y => Yout, clk => clock);
input_test: process
begin
wait for 10 ns;
Xin <= 1;
wait for 20 ns;
Xin <= 2;
wait for 20 ns;
Xin <= 3;
wait for 20 ns;
Xin <= 0;
wait;
end process input_test;
end testbench;