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A New Technique for Leakage Reduction in CMOS Circuits using

Self-Controlled Stacked Transistors


Narender Hanchate and N. Ranganathan
Nanomaterials and Nanomanufacturing Research Center
Department of Computer Science and Engineering
University of South Florida, Tampa, FL 33620.
narender,ranganat @csee.usf.edu


Abstract
In CMOS circuits, the reduction of the threshold voltage
due to voltage scaling leads to increase in sub threshold
leakage current and hence, static power dissipation. We
propose a novel technique called LECTOR for designing
CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In
the proposed technique, we introduce two leakage control
transistors (a p-type and a n-type) within the logic gate
for which the gate terminal of each leakage control transistor (LCT) is controlled by the source of the other. In this
arrangement, one of the LCTs is always near its cut-off
voltage for any input combination. This increases the reto ground leading to signifisistance of the path from
cant decrease in leakage currents. The gate-level netlist of
the given circuit is first converted into a static CMOS complex gate implementation and then LCTs are introduced to
obtain a leakage controlled circuit. The significant feature
of LECTOR is that it works effectively in both active and
idle states of the circuit, resulting in better leakage reduction compared to other techniques. Further, the proposed
technique overcomes the limitations posed by other existing
methods for leakage reduction. Experimental results indicate an average leakage reduction of 79.4% for MCNC 91
benchmark circuits.


dissipation can be reduced to 10% of total power dissipation by designing the circuit to have equal input and output rise/fall edge times [5]. Voltage scaling technique for
dynamic power reduction takes benefit of quadratic dependence of capacitive power on supply voltage. However, this
technique pays a penalty for the speed of the circuit by increasing the delay drastically as supply voltage approaches
the threshold voltage ( ) of the devices. In order to facilitate voltage scaling without affecting the performance,
threshold voltage has to be reduced. In general, the ratio between the supply voltage and the threshold voltage should
be at least five, so that the performance of CMOS circuits
is not affected [12]. This also leads to better noise margins
and helps to avoid the hot-carrier effects in short channel
devices [11]. Scaling down of threshold voltage ( ) results in exponential increase of the sub-threshold leakage
current [2]. The supply voltage and threshold voltage scaling trends for Intels microprocessor process technologies
are discussed in [15] and shown in Figure 1. The leakage
power dissipation is approaching the active power dissipation in near few generations, enforcing the necessity of leakage control techniques.


1 Introduction
Power dissipation is an important consideration in the
design of CMOS VLSI circuits. The main current components of power dissipation are: (i) capacitive load currents (ii) short circuit currents and (iii) leakage currents.
The leakage currents consist of reverse-bias diode currents
and sub-threshold currents. The former is due to the stored
charge between the drain and bulk of active transistors while
the latter is due to the carrier diffusion between the source
and drain of the Off transistors. The short circuit power

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Figure 1. Voltage supply and threshold voltage scaling


trend. Courtesy: Intel Corporations

The technique based on Input vector control [7], puts the

circuit into low-leakage standby state when idle and restores


to correct state when active with the help of additional logic
circuitry. This requires special latches to remember the correct state of the circuit, thereby, increasing the area overhead by five times in the worst-case [3]. Also, the amount
of time for which the unit remains in idle state should be
long enough so that the dynamic power consumed in forcing
the circuit to low-leakage state and the leakage power dissipated in the standby state together is less than the leakage
power without the technique. Power gating [9, 8] and multiple threshold CMOS (MTCMOS) techniques [6] turns off
the devices by cutting off their supply voltage using sleep
transistors. The sleep transistor is turned on when the circuit is active and turned off when the circuit is in idle state
with the help of sleep signal. There is a significant increase
in the delay of the circuit when active, due to the presence
of the sleep transistor on switching path. The identification of the idle regions of the circuit and the generation of
the sleep signal need additional hardware capable of predicting the circuit states accurately. This additional hardware consumes power throughout the circuit operation even
when the circuit is in an idle state to continuously monitor
the circuit state and control the sleep transistors. Another
variation called dual technique [11, 16], uses low threshold transistors for gates on the critical path and high threshold transistors for gates not in the critical path. Additional
mask layers for each value of threshold voltage are required
for fabricating the transistors selectively according to their
assigned threshold voltage values, giving raise to complex
fabrication process.


of the paper is organized as follows. Section 2 describes the


LECTOR technique and how it controls the leakage currents. A strategy for reducing the area overhead due to insersion of Leakage Control Transistors (LCTs) is described
in Section 3. Results are presented in Section 4 followed by
conclusions in Section 5.

2 The LECTOR Technique


The basic idea behind our approach for reduction of leakage power is the effective stacking of transistors in the path
from supply voltage to ground. This is based on the observation made in [14, 13, 8] that a state with more than
one transistor Off in a path from supply voltage to ground
is far less leaky than a state with only one transistor Off in
any supply to ground path. In our method, we introduce
two Leakage Control Transistors (LCTs) in each CMOS
gate such that one of the LCTs is near its cut-off region
of operation. We illustrate our LEakage Control TransistOR technique (LECTOR) with the case of a NAND gate.
A CMOS NAND gate with the addition of two leakage control transistors is shown in Figure 2 (we later refer to it as
LCT NAND gate).
Vdd

Forced stacking [13], introduces an additional transistor


for every input of the gate in both N- and P-networks to ensure two transistors to be Off for every Off-input of the gate.
However, the loading requirements due to forced stacking
reduces the drive current of the gate significantly and hence,
the switching speed. In [8], a blend of sleep transistors and
the stacking effects are used to reduce leakage power. This
method identifies a circuit input vector for which the leakage current of the circuit is the lowest possible. The sleep
signal controlled transistors are inserted away from the critical path where only one transistor is Off when low leakage
input vector is applied to the circuit. Hence, this technique
is input vector dependent. Moreover, as this technique uses
sleep transistors, it needs additional control hardware consuming power in both idle and active states.
All the existing techniques except forced stacks, donot
effectively control the leakage currents when the circuit is
in its active state. In this paper, we describe a new technique
called LECTOR (LEakage Control TransistOR) for designing CMOS circuits aimed at leakage power reduction. Our
technique control doesnot distinguish between active and
idle states of the circuit and effectively control the leakage
currents during all states of the circuit operation. The rest

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M1


M2


N1


Additional circuitry
for Leakage Control

LCT1
Out

LCT2
N2

Ain






LCT: Leakage Control Transistor


N1 N2 N3 are internal nodes

B in


M3
N3

M4
Gnd

Figure 2. 2-input LCT NAND gate


Two leakage control transistors
(PMOS) and
(NMOS) are introduced between the nodes
and
of the pull-up and pull-down logic of the NAND gate.
and
are conThe drain nodes of the transistors
nected together to form the output node. The source nodes
of the transistors are connected to nodes
and
of pullup and pull-down logic. The switching of transistors
and
are controlled by the voltage potentials at nodes
and
respectively. This wiring configuration ensures
that one of the LCTs is always near its cut-off region, irrespective of the input vector applied to the NAND gate. This
can be seen from the DC characteristics shown in Figure 3,
obtained from HSPICE simulations. Figure 3(a) shows the


DC characteristics of the unmodified NAND gate and Figure 3(b) shows that of the LCT NAND Gate, when the input
is fixed at 1V and
is varied from 0V to 1V.


Transistor


Input Vector - (
,
(0,0)
(0,1)
(1,0)
On
On
Off
On
Off
On
NCO NCO NCO
On
On
On
Off
Off
On
Off
On
Off


)
(1,1)
Off
Off
On
NCO
On
On


Note: NCO = Near Cut-Off

Table 1. State matrix of 2-input LCT NAND gate


age. We have observed that LECTOR produces slightly
weak logic levels (around 960mV of logic high and 35mV
of logic zero) for 180nm and 130nm process technologies.
But, it produces exact logic levels for 70nm and 100nm process variations. The reason for this behavior of LECTOR
could be the difference between the supply voltage and the
threshold voltage of a process variation. When we increase
the supply voltage to 1.8V, LECTOR produces exact logic
levels for all the four process variations.
The transistors of the LCT NAND gate are sized to study
its effect on the propagation delay of the gate. Y-LCT gates
are obtained by sizing the widths of only the leakage conand
to Y-times the width of
trol transistors,
other PMOS and NMOS transistors of the gate respectively.
Also, we have tried to adjust the widths of all the transistors of the LCT NAND gate such that its propagation delay
is almost equal to that of a conventional NAND gate (We
refer to this gate as Iso-LCT NAND gate). The widths of
PMOS and NMOS transistors, except LCT transistors, used
in simulation of Y-LCT gates are set to two and three times
the minimum feature width of the respective process variation. The leakage power dissipation and propagation delay values for 2-input NAND gate using 100nm and 70nm
technology processes are tabulated in Tables 2. It can be
observed that as the threshold voltage decreases, which is
the case as we move towards deep submicrometer, our technique produces better leakage power reductions. Hence, the
use of LECTOR enhances further reduction of the supply
voltage along with the threshold voltage, thereby favoring
technology advancements.
In the technique discussed in [8], the sleep transistors
have to be able to isolate the power supply and/or ground
from the rest of the transistors of the gate. Hence, they need
to be made bulkier dissipating more dynamic power. This
offsets the savings yielded when the circuit is idle. Moreover, this technique is input vector dependent and needs additional circuitry to monitor and control the switching of
sleep transistors. Thus, it consumes power in both active
and idle states. In comparison, LECTOR is vector independent and the required control signals are generated within
the gate. Forced stacks [13] have 100% area overhead. In
comparison, LECTOR requires exactly two additional transistors for every path from supply voltage to ground irre

Figure 3. DC Characteristics of 2-input NAND gate


Consider the DC characteristics of LCT NAND gate.
When
= 1V and
= 0V, the voltage at the node
is 800mV. This voltage is not sufficient to turn
completely to off state. Hence, the resistance of
will
be lesser than its off resistance, allowing conduction. Even
though the resistance of
is not as high as its off state
resistance, it increases the resistance of
to ground path,
controlling the flow of leakage currents, resulting in leak= 1V and
=
age power reduction. Similarly when
1V, the voltage of node
is 200mV, operating the transistor
near its cut-off region. The state of the transistors for all possible combinations of input vectors for LCT
NAND gate are tabulated in Table 1. Thus the introduction
to
of LCTs increases the resistance of the path from
ground. This also increases the propagation delay of the
gate. To reduce this hostile effect, the transistors of LCT
gate are sized such that the propagation delay is equal to its
conventional counter part.
We have tested the LECTOR with process variations of
180nm, 130nm, and 100nm technologies at 1V supply volt

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NAND
gate type
Conventional
LCT
1.5-LCT
2-LCT
2.5-LCT
Iso-LCT
Conventional
LCT
1.5-LCT
2-LCT
2.5-LCT
Iso-LCT

100nm Process Technology, Supply Voltage = 1V


Leakage Power Dissipation in Watts for Input Vector
(0,0)
(0,1)
(1,0)
(1,1)
1.228e-10 9.117e-10 5.356e-10
2.241e-09
1.180e-10 5.542e-10 4.477e-10
1.539e-09
1.182e-10 5.788e-10 4.533e-10
1.593e-09
1.194e-10 5.985e-10 4.606e-10
1.621e-09
1.197e-10 6.114e-10 4.678e-10
1.651e-09
1.224e-10 6.394e-10 4.872e-10
1.704e-09
70nm Process Technology, Supply Voltage = 1V
6.450e-10 5.600e-09 3.817e-09
1.091e-08
6.065e-10 3.808e-09 3.622e-09
5.564e-09
6.108e-10 3.900e-09 3.650e-09
5.742e-09
6.146e-10 3.961e-09 3.667e-09
5.872e-09
6.189e-10 4.016e-09 3.675e-09
6.060e-09
6.314e-10 4.125e-09 3.689e-09
6.196e-09

Delay
in (ps)
13.53
18.79
17.12
15.64
15.39
13.59

% Average
Savings
30.20%
28.01%
26.54%
25.22%
22.51%

15.16
21.40
19.09
18.36
17.99
15.23

35.12%
33.70%
32.71%
31.48%
30.18%

Note: Y-LCT = Only LCT transistors are Y times the widths of their respective type.

Table 2. Leakage power for 2-input NAND gate


spective of the logic function realized by the gate. The loading requirements of the gate with forced stacks are huge and
depend on the number of additional transistors added. In
comparison, the loading requirements with LCTs is much
lower and is almost a constant. Hence, the performance
degradation in the case of LECTOR can be nullified by sizing the transistors, and we overcome the major drawback
faced by forced stack technique.

3 Reducing Area Overhead


A method to control the leakage power in a 2-input
NAND gate was described above. If we extend this idea to
all the basic logic gates then the area overhead on the entire
circuit will increase up to an upper bound of 60% depending on the logic gates used. Consider a 4-input AND-ORInverter (AOI22) gate. Figure 4 shows two different implementations of the gate. The first implementation uses two
2-input AND gates, one 2-input OR gate and an Inverter, requiring a total of 20 transistors for its realization. A second
implementation shows an equivalent compound/complex
gate realization. A compound gate is formed by the combination of series- and parallel- MOS structures with complementary pull-up and pull-down logic [10]. The required
series and parallel combinations of transistors are generated
by analyzing the relevant Karnaugh map for both n- and plogic structures and using De-Morgans theorems. As these
gates are built on static CMOS technology, they are called
Static CMOS Complex Gates (SCCG) [10]. SCCG implementation of AOI22 gate needs 8 transistors and hence is an
efficient method for its realization. We have chosen to use
SCCG gates for LECTOR as it not only saves area but also
suits well for inserting leakage control transistors. This is
because SCCG gates have exactly one common node which
connects the pull-up and pull-down circuits of the gate. This

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node is the appropriate place for inserting LCTs as all the


paths from the supply voltage to ground would pass through
this node. The limitation with SCCG gates is that if the
number of transistors in series exceeds an upper limit in
any path of pull-up or pull-down logic then there is a hostile effect on the propagation delay of the gate. Typically
this upper bound can be safely fixed to three or even four
transistors.
Vdd
A

D
A

B
Z









Gnd

Z = ((A.B) + (C.D))
(a)

(b)

Figure 4. Two implementations of AND-OR-Inverter


Figure 5 describes the sequence of steps for obtaining a leakage-controlled circuit from the gate-level netlist.
The Sequential and Combinational circuit Synthesis System (SIS tool) [4] or the TRAnsistor Binding Using COmplex gates (TRABUCO) [1] tool can be used for performing technology mapping of the netlist. SIS is a technology
dependent mapping tool and hence uses a standard set of
gates pre-defined in its library for performing technology
mapping. A library of SCCG gates with a maximum of two
series transistors each was created. The constraint on the
maximum number was induced in the topology for performance reasons. TRABUCO, on other hand, is a technology
independent mapping tool, which maps the netlist on to a

Gate-Level
Netlist

Netlist to
BLIF Conversion

Technology Dependent
Mapping with
SIS

Technology Independent
Mapping with
TRABUCO

BLIF Netlist
with SCCG Gates
SCCG Gate Library
(3Serial Transistors)

Virtual Library
Leakage Controlled
Circuit (LCC)

BLIF to Spice
Conversion

Hspice Simulator

Figure 5. General design flow


virtual library of SCCG gates. The tool creates virtual library of SCCG gates dynamically and hence does not need
any library support. The circuit with SCCG gates obtained
by SIS or TRABUCO tool from the input netlist is then converted to LECTOR-style circuit by introducing LCTs. The
LECTOR circuit is then converted to spice format with the
help of a script for simulation with HSPICE simulator.

4 Experimental Results
The LECTOR technique was implemented and tested on
MCNC 91 benchmark circuits. The MCNC 91 benchmarks are mapped onto a library of SCCG gates using SIS
tool. The SCCG gates in the library are restricted to have atmost two series transistors. After mapping, the SCCG gates
are converted to LCT gates by the adding two LCTs to obtain a LCT MCNC Circuit. In order to make a fair comparison, the MCNC 91 benchmarks are again mapped using
SIS tool onto a different library of gates having atmost 3
inputs, to obtain an Unmodified MCNC circuit (we refer
to this as U-MC circuit later). We have analyzed the critical path delays of both LCT MCNC circuit and the corresponding U-MC circuit using HSPICE. Only the LCT gates
present on the critical path of the LCT MCNC circuit are
sized such that the critical path delays of both U-MC and
LCT MCNC circuit are almost equal. (This LCT MCNC
circuit is later refered as LCT-MC). The HSPICE simulator
was preferred for measuring the leakage power, as it is accurate. Simulations were performed using the 70nm fabrication process generated using the BSIM predictive models
with temperature set to 25 degree celsius.
Table 3 provide the summary of the results obtained
on the benchmark circuits. The first column indicates the
MCNC 91 benchmark circuits. Columns two and three
give the average leakage power dissipation for U-MC and

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LCT-MC circuits respectively. Columns six and seven provide the average total power dissipation for the respective
circuits. Both the leakage and total power estimates were
obtained by averaging the circuit simulations over 10 different sets of 500 randomly generated input patterns. The
input patterns are triggered with long time intervals between
them so as to have minimum circuit switching activity. The
values in columns four and five give the dynamic power estimates obtained for U-MC and LCT-MC circuits respectively. These estimates are obtained by triggering both the
circuits with the 10 different sets of 1000 randomly generated input patterns. These inputs are applied with quick
succession such that switching activity in the circuit is high.
Column eight gives the normalized area of LCT-MC circuits
with respect to U-MC circuits. We have created standard
cell layouts of all the gates used by both LCT-MC and UMC circuits. Cadence Silicon Ensemble is used as place and
route tool to measure the area overhead of LCT-MC circuit
with respect to U-MC circuit.
The results show an average reduction of 79.4% in average leakage power dissipation with an average area overhead of 14%. We want here to note that the leakage savings obtained is without any significant sacrifice in dynamic
power. Columns nine and ten of Table 3 shows a comparison of leakage savings obtained in MCNC 91 benchmarks
with LECTOR and the techniques from [8]and [16]. These
two works were chosen for comparison as the first technique
works on an idea similar to ours and the second work, because of the significant results it yields in dual threshold
voltage technique category. Referring to Table 3, the savings obtained by LECTOR for circuits I1 to I10 are compared with those obtained by transistor stacks. For circuits
C432 to C7552, we compare our results over dual threshold
voltage technique. The savings for transistor stacks technique are those obtained on application of the Best Inputs
as against average case values in the case of LECTOR. We
can observe from Table 3 that LECTOR out-performs both
the compared techniques for all the circuits except C880
circuit where in also, it is almost equal to the dual threshold
voltage technique. The area overhead observed in transistor
stacks technique [8] was 18% as against to 14% in our case.

5 Conclusions
Scaling down of device dimensions, supply voltage, and
threshold voltage for achieving high-performance and low
dynamic power dissipation has largely contributed to the
increase in leakage power dissipation. Leakage current is
especially important in portable systems where battery life
is important. We have presented an efficient design methodology for reducing the leakage power in CMOS circuits.
LECTOR performs well as the threshold voltage decreases
and hence aids further reduction of supply voltage and minimization of transistor sizes. Experimental results show that

MCNC 91
Circuit
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10

Leak Pwr ( W)
U-MC LCT-MC
1.159
0.156
2.305
0.735
1.383
0.419
2.356
0.632
4.625
0.475
6.906
1.912
8.933
3.126
30.05
5.038
21.90
2.897
40.47
5.842

Dyn. Pwr (in W)


U-MC LCT-MC
1.122
1.094
2.420
2.661
1.063
1.025
2.043
1.995
5.905
5.945
18.62
18.85
25.62
25.59
59.06
58.34
38.79
37.24
54.58
52.13

Total Pwr ( W)
U-MC LCT-MC
1.275
0.291
2.375
0.807
1.451
0.712
2.436
0.756
5.473
0.732
12.70
6.495
17.95
9.248
41.08
10.56
25.75
8.982
43.31
11.23

1.395
3.469
6.141
8.089
19.61
52.17
64.79
82.58
163.7
323.2

6.970
16.38
9.472
16.08
28.43
70.45
81.65
99.21
520.4
576.2

1.923
5.037
7.972
9.754
24.53
65.70
73.41
88.50
390.2
393.3

Norm.
area
1.21
1.14
1.18
1.12
1.19
1.13
1.12
1.08
1.12
1.15

% Leakage savings by
Stacks [8]
LECTOR
67.34%
86.54%
61.61%
68.11%
61.97%
69.70%
55.03%
73.17%
83.51%
89.72%
60.74%
72.31%
51.39%
65.01%
74.32%
83.23%
85.15%
86.77%
83.39%
85.56%
Dual
[16]
28.83%
51.82%
22.96%
58.37%
82.67%
81.21%
21.50%
79.32%
84.92%
90.18%
90.25%
94.54%
83.36%
94.05%
91.56%
94.16%
61.75%
94.05%
90.90%
96.86%


C432
C499
C880
C1355
C1908
C2670
C3540
C5315
C6288
C7552

0.672
1.444
1.154
1.672
1.926
2.845
3.852
4.826
9.725
10.24

6.889
16.03
9.502
15.93
27.10
69.59
76.49
97.60
502.2
566.6

1.260
2.990
2.493
3.104
3.613
4.338
4.588
5.892
30.23
22.96

1.17
1.15
1.18
1.11
1.13
1.19
1.14
1.12
1.10
1.08

The critical path delays of U-MC and LCT-MC circuits are made equal by sizing LCT gates on critcal path.
Normalized area is the ratio of areas of LCT-MC circuit and U-MC circuit.

Table 3. Experimental results for MCNC 91 benchmarks


our technique offers a leakage reduction on the average of
about 79.4% for the same critical path delay relative to the
unmodified circuit for MCNC 91 benchmarks with 14%
area overhead.

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