Beruflich Dokumente
Kultur Dokumente
Background
Swapping
Paging
Segmentation
8.2
Objectives
To provide a detailed description of the Intel Pentium, which supports both pure segmentation and
segmentation with paging
8.3
Background
Program must be brought (from disk) into memory and placed within a process for it to be run
Main memory and registers are only storage CPU can access directly
Memory unit only sees a stream of addresses + read requests, or address + data and write requests
8.4
A pair of base and limit registers define the logical address space
8.5
8.6
Address Binding
8.7
Address binding of instructions and data to memory addresses can happen at three different stages
Compile time: If memory location known a priori, absolute code can be generated; must
recompile code if starting location changes
Load time: Must generate relocatable code if memory location is not known at compile time
Execution time: Binding delayed until run time if the process can be moved during its execution
from one memory segment to another
Need hardware support for address maps (e.g., base and limit registers)
8.8
8.9
The concept of a logical address space that is bound to a separate physical address space is central to
proper memory management
Logical and physical addresses are the same in compile-time and load-time address-binding schemes;
logical (virtual) and physical addresses differ in execution-time address-binding scheme
Logical address space is the set of all logical addresses generated by a program
Physical address space is the set of all physical addresses generated by a program
8.10
To start, consider simple scheme where the value in the relocation register is added to every address
generated by a user process at the time it is sent to memory
The user program deals with logical addresses; it never sees the real physical addresses
8.11
8.12
Dynamic Loading
Useful when large amounts of code are needed to handle infrequently occurring cases
8.13
Dynamic Linking
Static linking system libraries and program code combined by the loader into the binary program image
Small piece of code, stub, used to locate the appropriate memory-resident library routine
Stub replaces itself with the address of the routine, and executes the routine
8.14
Swapping
A process can be swapped temporarily out of memory to a backing store, and then brought back
into memory for continued execution
Total physical memory space of processes can exceed physical memory
Backing store fast disk large enough to accommodate copies of all memory images for all
users; must provide direct access to these memory images
Roll out, roll in swapping variant used for priority-based scheduling algorithms; lower-priority
process is swapped out so higher-priority process can be loaded and executed
Major part of swap time is transfer time; total transfer time is directly proportional to the amount
of memory swapped
System maintains a ready queue of ready-to-run processes which have memory images on disk
Does the swapped out process need to swap back in to same physical addresses?
Depends on address binding method
Plus consider pending I/O to / from process memory space
Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows)
8.15
8.16
If next processes to be put on CPU is not in memory, need to swap out a process and swap in target
process
Can reduce if reduce size of memory swapped by knowing how much memory really being used
System calls to inform OS of memory use via request memory and release memory
8.17
Contiguous Allocation
Resident operating system, usually held in low memory with interrupt vector
Relocation registers used to protect user processes from each other, and from changing operating-system
code and data
Limit register contains range of logical addresses each logical address must be less than the limit
register
Can then allow actions such as kernel code being transient and kernel changing size
8.18
8.19
Multiple-partition allocation
Hole block of available memory; holes of various size are scattered throughout memory
When a process arrives, it is allocated memory from a hole large enough to accommodate it
OS
OS
OS
OS
process 5
process 5
process 5
process 5
process 9
process 9
process 8
process 2
Operating System Concepts 8th Edition
process 10
process 2
process 2
8.20
process 2
Silberschatz, Galvin and Gagne 2009
Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size
Produces the smallest leftover hole
Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole
First-fit and best-fit better than worst-fit in terms of speed and storage utilization
8.21
Fragmentation
External Fragmentation total memory space exists to satisfy a request, but it is not contiguous
Internal Fragmentation allocated memory may be slightly larger than requested memory; this size
difference is memory internal to a partition, but not being used
First fit analysis reveals that given N blocks allocated, 0.5 N blocks lost to fragmentation
8.22
Fragmentation (Cont.)
Shuffle memory contents to place all free memory together in one large block
I/O problem
8.23
Paging
Physical address space of a process can be noncontiguous; process is allocated physical memory
whenever the latter is available
To run a program of size N pages, need to find N free frames and load program
8.24
Page number (p) used as an index into a page table which contains base address of each page in
physical memory
Page offset (d) combined with base address to define the physical memory address that is sent to
the memory unit
page number
page offset
m-n
8.25
Paging Hardware
8.26
8.27
Paging Example
8.28
Paging (Cont.)
8.29
Free Frames
After allocation
Before allocation
Operating System Concepts 8th Edition
8.30
One for the page table and one for the data / instruction
The two memory access problem can be solved by the use of a special fast-lookup hardware cache called
associative memory or translation look-aside buffers (TLBs)
Some TLBs store address-space identifiers (ASIDs) in each TLB entry uniquely identifies each process
to provide address-space protection for that process
On a TLB miss, value is loaded into the TLB for faster access next time
8.31
Associative Memory
Page #
Frame #
8.32
8.33
Hit ratio =
Hit ratio percentage of times that a page number is found in the associative registers; ratio related
to number of associative registers
Consider = 80%, = 20ns for TLB search, 100ns for memory access
Consider = 80%, = 20ns for TLB search, 100ns for memory access
EAT = 0.80 x 120 + 0.20 x 220 = 140ns
Consider slower memory but better hit ratio -> = 98%, = 20ns for TLB search, 140ns for memory
access
EAT = 0.98 x 160 + 0.02 x 300 = 162.8ns
8.34
Memory Protection
Memory protection implemented by associating protection bit with each frame to indicate if read-only or
read-write access is allowed
valid indicates that the associated page is in the process logical address space, and is thus a legal
page
invalid indicates that the page is not in the process logical address space
Or use PTLR
8.35
8.36
Shared Pages
Shared code
One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers,
window systems)
The pages for the private code and data can appear anywhere in the logical address space
8.37
8.38
Memory structures for paging can get huge using straight-forward methods
If each entry is 4 bytes -> 4 MB of physical address space / memory for page table alone
Hierarchical Paging
8.39
8.40
8.41
A logical address (on 32-bit machine with 1K page size) is divided into:
a page number consisting of 22 bits
a page offset consisting of 10 bits
Since the page table is paged, the page number is further divided into:
a 12-bit page number
a 10-bit page offset
page number
page offset
p1
p2
12
10
d
10
where p1 is an index into the outer page table, and p2 is the displacement within the page of the inner page
table
Known as forward-mapped page table
8.42
Address-Translation Scheme
8.43
If two level scheme, inner page tables could be 210 4-byte entries
p2
42
10
page offset
d
12
But in the following example the 2nd outer page table is still 234 bytes in size
8.44
8.45
This page table contains a chain of elements hashing to the same location
Each element contains (1) the virtual page number (2) the value of the mapped page frame (3) a pointer to
the next element
Virtual page numbers are compared in this chain searching for a match
8.46
8.47
Rather than each process having a page table and keeping track of all possible logical pages, track all
physical pages
Entry consists of the virtual address of the page stored in that real memory location, with information
about the process that owns that page
Decreases memory needed to store each page table, but increases time needed to search the table
when a page reference occurs
Use hash table to limit the search to one or at most a few page-table entries
8.48
8.49
Segmentation
8.50
8.51
2
4
3
user space
8.52
Segmentation Architecture
Segment table maps two-dimensional physical addresses; each table entry has:
base contains the starting physical address where the segments reside in memory
Segment-table base register (STBR) points to the segment tables location in memory
8.53
Protection
read/write/execute privileges
Protection bits associated with segments; code sharing occurs at segment level
8.54
Segmentation Hardware
8.55
Example of Segmentation
8.56
First partition of up to 8 K segments are private to process (kept in local descriptor table LDT)
Second partition of up to 8K segments shared among all processes (kept in global descriptor
table GDT)
8.57
8.58
8.59
8.60
Linux uses only 6 segments (kernel code, kernel data, user code, user data,
task-state segment (TSS), default LDT segment)
Linux only uses two of four possible modes kernel and user
Uses a three-level paging strategy that works well for 32-bit and 64-bit systems
8.61
8.62
End of Chapter 7