Beruflich Dokumente
Kultur Dokumente
DATA SHEET
2000 Mar 16
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
13
13.1
13.2
13.3
13.4
13.5
13.6.1
13.6.2
13.6.3
Test circuits
Measurement circuit
Tuning amplifier
Crystal oscillator
Examples of I2C-bus data format sequences for
TDA6502 and TDA6503
Write sequences to register C2
Read sequences from register C3
Examples of 3-wire bus data format sequences
for TDA6502 and TDA6503
18-bit sequence
19-bit sequence
27-bit sequence
14
15
PACKAGE OUTLINE
16
SOLDERING
16.1
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
3.1
3.2
I2C-bus format
3-wire bus format
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.3
8.3.1
LIMITING VALUES
16.2
16.3
16.4
10
THERMAL CHARACTERISTICS
17
DEFINITIONS
11
CHARACTERISTICS
18
TIMING CHARACTERISTICS
19
12
2000 Mar 16
13.5.1
13.5.2
13.6
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
FEATURES
GENERAL DESCRIPTION
In-lock detector
5-step analog-to-digital converter (3 bits in I2C-bus
mode)
15-bit programmable divider
Two pins are available between the mixer output and the
IF amplifier input to enable IF filtering for improved signal
handling.
Low radiation
Small size
The TDA6502A and TDA6503A differ from the TDA6502
and TDA6503 by the UHF port protocol in the I2C-bus
mode (see Tables 3 and 4).
2000 Mar 16
APPLICATIONS
Philips Semiconductors
Preliminary specification
I2C-bus format
2000 Mar 16
DATA WORD
REFERENCE
DIVIDER(1)
FREQUENCY
STEP
18-bit
64
62.50 kHz
19-bit
128
31.25 kHz
27-bit
programmable
programmable
3.2
Note
3.1
TDA6502; TDA6502A;
TDA6503; TDA6503A
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCC
supply voltage
operating
4.5
5.5
ICC
supply current
71
mA
fXTAL
4.0
MHz
Io(PMOS)
note 1
30
mA
Ptot
note 2
520
mW
Tstg
IC storage temperature
40
+150
Tamb
ambient temperature
20
+85
fRF
RF frequency
VHF band
40
800
MHz
UHF band
200
900
MHz
VHF band
20
dB
UHF band
32
dB
VHF band
7.5
dB
UHF band
dB
VHF band
110
dBV
UHF band
110
dBV
GV
voltage gain
NF
noise figure
Vo
Notes
1. One buffer on, Io = 25 mA; two buffers on, maximum sum of Io = 30 mA.
2. The power dissipation is calculated as follows:
2
( 0.5 33V )
P tot = V CC ( I CC I o ) + V P(sat) I o + --------------------------------22 k
where:
VP(sat) = output saturation voltage on the buffer output
Io = source current for one buffer output.
5
ORDERING INFORMATION
TYPE
NUMBER
TDA6502;
TDA6502A;
TDA6503;
TDA6503A
2000 Mar 16
PACKAGE
NAME
DESCRIPTION
VERSION
SSOP28
SOT341-1
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
BLOCK DIAGRAM
VCC
IFFIL1 IFFIL2
5 (24) 6 (23)
VHFIN
19 (10)
(5) 24
3 (26)
VHF
OSCILLATOR
VHF
MIXER
RF INPUT
VHF
BS
BS
BS
(7) 22
(6) 23
RFGND
UHFIN1
UHFIN2
4 (25)
TDA6502
TDA6502A
(TDA6503)
(TDA6503A)
IF
PREAMPLIFIER
(9) 20
(1) 28
1 (28)
(2) 27
RF INPUT
UHF
2 (27)
UHF
MIXER
BS
UHF
OSCILLATOR
(4) 25
BS
BS
(3) 26
(13) 16
XTAL
18 (11)
XTAL
OSCILLATOR
4 MHz
REFERENCE
DIVIDER
64, 80, 128
RSA
fREF
FL
CL
DA
SW
14 (15)
13 (16)
11 (18)
SCL
SDA
SW
CHARGE
PUMP
UHFOSCOC2
UHFOSCOC1
UHFOSCIB1
CP
T0, T1, T2 CP
FL
CONTROL
REGISTER
CP
T2
T1
fREF
1/2fDIV
T0 RSA RSB OS
PORT
REGISTER
12 (17)
UHF
GATE
BS
(8) 21
T0, T1, T2
15 (14)
9 (20)
8 (21)
7 (22)
10 (19)
FCE527
PVHFH
LOCK/ADC
PUHF
2000 Mar 16
UHFOSCIB2
OS
15-BIT
FREQUENCY
REGISTER
3-BIT ADC
IFOUT
OPAMP
fDIV
FL
CE/AS
OSCGND
VT
IN-LOCK
DETECTOR
POWER-DOWN
DETECTOR
VHFOSCIB
(12) 17
PHASE
COMPARATOR
RSB
15-BIT
PROGRAMMABLE
DIVIDER
VHFOSCOC
FMST
PVHFL
GND
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
PINNING
PIN
SYMBOL
UHFIN1
TDA6502;
TDA6502A
TDA6503;
TDA6503A
28
DESCRIPTION
UHF RF input 1
UHFIN2
27
UHF RF input 2
VHFIN
26
VHF RF input
RFGND
25
RF ground
IFFIL1
24
IF filter output 1
IFFIL2
23
IF filter output 2
PVHFL
22
PVHFH
21
PUHF
20
FMST
10
19
SW
11
18
CE/AS
12
17
DA
13
16
CL
14
15
LOCK/ADC
15
14
CP
16
13
VT
17
12
XTAL
18
11
VCC
19
10
supply voltage
IFOUT
20
IF output
GND
21
digital ground
VHFOSCIB
22
OSCGND
23
oscillator ground
VHFOSCOC
24
UHFOSCIB1
25
UHFOSCOC1
26
UHFOSCOC2
27
UHFOSCIB2
28
2000 Mar 16
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
handbook, halfpage
handbook, halfpage
UHFIN1 1
28 UHFOSCIB2
UHFOSCIB2
28 UHFIN1
UHFIN2
27 UHFOSCOC2
UHFOSCOC2
27 UHFIN2
VHFIN
26 UHFOSCOC1
UHFOSCOC1
26 VHFIN
RFGND
25 UHFOSCIB1
UHFOSCIB1
25 RFGND
IFFIL1
24 VHFOSCOC
VHFOSCOC
24 IFFIL1
IFFIL2
23 OSCGND
OSCGND
23 IFFIL2
PVHFL
VHFOSCIB
PVHFH
GND
PUHF
IFOUT
20 PUHF
19 VCC
VCC 10
19 FMST
18 XTAL
XTAL 11
VHFOSCIB
TDA6502 22
TDA6502A 21 GND
20 IFOUT
FMST 10
SW 11
22 PVHFL
TDA6503
TDA6503A 21 PVHFH
18 SW
CE/AS 12
17 VT
VT 12
17 CE/AS
DA 13
16 CP
CP 13
16 DA
CL 14
15 LOCK/ADC
LOCK/ADC 14
15 CL
FCE571
FCE570
Fig.2
Fig.3
FUNCTIONAL DESCRIPTION
8.1
The device is controlled via the I2C-bus or the 3-wire bus, depending on the voltage applied to pin SW (see Table 2).
A LOW level on pin SW enables the I2C-bus: pins CE/AS, DA and CL are used as address selection (AS), serial data
(SDA) and serial clock (SCL) input respectively.
A HIGH level on pin SW enables the 3-wire bus: pins CE/AS, DA and CL are used as chip enable (CE), data and clock
inputs respectively.
Table 2
TDA6502;
TDA6502A
TDA6503;
TDA6503A
SW
11
18
CE/AS
12
17
enable input
DA
13
16
data input
CL
14
15
clock input
LOCK/ADC
15
14
SYMBOL
2000 Mar 16
Philips Semiconductors
Preliminary specification
8.2.1
WRITE MODE
TDA6502; TDA6502A;
TDA6503; TDA6503A
BYTE
MSB
Address byte
ADB
Divider byte 1
Divider byte 2
LSB
MA0
R/W = 0
N10
N9
N8
N2
N1
N0
T0
RSA
RSB
OS
FMST
PUHF
PVHFH
PVHFL
MA1
DB1
N14
N13
N12
N11
DB2
N7
N6
N5
N4
N3
Control byte
CB
CP
T2
T1
Band-switch byte
BB
Table 4
BYTE
MSB
LSB
Address byte
ADB
MA1
MA0
R/W = 0
Divider byte 1
DB1
N14
N13
N12
N11
N10
N9
N8
Divider byte 2
DB2
N7
N6
N5
N4
N3
N2
N1
N0
Control byte
CB
CP
T2
T1
T0
RSA
RSB
OS
Band-switch byte
BB
PUHF
FMST
PVHFH
PVHFL
2000 Mar 16
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
DESCRIPTION
R/W
N14 to N0
CP
T2, T1 and T0
OS
dont care
Table 6
MA1
MA0
0 V to 0.1VCC
0.4VCC to 0.6VCC
0.9VCC to 1.0VCC
Table 7
T2
T1
T0
TEST MODE
normal mode
Notes
1. This is the default mode at Power-on reset.
2. The ADC input cannot be used when these test modes are active; see Section 8.2.3 for more information.
2000 Mar 16
10
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
RSA
RSB
80
50
128
31.25
64
62.5
8.2.3
READ MODE
The read mode is defined by the address byte ADB with bit R/W = 1 (see Table 9).
After the slave address has been recognized, the device generates an acknowledge pulse and status byte SB is
transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL line. A second data
byte can be read from the device if the microcontroller generates an acknowledge on the SDA line (master acknowledge).
End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the
microcontroller to generate a STOP condition.
Bit POR is set to logic 1 at power-on. The bit is reset when an end-of-data is detected by the device (end of a read
sequence). Control of the loop is made possible with bit FL which indicates when the loop is locked (bit FL = 1)
A built-in ADC input is available on pin LOCK/ADC (I2C-bus mode only). This converter can be used to apply AFC
information to the microcontroller of the IF section of the television.
Table 9
NAME
Address byte
Status byte
BYTE
MSB(1)
LSB
ADB
MA1
MA0
R/W = 1
SB
POR
FL
A2
A1
A0
Note
1. MSB is transmitted first.
Table 10 Description of the bits used in Table 9
BIT
DESCRIPTION
R/W
POR
FL
in-lock flag:
logic 0: loop is not locked
logic 1: loop is locked
ready flag:
logic 0: mode after Power-on reset (bit T2 = 0, bit T1 = 0 and bit T0 = 1) and the PLL is locked
logic 1: in other conditions
A2, A1 and A0
2000 Mar 16
11
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
A1
A0
0 to 0.15VCC
0.15VCC to 0.30VCC
0.30VCC to 0.45VCC
0.45VCC to 0.60VCC
0.60VCC to 1.00VCC
Note
1. Accuracy is 0.03 VCC.
8.2.4
POWER-ON RESET
The power-on detection threshold voltage VPOR is set to 3.2 V at room temperature. Below this threshold the device is
reset to the power-on state.
At power-on state the following actions take place:
The charge pump current is set to 280 A
The tuning voltage output is disabled
The test bits T2, T1 and T0 are set to logic 001
The divider bit RSB is set to logic 1
Port register UHF is off, which means that the UHF oscillator and the UHF mixer are switched off. Consequently, the
VHF oscillator and the VHF mixer are switched on. Port registers VHFL and VHFH are off, which means that the VHF
tank circuit is operating in the VHF low sub-band. The tuning amplifier is switched off until the first transmission. In that
case, the tank circuit is supplied with the maximum tuning voltage. The oscillator is therefore operating at the end of
the VHF low sub-band.
Table 12 Default setting of the bits at Power-on reset
BITS
NAME
BYTE
MSB
LSB
Address byte
ADB
MA1
MA0
Divider byte 1
DB1
Divider byte 2
DB2
Control byte
CB
BB
2000 Mar 16
12
Philips Semiconductors
Preliminary specification
8.3.1
TDA6502; TDA6502A;
TDA6503; TDA6503A
POWER-ON RESET
The first four bits control the PMOS ports and are loaded
into the internal band-switch register on the 5th rising edge
of the clock pulse.
2000 Mar 16
13
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
INVALID
DATA
BAND-SWITCH
DATA
FMST
PUHF
FREQUENCY
DATA
INVALID
DATA
PVHFL
PVHFH
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
DA
18
CL
CE
LOAD BAND-SWITCH
REGISTER
LOAD FREQUENCY
REGISTER
FCE572
handbook, full
pagewidth
INVALID
BAND-SWITCH
DATA
DATA
FMST
PUHF
FREQUENCY
DATA
INVALID
DATA
PVHFL
PVHFH
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
DA
19
CL
CE
LOAD BAND-SWITCH
REGISTER
LOAD FREQUENCY
REGISTER
FCE573
2000 Mar 16
14
Philips Semiconductors
Preliminary specification
handbook, fullINVALID
pagewidth
BAND-SWITCH
DATA
DATA
FMST
PUHF
TDA6502; TDA6502A;
TDA6503; TDA6503A
FREQUENCY
DATA
INVALID
DATA
PVHFL
PVHFH
N2
N1
N0
19
20
CP
T2
T1
T0 RSA RSB OS
DA
27
CL
CE
LOAD BAND-SWITCH
REGISTER
LOAD FREQUENCY
REGISTER
LOAD CONTROL
REGISTER
FCE574
2000 Mar 16
15
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); note 1.
PIN
SYMBOL
VCC
PARAMETER
TDA6502; TDA6503;
TDA6502A TDA6503A
19
10
MIN.
0.3
DC supply voltage
MAX.
UNIT
+6
VPn
7 to 10
19 to 22
0.3
VCC +0.3
IPn
7 to 10
19 to 22
+30
mA
VCP
16
13
0.3
VCC +0.3
VSW
11
18
0.3
VCC+ 0.3
VVT
17
12
0.3
+35
VLOCK/ADC
15
14
0.3
VCC +0.3
VCL
14
15
0.3
+6
VDA
13
16
0.3
+6
IDA
13
16
+10
mA
VCE/AS
12
17
0.3
+6
VXTAL
18
11
0.3
VCC +0.3
1 to 6,
19 to 28
1 to 10,
23 to 28
10
mA
tsc(max)
10
Tstg
storage temperature
40
+150
Tamb
ambient temperature
20
+85
Tj
junction temperature
150
IO(n)
(I2C-bus
mode)
Note
1. Maximum ratings can not be exceeded, not even momentarily without causing irreversible IC damage. Maximum
ratings can not be accumulated.
10 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
2000 Mar 16
PARAMETER
CONDITIONS
in free air
16
TYP.
UNIT
110
K/W
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
11 CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply; Tamb = 25 oC
VCC
supply voltage
ICC
supply current
4.5
5.0
5.5
71
78
mA
103
113
mA
111
122
mA
3.2
at VCC = 5 V
PLL part; VCC = 4.5 to 5.5 V; Tamb = 20 to +85 C; unless otherwise specified
FUNCTIONAL RANGE
VPOR
divider ratio
64
32767
64
16383
fXTAL
RXTAL = 25 to 300
4.0
MHz
ZXTAL
input impedance
(absolute value)
fXTAL = 4 MHz
600
1200
leakage current
10
VPn(sat)
0.25
0.4
200
VUNLOCK
0.4
0.8
VLOCK
output voltage
0.2
0.40
VADC
see Table 11
VCC
IADC(H)
VADC = VCC
10
IADC(L)
VADC = 0 V
10
1.5
VSW(H)
VCC
ISW(H)
VSW = VCC
10
ISW(L)
VSW = 0 V
100
2000 Mar 16
17
Philips Semiconductors
Preliminary specification
PARAMETER
TDA6502; TDA6502A;
TDA6503; TDA6503A
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1.5
VCE/AS(H)
5.5
ICE/AS(H)
VCE/AS = 5.5 V
10
ICE/AS(L)
VCE/AS = 0 V
10
1.5
VCL(H),
VDA(H)
5.5
10
10
10
10
VDA = 5.5 V
10
VDA(H)
0.4
400
kHz
clock frequency
CP = 1
280
ICP(L)
CP = 0
60
ICP(leak)
T2 = 0; T1 = 1
15
0.5
+15
nA
OS = 1; tuning supply is 33 V
10
0.2
32.7
VVT
Mixer/oscillator part; VCC = 5 V; Tamb = 25 oC; measurements related to the measurement circuit (see Fig.19)
VHF MIXER (INCLUDING IF PREAMPLIFIER)
fRF(o)
RF operational frequency
800
MHz
fRF
RF frequency
note 1
55.25
361.25
MHz
Gv
voltage gain
17.5
20
22.5
dB
NF
noise figure
2000 Mar 16
40
17.5
20
22.5
dB
7.5
10
dB
7.5
10
dB
7.5
10
dB
18
Philips Semiconductors
Preliminary specification
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
110
dBV
107
110
dBV
83
dBV
optimum source
fRF = 50 MHz
conductance for noise figure fRF = 150 MHz
0.7
mS
0.9
mS
1.5
mS
0.3
mS
0.4
mS
1.35
pF
600
MHz
Vi
gos
Ci
MIN.
107
Vo
gi
TDA6502; TDA6502A;
TDA6503; TDA6503A
input conductance
input capacitance
VHF OSCILLATOR
fOSC(o)
oscillator operational
frequency
fOSC
oscillator frequency
fOSC(V)
60
101
407
MHz
60
kHz
110
kHz
fOSC(T)
1600
kHz
fOSC(t)
400
kHz
OSC
105
dBc/Hz
RSC
15
30
mV
900
MHz
note 3
RF operational frequency
fRF
RF frequency
Gv
voltage gain
NF
Vo
Vi
2000 Mar 16
200
note 1
367.25
801.25
MHz
29
32
35
dB
29
32
35
dB
dB
dB
107
110
dBV
107
110
dBV
85
dBV
19
Philips Semiconductors
Preliminary specification
PARAMETER
TDA6502; TDA6502A;
TDA6503; TDA6503A
CONDITIONS
MIN.
TYP.
26
MAX.
UNIT
28
8.5
nH
nH
1000
MHz
UHF OSCILLATOR
fOSC(o)
oscillator operational
frequency
fOSC
oscillator frequency
fOSC(V)
300
413
847
MHz
35
kHz
100
kHz
fOSC(T)
500
kHz
fOSC(t)
120
kHz
OSC
105
dBc/Hz
RSC
15
30
mV
60
MHz
note 3
IF PREAMPLIFIER
IF
IF operational frequency
S22
Zo
output impedance
(RS + jLS)
30
magnitude; see Fig.9
12.8
dB
0.2
degree
80
0.5
nH
16
20
dBV
INTxtal
crystal oscillator
interferences rejection
60
dBc
INTref
reference frequency
rejection
60
dBc
INTch6
channel 6 beat
tbf
54
dBc
INTchA-5
tbf
60
dBc
Notes
1. The RF frequency range is defined by the oscillator frequency range and the IF frequency.
2. This is the level of the RF signal (100% amplitude modulated with 11.89 kHz) that causes a 750 Hz frequency
deviation on the oscillator signal; it produces sidebands 30 dB below the level of the oscillator signal.
3. Limits are related to the tank circuits used in Fig.19; frequency bands may be adjusted by the choice of external
components.
2000 Mar 16
20
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
4. The frequency shift is defined as a change in oscillator frequency when the supply voltage varies from
VCC = 5 to 4.75 V (4.5 V) or from VCC = 5 to 5.25 V (5.5 V). The oscillator is free running during this measurement.
5. The frequency drift is defined as a change in oscillator frequency when the ambient temperature varies from
Tamb = 25 to 50 C or from Tamb = 25 to 0 C. The oscillator is free running during this measurement.
6. Switch-on drift is defined as the change in oscillator frequency between 5 s and 15 min after switch-on. The oscillator
is free running during this measurement.
7. The ripple susceptibility is measured for a 500 kHz ripple at the IF output using the measurement circuit of Fig.19;
the level of the ripple signal is increased until a difference of 53.5 dB occurs between the IF carrier fixed at 100 dBV
and the sideband components.
8. This is the level of divider interferences close to the IF frequency. For example channel C: fOSC = 179 MHz,
1 f
4 OSC = 44.75 MHz. The VHFIN input must be left open (i.e. not connected to any load or cable); The UHFIN1 and
UHFIN2 inputs are connected to a hybrid.
9. Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator. The rejection has to be
greater than 60 dB for an IF output signal of 100 dBV.
10. The reference frequency rejection is the level of reference frequency sidebands related to the sound sub-carrier.
11. Channel 6 beat is the interfering product of fRF(pix) + fRF(snd) fOSC of channel 6 at 42 MHz.
12. Channel A-5 beat is the interfering product of fRF(pix), fIF and fOSC of channel A-5: fbeat = 45.5 MHz.
The possible mechanisms are: fOSC 2 fIF or 2 fRF(pix) fOSC. For the measurement: VRF = 80 dBV.
0.5
0.2
5
10
j
10
0.5
0.2
40 MHz
0
+j
10
400 MHz
5
0.2
0.5
1
FCE528
Fig.7 Input admittance (S11) of the VHF mixer input (40 to 400 MHz); Y0 = 20 mS.
2000 Mar 16
21
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
0.5
860 MHz
0.2
350 MHz
10
+j
0.2
0.5
10
j
10
5
0.2
0.5
1
FCE529
Fig.8 Input impedance (S11) of the UHF mixer input (350 to 860 MHz); Z0 = 50 .
0.5
0.2
5
10
+j
0
0.2
0.5
20 MHz
10
100 MHz
10
5
0.2
0.5
1
FCE530
2000 Mar 16
22
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
12 TIMING CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
UNIT
see Fig.10
tSU;DA
see Fig.10
tHD;DA
see Fig.10
tSU;ENCL
see Fig.10
10
tHD;ENDA
see Fig.10
tEN
see Fig.11
10
tHD;ENCL
see Fig.11
INVALID
DATA
DA
INVALID
DATA
LSB
MSB
CL
tHIGH
tSU;DA
tHD;DA
CE
tSU;ENCL
tHD;ENDA
FCE575
handbook, halfpage
tEN
CE
CL
tHD;ENCL
FCE576
2000 Mar 16
23
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
Test circuits
signal
source
50
27
VHFIN
Vmeas V
50
IFOUT
D.U.T.
Vi
spectrum
analyzer
Vo
50
V'meas
RMS
voltmeter
FCE577
I1
BNC
I3
PCB
C1
L1
BNC
C2
PCB
C3
plug
plug
I2
RIM-RIM
RIM-RIM
C4
(a)
(b)
FCE578
C1 = 9 pF
C2 = 15 pF
L1 = 7 turns ( 5.5 mm, wire = 0.5 mm)
l1 = semi rigid cable (RIM) of 5 cm long
(semi rigid cable (RIM); 33 dB/100 m; 50 ; 96 pF/m).
C3 = 5 pF
C4 = 25 pF
l2 = semi rigid cable (RIM): 30 cm long
l3 = semi rigid cable (RIM) of 5 cm long
(semi rigid cable (RIM); 33 dB/100 m; 50 ; 96 pF/m).
2000 Mar 16
24
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
27
NOISE
SOURCE
VHFIN
RIM
BNC
INPUT
CIRCUIT
IFOUT
NOISE
FIGURE
METER
D.U.T.
FCE579
FILTER
50
AM = 30%
2 kHz
unwanted
signal
source
eu
27
A
VHFIN
18 dB
attenuator
IFOUT
45.75 MHz
HYBRID
D.U.T.
Vo
V Vmeas
modulation
analyzer
50
50
B
ew
wanted
signal
source
D
50
RMS
voltmeter
FCE580
50 + 27
Vo = Vmeas ------------------50
Wanted output signal at fRF(w) = 55.25 (361.25) MHz; Vo(w) = 100 dBV.
Measuring the level of the unwanted output signal Vo(u) causing 0.3% AM modulation in the wanted output signal; fRF(u) = 59.75 (366.75) MHz.
fOSC = 101 (407) MHz.
Filter characteristics: fc = 45.75 MHz, f3 dB(BW) = 1.4 MHz, f30 dB(BW) = 3.1 MHz.
2000 Mar 16
25
Philips Semiconductors
Preliminary specification
50
TDA6502; TDA6502A;
TDA6503; TDA6503A
signal
source
27
A
Vmeas V
50
Vi
UHFIN1 IFOUT
HYBRID
D.U.T.
spectrum
analyzer
Vo
V'meas
UHFIN2
RMS 50
voltmeter
FCE581
27
NOISE
SOURCE
UHFIN
HYBRID
IFOUT
NOISE
FIGURE
METER
D.U.T.
UHFIN
50
FCE582
2000 Mar 16
50
26
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
FILTER
AM = 30%
50
2 kHz
unwanted
signal
source
eu
ew
27
UHFIN
IFOUT
45.75 MHz
HYBRID
HYBRID
50
wanted
signal
source
18 dB
attenuator
D
50
D.U.T.
Vo
V Vmeas
modulation
analyzer
50
UHFIN
RMS
voltmeter
50
FCE583
50 + 27
Vo = Vmeas ------------------50
Wanted output signal at fRF(w) = 367.25 (801.25) MHz; Vo(w) = 100 dBV.
Measuring the level of the unwanted output signal Vo(u) causing 0.3% AM modulation in the wanted output signal; fRF(u) = 371.25 (805.75) MHz.
fOSC = 413 (847) MHz.
Filter characteristics: fc = 45.75 MHz, f3 dB(BW) = 1.4 MHz, f30 dB(BW) = 3.1 MHz.
2000 Mar 16
27
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W3
C2
4.7 nF
UHFIN2
C3
4.7 nF
C4
VHFIN
IFFIL1 5(24)
24(5)
IFFIL2
23(6) OSCGND
R16 330
FMST
(TDA6503/3A)
9(20)
20(9)
19(10)
10(19)
18(11) XTAL
SW 11(18)
DA
VCC
CL
CON1
TR1
D2
82 pF
L3
C17
4.7 nF
C16
BA792
10 k C6
C14
4.7 nF
C18 4.7 nF
L5
VCC
Y1
13(16)
16(13)
14(15)
100 nF
15(14) LOCK/ADC
C21
C20
R9
R8 22 nF
VHF-HIGH
680
VHF-LOW
3.9 k
18 pF
CON3
R12
J1
R14
2.2 k
C23
10 nF
R13
22 k
C22
330 pF
R22
330
R11
27
R26
6.8 k
R25
C26
10 F
(16 V)
1 k
LOCK/ADC
for test
purpose only
R24
TR2
GND
VS
LOCK
+5 V
EN/AS
BC847B
FCE481
J2 04 03 02 01
Preliminary specification
01 02 03 04 05 06 J3
+33 V
68 k
RIPPLE
D3
3.9 k
R10
C19 4.7 nF
12 k
22 k
R7
2 pF
17(12) VT
R19
330
R6 5.6
C15
TDA6502; TDA6502A;
TDA6503; TDA6503A
C27
10 F
(16 V)
BB178
C13
L2
12(17)
CP
R5
+5 V
BC847B
R20
330
R21
330
CLOCK
GND
DATA
28
CE/AS
22 k
C11 1.2 pF
IFOUT
VCC
C12
27 pF
R2 27
VHFOSCIB
8(21)
L1
C10 1.2 pF
VHFOSCOC
21(8) GND
CON4
UHFOSCIB1
R3
22 k
D1
BB179 R4
C9 1.2 pF
2 pF
6(23)
PUHF
R17 330
UHFOSCOC1
25(4)
PVHFH
R18 330
UHFOSCIB2
RFGND 4(25)
PVHFL
R15 330
27(2)
26(3)
L4
15 pF
D4
LED
D5
LED
D6
LED
D7
LED
2(27)
C8 1.2 pF
UHFOSCOC2
3(26)
15 pF
C5
28(1)
Philips Semiconductors
4.7 nF
1(28)
Measurement circuit
W2
UHFIN1
13.2
2000 Mar 16
C1
W1
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
COMPONENT
VALUE
VALUE
R15
330
C1
4.7 nF
R16
330
C2
4.7 nF
R17
330
C3
4.7 nF
R18
330
C4
15 pF
R19
330
C5
15 pF
R20
330
C6
22 nF
R21
330
C8
1.2 pF (N750)
R22
330
C9
1.2 pF (N750)
R24
68 k
C10
1.2 pF(N750)
R25
1 k
C11
1.2 pF (N750)
R26
6.8 k
C12
27 pF (N750)
C13
2 pF (N750)
C14
2 pF (N750)
C15
82 pF (N750)
D1
BB179
C16
4.7 nF
D2
BB178
C17
4.7 nF
D3
BA792
C18
4.7 nF
IC
C19
4.7 nF
TDA6502; TDA6502A
TDA6503; TDA6503A
C20
18 pF
C21
100 nF
C22
330 pF
C23
10 nF
L1
C26
10 F (16 V, electrolytic)
L2
C27
10 F (16 V, electrolytic)
L3
L5
VALUE
Note
COMPONENT
VALUE
R2
27
R3
22 k
R4
22 k
R5
22 k
R6
5.6
R7
10 k
R8
680
R9
3.9 k
R10
3.9 k
R11
27
R12
12 k
R13
22 k
R14
2.2 k
2000 Mar 16
VALUE
VALUE
2 x 5 turns
Note
1. Coil type: TOKO 7kN; material: 113 kN; screw core:
03-0093; pot core: 04-0026.
Table 18 Crystal
COMPONENT
Y1
29
VALUE
4 MHz
Philips Semiconductors
Preliminary specification
13.5
COMPONENT
VALUE
TR1
BC847B
TR2
BC847B
TDA6502; TDA6502A;
TDA6503; TDA6503A
Examples of I2C-bus data format sequences for
TDA6502 and TDA6503
13.3
Tuning amplifier
P = STOP bit.
Conditions:
fxtal = 4 MHz
N = 1600
fosc = 100 MHz
fstep = 62.5 kHz
Port register VHFL is on to switch-on band VHF low
Crystal oscillator
ICP = 280 A.
Table 20 Complete sequence with first the divider bytes (first data bit = 0)
START
ADDRESS
ACK
BYTE
C2
DIVIDER
BYTE 1
ACK
DIVIDER
BYTE 2
ACK
06
40
BANDSWITCH
BYTE
CONTROL
ACK
BYTE
CE
09
ACK STOP
A
Table 21 Complete sequence with first the control and band-switch bytes (first data bit = 1)
START
ADDRESS
CONTROL
ACK
ACK
BYTE
BYTE
C2
CE
BANDSWITCH
BYTE
ACK
DIVIDER
BYTE 1
ACK
DIVIDER
BYTE 2
09
06
40
ACK STOP
A
ADDRESS BYTE
ACK
DIVIDER BYTE 1
ACK
DIVIDER BYTE 2
C2
06
40
ACK STOP
A
Table 23 Sequence with control and band-switch bytes only (first data bit = 1)
START
ADDRESS BYTE
ACK
CONTROL BYTE
ACK
BAND-SWITCH BYTE
C2
CE
09
ACK STOP
A
ADDRESS BYTE
ACK
CONTROL BYTE
C2
CE
2000 Mar 16
30
ACK STOP
A
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
ADDRESS BYTE
ACK
STATUS BYTE
C3
XX
ACK STOP
X
ADDRESS BYTE
ACK
STATUS BYTE
ACK
STATUS BYTE
C3
XX
XX
13.6
13.6.1
ACK STOP
X
Examples of 3-wire bus data format sequences for TDA6502 and TDA6503
18-BIT SEQUENCE
Conditions:
fosc = 800 MHz
Port register PUHF is on.
Table 27 18-bit sequence
PUHF FMST PVHFH PVHFL
1
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
The reference divider is automatically set to 64 assuming that bit RSB has been set to logic 1 at power-on. If bit RSB has
been set to logic 0, in a previous 27-bit sequence, the reference divider will still be set at 80. In this event, the 18-bit
sequence has to be adapted to the 80 divider ratio.
13.6.2
19-BIT SEQUENCE
Conditions:
fosc = 650 MHz
Port register PUHF is on.
Table 28 19-bit sequence
PUHF FMST PVHFH PVHFL N14
1
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
The reference divider is automatically set to 128 assuming that bit RSB has been set to logic 1 at power-on. If bit RSB
has been set to logic 0 in a previous 27-bit sequence, the reference divider will still be set at 80. In this event, the 19-bit
sequence has to be adapted to the 80 divider ratio.
2000 Mar 16
31
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
27-BIT SEQUENCE
Conditions:
fosc = 750 MHz
Port register PUHF is on
Reference divider is set at 80
ICP = 60 A
No test function.
Table 29 27-bit sequence
FREQUENCY DATA BITS
PORT BITS
1 0 0 0
14 13 12 11 10
X CP T2 T1 T0 RSA RSB OS
To change the oscillator frequency to 600 MHz in 50 kHz steps a 19-bit sequence or an 18-bit sequence can be used.
The charge pump current remains at 60 A.
Table 30 Changing frequency with a 19-bit sequence
FREQUENCY DATA BITS
PORT BITS
1
14
13
12
11
10
2000 Mar 16
13
12
11
10
32
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
PIN
SYMBOL
TDA6502;
TDA6502A
TDA6503;
TDA6503A
VHF
UHF
UHFIN1
28
1.0 V
UHFIN2
27
1.0 V
EQUIVALENT CIRCUIT(1)
(28)
(27)
FCE584
VHFIN
26
3
(26)
FCE585
RFGND
25
0.0 V
0.0 V
4
(25)
FCE586
IFFIL1
24
3.6 V
3.6 V
IFFIL2
23
3.6 V
3.6 V
(24) 5
6 (23)
FCE587
PVHFL
22
n.a. or 4.8 V
n.a.
PVHFH
21
4.8 V or n.a.
n.a.
n.a.
4.8 V
PUHF
20
FMST
10
19
(22)
(21)
10
(20)
(19)
FCE588
2000 Mar 16
33
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
DC VOLTAGE
(AVERAGE VALUE)(2)
PIN
SYMBOL
SW
TDA6502;
TDA6502A
TDA6503;
TDA6503A
VHF
UHF
11
18
5.0 V
5.0 V
EQUIVALENT CIRCUIT(1)
11
(18)
FCE189
CE/AS
12
17
1.25 V
1.25 V
12
(17)
FCE191
DA
13
16
13
(16)
FCE190
CL
14
15
14
(15)
FCE192
LOCK/ADC
15
14
4.6 V
4.6 V
15
(14)
FCE193
2000 Mar 16
34
Philips Semiconductors
Preliminary specification
PIN
SYMBOL
CP
TDA6502;
TDA6502A
TDA6503;
TDA6503A
VHF
UHF
16
13
1V
1V
TDA6502; TDA6502A;
TDA6503; TDA6503A
EQUIVALENT CIRCUIT(1)
16
(13)
FCE194
VT
17
12
VVT
VVT
17
(12)
FCE589
XTAL
18
11
2.6 V
2.6 V
18
(11)
FCE590
VCC
19
10
5.0 V
5.0 V
IFOUT
20
2.1 V
2.1 V
supply voltage
20
(9)
FCE591
GND
21
0.0 V
0.0 V
21
(8)
FCE592
2000 Mar 16
35
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
DC VOLTAGE
(AVERAGE VALUE)(2)
PIN
SYMBOL
OSCGND
TDA6502;
TDA6502A
TDA6503;
TDA6503A
VHF
UHF
23
0.0 V
0.0 V
EQUIVALENT CIRCUIT(1)
23
(6)
FCE593
VHFOSCIB
22
1.8 V
VHFOSCOC
24
3.0 V
24
(5)
22
(7)
FCE594
UHFOSCIB1
25
1.9 V
UHFOSCOC1
26
2.9 V
UHFOSCOC2
27
2.9 V
UHFOSCIB2
28
1.9 V
(2)
(3)
27
26
25
28
(4)
(1)
FCE595
Notes
1. The pin numbers in parenthesis represent the TDA6503 and TDA6503A.
2. Measured in circuit of Fig.19.
2000 Mar 16
36
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
15 PACKAGE OUTLINE
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
A
X
c
HE
v M A
Z
28
15
Q
A2
(A 3)
A1
pin 1 index
Lp
L
1
14
bp
detail X
w M
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (1)
HE
Lp
Z (1)
mm
2.0
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
10.4
10.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.1
0.7
8
0o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
SOT341-1
2000 Mar 16
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
99-12-27
MO-150
37
Philips Semiconductors
Preliminary specification
16 SOLDERING
16.1
TDA6502; TDA6502A;
TDA6503; TDA6503A
Reflow soldering
16.3
16.4
Wave soldering
2000 Mar 16
Manual soldering
38
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
not suitable
suitable(2)
not
suitable
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Mar 16
39
Philips Semiconductors
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
17 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2000 Mar 16
40
Philips Semiconductors
Preliminary specification
2000 Mar 16
41
TDA6502; TDA6502A;
TDA6503; TDA6503A
Philips Semiconductors
Preliminary specification
2000 Mar 16
42
TDA6502; TDA6502A;
TDA6503; TDA6503A
Philips Semiconductors
Preliminary specification
2000 Mar 16
43
TDA6502; TDA6502A;
TDA6503; TDA6503A
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
753504/02/pp44
Mar 16