a

APPLICATIONS
Battery Powered Instruments
Hand-Held Scopemeters
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FUNCTIONAL BLOCK DIAGRAM

ENCA

AD9288

TIMING

AINA

T/H

AINA

ADC

REFINA
REFOUT

AINB

T/H

AINB
ENCB

The AD9288 is a dual 8-bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits and is
optimized for low cost, low power, small size and ease of use.
The product operates at a 100 MSPS conversion rate with outstanding dynamic performance over its full operating range.
Each channel can be operated independently.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and an encode clock for full-performance operation. No
external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS compatible
and a separate output power supply pin supports interfacing
with 3.3 V or 2.5 V logic.

ADC

D7AD0A
SELECT #1
SELECT #2

REF

REFINB
8

TIMING

VD

GENERAL DESCRIPTION

OUTPUT REGISTER

VDD

GND

OUTPUT REGISTER

FEATURES
Dual 8-Bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC
Low Power: 90 mW at 100 MSPS per Channel
On-Chip Reference and Track/Holds
475 MHz Analog Bandwidth Each Channel
SNR = 47 dB @ 41 MHz
1 V p-p Analog Input Range Each Channel
Single +3.0 V Supply Operation (2.7 V3.6 V)
Standby Mode for Single Channel Operation
Twos Complement or Offset Binary Output Mode
Output Data Alignment Mode

8-Bit, 40/80/100 MSPS

Dual A/D Converter
AD9288

DATA FORMAT
SELECT
8

D7BD0B

VDD

The encode input is TTL/CMOS compatible and the 8-bit

digital outputs can be operated from +3.0 V (2.5 V to 3.6 V)
supplies. User-selectable options are available to offer a combination of standby modes, digital data formats and digital data
timing schemes. In standby mode, the digital outputs are driven
to a high impedance state.
Fabricated on an advanced CMOS process, the AD9288 is available in a 48-lead surface mount plastic package (7 7 mm,
1.4 mm LQFP) specified over the industrial temperature range
(40C to +85C).

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999

AD9288SPECIFICATIONS (V
Parameter

Temp

Test
Level

DD

= 3.0 V; VD = 3.0 V, Differential Input; External reference unless otherwise noted.)

AD9288BST-100
Min
Typ
Max

RESOLUTION

AD9288BST-80
Min
Typ
Max

DC ACCURACY
Differential Nonlinearity

0.5

8
0.5

I
VI
I
VI
VI
I
VI
VI
V
V

Input Capacitance
Analog Bandwidth, Full Power

Full
Full
+25C
Full
Full
Full
+25C
Full
+25C
+25C

V
V
I
VI
VI
VI
I
VI
V
V

SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulsewidth High (tEH)
Encode Pulsewidth Low (tEL)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Valid Time (tV)2
Output Propagation Delay (tPD)2

Full
+25C
+25C
+25C
+25C
+25C
Full
Full

VI
IV
IV
IV
V
V
VI
VI

DIGITAL INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance

Full
Full
Full
Full
+25C

VI
VI
VI
VI
V

2.0

Full
Full

VI
VI

2.45

Full
Full

VI
VI

180
6

218
11

171
6

207
11

+25C

20

20

+25C
+25C

V
V

2
2

+25C
+25C
+25C

I
I
I

47.5
47.5
47.0

No Missing Codes
Gain Error1
Gain Tempco1
Gain Matching
Voltage Matching
ANALOG INPUT
Input Voltage Range
(With Respect to AIN)
Common-Mode Voltage
Input Offset Voltage
Reference Voltage
Reference Tempco
Input Resistance

DIGITAL OUTPUTS
Logic 1 Voltage
Logic 0 Voltage

0.50

6
8

+1.25
+1.50
+1.25
+1.50

+25C
Full
+25C
Full
Full
+25C
Full
Full
+25C
+25C

Integral Nonlinearity

Guaranteed
2.5
+6
+8
80
1.5
15

35
1.2
7
5

512
200
10
40
1.25
130
10

0.50

6
8

+35

35

1.3

1.2

13
16

7
5

2
475

Guaranteed
2.5
+6
+8
80
1.5
15

512
200
10
40
1.25
130
10

0.5

+1.25
+1.50
+1.25
+1.50

0.50

6
8

+35

35

1.3

1.2

13
16

7
5

2
475

100

1.3
13
16

1
1000
1000

8.0
8.0

0
5
3.0
4.5

0
5
3.0
4.5

2.0

2.0

0.8
1
1

0.8
1
1

2.0

+35

40
1
1000
1000

5.0
5.0

0
5
3.0
4.5

+1.25
+1.50
+1.25
+1.50

Guaranteed
2.5
+6
+8
80
1.5
15

512
200
10
40
1.25
130
10

0.8
1
1

2.0

Units
Bits

2
475

80
1
1000
1000

4.3
4.3

AD9288BST-40
Min
Typ
Max

2.0

LSB
LSB
LSB
LSB
% FS
% FS
ppm/C
% FS
mV

mV p-p
mV
mV
mV
V
ppm/C
k
k
pF
MHz
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
V
V
A
A
pF

POWER SUPPLY
Power Dissipation4
Standby Dissipation4, 5
Power Supply Rejection Ratio
(PSRR)

2.45

2.45

0.05

0.05

V
V

156
6

189
11

mW
mW

20

mV/V

0.05

DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10.3 MHz
fIN = 26 MHz
fIN = 41 MHz

44

2
2

44

47.5
47

44

2
2

ns
ns

47.5

dB
dB
dB

REV. 0

AD9288
Parameter

Temp

Test
Level

AD9288BST-100
Min
Typ
Max

AD9288BST-80
Min
Typ
Max

AD9288BST-40
Min
Typ
Max

Units

DYNAMIC PERFORMANCE (Continued)

Signal-to-Noise Ratio (SINAD) (With Harmonics)
fIN = 10.3 MHz
+25C I
fIN = 26 MHz
+25C I
fIN = 41 MHz
+25C I
Effective Number of Bits
fIN = 10.3 MHz
+25C I
fIN = 26 MHz
+25C I
+25C I
fIN = 41 MHz
2nd Harmonic Distortion
+25C I
fIN = 10.3 MHz
fIN = 26 MHz
+25C I
+25C I
fIN = 41 MHz
3rd Harmonic Distortion
+25C I
fIN = 10.3 MHz
fIN = 26 MHz
+25C I
+25C I
fIN = 41 MHz
Two-Tone Intermod Distortion (IMD)
fIN = 10.3 MHz
+25C V

47
47
47

44

47

44

44

47
47
47

dB
dB
dB

7.5
7.5
7.5

7.0

7.5

7.0

7.0

7.5
7.5
7.5

Bits
Bits
Bits

70
70
70

55

70

55

55

70
70
70

dBc
dBc
dBc

60
60
60

55

60

55

52

60
60
60

dBc
dBc
dBc

60

dBc

60

60

NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference).
2
tV and t PD are measured from the 1.5 V level of the ENCODE input to the 10%/90% levels of the digital outputs swing. The digital output load during test is not to
exceed an ac load of 10 pF or a dc current of 40 A.
3
Digital supply current based on V DD = +3.0 V output drive with <10 pF loading under dynamic test conditions.
4
Power dissipation measured under the following conditions: f S = 100 MSPS, analog input is 0.7 dBFS, both channels in operation.
5
Standby dissipation calculated with encode clock in operation.
6
SNR/harmonics based on an analog input voltage of 0.7 dBFS referenced to a 1.024 V full-scale input range.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

EXPLANATION OF TEST LEVELS

VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . 0.5 V to VD + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . 55C to +125C
Storage Temperature . . . . . . . . . . . . . . . . . . 65C to +150C
Maximum Junction Temperature . . . . . . . . . . . . . . . +175C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150C

Test Level
I
100% production tested.
II 100% production tested at +25C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at +25C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes for
military devices.

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.

Table I. User Select Options

ORDERING GUIDE

Model

Temperature
Ranges

Package
Options

AD9288BST
-40, -80, -100
AD9288/PCB

40C to +85C
+25C

ST-48*
Evaluation Board

*ST = Thin Plastic Quad Flatpack (1.4 mm thick, 7 7 mm: LQFP).

S1

S2

User Select Options

0
0
1
1

0
1
0
1

Standby Both Channels A and B.

Standby Channel B Only.
Normal Operation (Data Align Disabled).
Data align enabled (data from both channels available on rising edge of Clock A. Channel B data is
delayed a 1/2 clock cycle).

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9288 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

WARNING!
ESD SENSITIVE DEVICE

AD9288
Aperture Delay

Aperture Uncertainty (Jitter)

D0A

D2A

D1A

D4A
D3A

The delay between a differential crossing of ENCODE and

ENCODE and the instant at which the analog input is sampled.
D6A
D5A

GND

D7A (MSB)

VD

ENCA
VDD

PIN CONFIGURATION

The sample-to-sample variation in aperture delay.

48 47 46 45 44 43 42 41 40 39 38 37

GND 1
AINA 2
AINA 3
DFS 4

Differential Nonlinearity

36 NC

PIN 1
IDENTIFIER

The deviation of any code from an ideal 1 LSB step.

35 NC
34 GND

Encode Pulsewidth/Duty Cycle

33 VDD

REFINA 5

Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these
specs define an acceptable Encode duty cycle.

32 GND

AD9288

REFOUT 6

31 VD
30 VD

TOP VIEW
(Not to Scale)

REFINB 7
S1 8

29 GND

S2 9

28 VDD

AINB 10

27 GND

AINB 11

26 NC

Integral Nonlinearity

GND 12

25 NC

The deviation of the transfer function from a reference line

measured in fractions of 1 LSB using a best straight line determined by a least square curve fit.

D0B

D1B

D3B
D2B

D5B
D4B

GND

(MSB) D7B
D6B

VD

ENCB
VDD

NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.

PIN FUNCTION DESCRIPTIONS

Pin No.

Name

1, 12, 16, 27, 29,

32, 34, 45
GND
2
AINA
3
AINA
4

DFS

REFINA

6
7

REFOUT
REFINB

S1

S2

10

AINB

11
13, 30, 31, 48
14
15, 28, 33, 46
1724
25, 26, 35, 36
3744
47

AINB
VD
ENCB
VDD
D7BD0B
NC
D0AD7A
ENCA

Description

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

Ground.
Analog Input for Channel A.
Analog Input for Channel A
(Complementary).
Data Format Select: (Offset
binary output available if set
low. Twos complement output
available if set high).
Reference Voltage Input for
Channel A.
Internal Reference Voltage.
Reference Voltage Input for
Channel B.
User Select #1 (Refer to Table
I), Tied with Respect to VD.
User Select #2 (Refer to Table
I), Tied with Respect to VD.
Analog Input for Channel B
(Complementary).
Analog Input for Channel B.
Analog Supply (3 V).
Clock Input for Channel B.
Digital Supply (3 V).
Digital Output for Channel B.
Do Not Connect.
Digital Output for Channel A.
Clock Input for Channel A.

The delay between a differential crossing of ENCODE and

ENCODE and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in

power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set at 1 dB below full

scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)

The ratio of the rms signal amplitude (set at 1 dB below full

scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).

DEFINITION OF SPECIFICATIONS
Analog Bandwidth (Small Signal)

Worst Harmonic

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

The ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.
4

REV. 0

AD9288
SAMPLE N

SAMPLE N+1

SAMPLE N+5

A IN A, A IN B

tA

SAMPLE N+2

tEH

tEL

SAMPLE N+3

SAMPLE N+4

1/ f

ENCODE A, B

tPD

tV

D7AD0A

DATA N4

DATA N3

DATA N2

DATA N1

DATA N

DATA N+1

D7BD0B

DATA N4

DATA N3

DATA N2

DATA N1

DATA N

DATA N+1

Figure 1. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing

SAMPLE N

SAMPLE N+1

SAMPLE N+5

AINA, AINB

tA

SAMPLE N+2

tEH

tEL

SAMPLE N+3

SAMPLE N+4

1/ fS

ENCODE A

tPD

ENCODE B

D7AD0A

D7BD0B

DATA N4

DATA N3

DATA N4

DATA N2

DATA N3

DATA N1

DATA N2

DATA N1

tV

DATA N

DATA N+1

DATA N

DATA N+1

Figure 2. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing

REV. 0

AD9288
SAMPLE N

SAMPLE N+1

SAMPLE N+5

AINA, AINB

tA

SAMPLE N+2

tEH

tEL

SAMPLE N+3

SAMPLE N+4

1/ fS

ENCODE A

tPD

ENCODE B

tV

D7AD0A

DATA N4

DATA N3

DATA N2

DATA N1

DATA N

DATA N+1

D7BD0B

DATA N4

DATA N3

DATA N2

DATA N1

DATA N

DATA N+1

Figure 3. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing

REV. 0

Typical Performance CharacteristicsAD9288

72.00

0
10
20

ENCODE = 100MSPS
AIN = 10.3MHz
SNR = 48.52dB
SINAD = 48.08dB
2ND HARMONIC = 62.54dBc
3RD HARMONIC = 63.56dBc

ENCODE RATE = 100MSPS

68.00
64.00
2ND

30
60.00

dB

dB

40
56.00

50

3RD

52.00

60
48.00

70

44.00

80

40.00

90

SAMPLE

10

20

30

40

50

60

70

80

90

MHz

Figure 7. Harmonic Distortion vs. AIN Frequency

Figure 4. Spectrum: fS = 100 MSPS, fIN = 10 MHz,

Single-Ended Input

0
10
20

ENCODE = 100MSPS
AIN = 41MHz
SNR = 47.87dB
SINAD = 46.27dB
2ND HARMONIC = 54.10dBc
3RD HARMONIC = 55.46dBc

ENCODE = 100MSPS
AIN1 = 9.3MHz
AIN2 = 10.3MHz
IMD = 60.0dBc

10
20
30

40

40

dB

dB

30

50

50

60

60

70

70

80

80
90

90

SAMPLE

SAMPLE

Figure 5. Spectrum: fS = 100 MSPS, fIN = 41 MHz,

Single-Ended Input

Figure 8. Two-Tone Intermodulation Distortion

0
10
20

50.00

ENCODE = 100MSPS
AIN = 76MHz
SNR = 47.1dB
SINAD = 43.2dB
2ND HARMONIC = 52.2dBc
3RD HARMONIC = 51.5dBc

ENCODE RATE = 100MSPS

48.00
SNR
46.00

30

SINAD
44.00
dB

dB

40
50

42.00

60
40.00

70
38.00

80

36.00

90

SAMPLE

10

20

30

40

50

60

70

80

MHz

Figure 6. Spectrum: fS = 100 MSPS, fIN = 76 MHz,

Single-Ended Input

REV. 0

Figure 9. SINAD/SNR vs. AIN Frequency

90

AD9288
49.00

190
AIN = 10.3MHz

SNR

AIN = 10.3MHz

185
SINAD

180

48.00
POWER mW

dB

175

47.00

170
165
160
155

46.00
150
145
45.00
30

40

50

60

70
MSPS

80

90

100

140

110

Figure 10. SINAD/SNR vs. Encode Rate

10

20

30

40

50
MSPS

60

70

80

90

100

Figure 13. Analog Power Dissipation vs. Encode Rate

50.00

48.0
AIN = 10.3MHz

SNR

ENCODE RATE = 100MSPS

AIN = 10.3MHz

47.5
SINAD

46.00

47.0

SNR

46.5
SINAD

42.00

dB

dB

46.0
45.5

38.00
45.0
44.5

34.00

44.0
30.00
7.0

6.5

6.0
5.5
5.0
4.5
4.0
ENCODE HIGH PULSEWIDTH ns

3.5

43.5

3.0

Figure 11. SINAD/SNR vs. Encode Pulsewidth High

0.5

40

25
TEMPERATURE 8C

85

Figure 14. SINAD/SNR vs. Temperature

0.6

ENCODE RATE = 100MSPS

0.0

ENCODE RATE = 100MSPS

AIN = 10.3MHz

0.4

0.5
0.2

1.0
1.5

0
3dB

% GAIN

dB

2.0
2.5
3.0

0.2
0.4

3.5
4.0

0.6

4.5
0.8
5.0
5.5
0

100

200
300
400
BANDWIDTH MHz

500

1.0

600

Figure 12. ADC Frequency Response: fS = 100 MSPS

40

25
TEMPERATURE 8C

85

Figure 15. ADC Gain vs. Temperature (with External

+1.25 V Reference)

REV. 0

AD9288
VD

2.0
1.5
1.0

28kV

28kV

AIN

AIN
12kV

12kV

LSB

0.5

Figure 19. Equivalent Analog Input Circuit

0.0
0.5

VD

1.0
1.5

VBIAS

2.0

REFIN

CODE

Figure 16. Integral Nonlinearity

Figure 20. Equivalent Reference Input Circuit
1.00
VD

0.75
0.50

ENCODE

LSB

0.25
0.00

Figure 21. Equivalent Encode Input Circuit

0.25
0.50

VDD
0.75

OUT

1.00
CODE

Figure 17. Differential Nonlinearity

Figure 22. Equivalent Digital Output Circuit
1.3
ENCODE = 100MSPS
VD = 3.0V
TA = +258C

1.2

VD

VREFOUT V

1.1
OUT

1.0

0.9

Figure 23. Equivalent Reference Output Circuit

0.8

0.7

0.25

0.5

0.75
1
LOAD mA

1.25

1.5

1.75

Figure 18. Voltage Reference Out vs. Current Load

REV. 0

AD9288
APPLICATION NOTES

Timing

THEORY OF OPERATION

The AD9288 provides latched data outputs, with four pipeline

delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the encode command (see Figures 1, 2
and 3). The length of the output data lines and loads placed on
them should be minimized to reduce transients within the
AD9288. These transients can detract from the converters
dynamic performance.

The AD9288 ADC architecture is a bit-per-stage pipeline-type

converter utilizing switch capacitor techniques. These stages
determine the 5 MSBs and drive a 3-bit flash. Each stage provides sufficient overlap and error correction allowing optimization of comparator accuracy. The input buffers are differential
and both sets of inputs are internally biased. This allows the
most flexible use of ac or dc and differential or single-ended
input modes. The output staging block aligns the data, carries
out the error correction and feeds the data to output buffers.
The set of output buffers are powered from a separate supply,
allowing adjustment of the output voltage swing. There is no
discernible difference in performance between the two channels.

The minimum guaranteed conversion rate of the AD9288 is

1 MSPS. At clock rates below 1 MSPS, dynamic performance
will degrade. Typical power-up recovery time after standby
mode is 15 clock cycles.
User Select Options

USING THE AD9288

Good high speed design practices must be followed when using

the AD9288. To obtain maximum benefit, decoupling capacitors
should be physically as close to the chip as possible, minimizing
trace and via inductance between chip pins and capacitor (0603
surface mount caps are used on the AD9288/PCB evaluation
board). It is recommended to place a 0.1 F capacitor at each
power-ground pin pair for high frequency decoupling, and include one 10 F capacitor for local low frequency decoupling.
The VREF IN pin should also be decoupled by a 0.1 F capacitor. It is also recommended to use a split power plane and
contiguous ground plane (see evaluation board section). Data
output traces should be short (<1 inch), minimizing on-chip
noise at switching.

Two pins are available for a combination of operational modes.

These options allow the user to place both channels in standby,
excluding the reference, or just the B channel. Both modes place
the output buffers and clock inputs in high impedance states.
The other option allows the user to skew the B channel output
data by 1/2 a clock cycle. In other words, if two clocks are fed to
the AD9288 and are 180 out of phase, enabling the data align
will allow Channel B output data to be available at the rising
edge of Clock A. If the same encode clock is provided to both
channels and the data align pin is enabled, then output data
from Channel B will be 180 out of phase with respect to Channel A. If the same encode clock is provided to both channels
and the data align pin is disabled, then both outputs are delivered on the same rising edge of the clock.
EVALUATION BOARD

ENCODE Input

Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track/hold
circuit is essentially a mixer. Any noise, distortion or timing
jitter on the clock will be combined with the desired signal at
the A/D output. For that reason, considerable care has been
taken in the design of the ENCODE input of the AD9288, and
the user is advised to give commensurate thought to the clock
source. The ENCODE input is fully TTL/CMOS compatible.
Digital Outputs

The digital outputs are TTL/CMOS compatible for lower

power consumption. During standby, the output buffers transition to a high impedance state. A data format selection option
supports either twos complement (set high) or offset binary
output (set low) formats.
Analog Input

The AD9288 evaluation board offers an easy way to test the

AD9288. It provides a means to drive the analog inputs singleendedly or differentially. The two encode clocks are easily
accessible at on-board SMB connectors J2, J7. These clocks are
buffered on the board to provide the clocks for an on-board
DAC and latches. The digital outputs and output clocks are
available at a standard 37-pin connector, P2. The board has
several different modes of operation, and is shipped in the following configuration:
Single-Ended Analog Input
Normal Operation Timing Mode
Internal Voltage Reference
Power Connector

Power is supplied to the board via a detachable 6-pin power

strip, P1.

Optional External Reference Input (1.25 V/1 A)

Optional External Reference Input (1.25 V/1 A)
Supply for Support Logic and DAC (3 V/215 mA)
Supply for ADC Outputs
(3 V/15 mA)
Supply for ADC Analog
(3 V/30 mA)

The analog input to the AD9288 is a differential buffer. For

best dynamic performance, impedance at AIN and AIN should
match. Special care was taken in the design of the analog input
stage of the AD9288 to prevent damage and corruption of
data when the input is overdriven. The nominal input range is
1.024 V p-p centered at VD 0.3.

VREFA
VREFB
VDL
VDD
VD

Voltage Reference

The evaluation board accepts a 1 V analog input signal centered

at ground at each analog input. These can be single-ended signals using SMB connectors J5 (channel A) and J1 (Channel B).
In this mode use jumpers E4E5 and E6E7. (E1E2 and E9
E10 jumpers should be lifted.)

Analog Inputs

A stable and accurate 1.25 V voltage reference is built into the

AD9288 (REFOUT). In normal operation, the internal reference
is used by strapping Pins 5 (REFINA) and 7 (REFINB) to Pin 6
(REFOUT). The input range can be adjusted by varying the
reference voltage applied to the AD9288. No appreciable degradation in performance occurs when the reference is adjusted
5%. The full-scale range of the ADC tracks reference voltage,
which changes linearly.

Differential analog inputs use SMB connectors J4 and J6. Input

is 1 V centered at ground. The single-ended input is converted

10

REV. 0

AD9288
to differential by transformers T1, T2allowing the ADC performance for differential inputs to be measured using a singleended source. In this mode use jumpers E1E2, E3E4, E7E8
and E9E10. (E4E5 and E6E7 jumpers should be lifted.)

PIN 22 (DATA)

Each analog input is terminated on the board with 50 to

ground. Each input is ac-coupled on the board through a 0.1 F
capacitor to an on-chip resistor divider that provides dc bias.
Note that the inverting analog inputs are terminated on the
board with 25 (optimized for single-ended operation). When
driving the board differentially these resistors can be changed to
50 to provide balanced inputs.
Encode

The encode clock for channel A uses SMB connector J7. Channel B encode is at SMB connector J2. Each clock input is terminated on the board with 50 to ground. The input clocks are
fed directly to the ADC and to buffers U5, U6 which drive the
DAC and latches. The clock inputs are TTL compatible, but
should be limited to a maximum of VD.
Voltage Reference

The AD9288 has an internal 1.25 V voltage reference. An external reference for each channel may be employed instead. The
evaluation board is configured for the internal reference (use
jumpers E18E41 and E17E19. To use external references,
connect to VREFA and VREFB pins on the power connector
P1 and use jumpers E20E18 and E21E19.

PIN 2 (CLOCK)

Ch1

2.00V

CH2

2.00V

M 10.0ns CH4

40mV

Figure 24. Data Output and Clock at 37-Pin Connector

DAC Outputs

Each channel is reconstructed by an on-board dual channel

DAC, an AD9763. This DAC is intended to assist in debugit
should not be used to measure the performance of the ADC. It
is a current output DAC with on-board 50 termination resistors. Figure 25 is representative of the DAC output with a fullscale analog input. The scope setting was low bandwidth, 50
termination.

Normal Operation Mode

In this mode both converters are clocked by the same encode

clock; latency is four clock cycles (see timing diagram). Signal
S1 (Pin 8) is held high and signal S2 (Pin 9) is held low. This is
set at jumpers E22E29 and E26E23.

Ch1 500mVVBW

Data Align Mode

In this mode channel B output is delayed an additional 1/2 cycle.

Signal S1 (Pin 8) and signal S2 (Pin 9) are both held high. This
is set at jumpers E22E29 and E26E28.
Data Format Select

Data Format Select sets the output data format that the ADC
outputs. Setting DFS (Pin 4) low at E30E27 sets the output
format to be offset binary; setting DFS high at E30E25 sets
the output to be twos complement.
Data Outputs

The ADC digital outputs are latched on the board by two 574s,
the latch outputs are available at the 37-pin connector at Pins
2229 (Channel A) and Pins 3037 (Channel B). A latch output clock (data ready) is available at Pin 2 or 21 on the output
connector. The data ready signal can be aligned with clock A
input by connecting E31E32 or aligned with clock B input by
connecting E31E33.

REV. 0

M 50.0ns CH1

380mV

Figure 25. AD9763 Reconstruction DAC Output

Troubleshooting

If the board does not seem to be working correctly, try the

following:
Verify power at IC pins.
Check that all jumpers are in the correct position for the
desired mode of operation.
Verify VREF is at 1.25 V
Try running encode clock and analog inputs at low speeds
(10 MSPS/1 MHz) and monitor 574 outputs, DAC outputs,
and ADC outputs for toggling.
The AD9288 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.

11

AD9288
BILL OF MATERIALS

QTY

REFDES

DEVICE

PACKAGE

VALUE

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

22
5
43
8
1
1
10
2
2
2
2
1
1
2
2

C1C15, C20C25, C27

C16C19, C26
E1E43
J1J8
P1
P2
R1, R3, R5R7, R10R14
R2, R4
R8, R9
R15, R16
T1, T2
U1
U2
U3, U4
U5, U6

Ceramic Cap
Tantalum Cap
W-HOLE
SMBPN
TB6
37DRFP
Resistor
Resistor
Resistor
Resistor
Transformer
AD9288
AD9763
74ACQ574
SN74LCX86

0603
TAJD
W-HOLE
SMBP
TB6
C37DRFP
R1206
R1206
R1206
R1206
T11T
LQFP48
LQFP48
DIP20\SOL
SO14

0.1 F
10 F

12

50
25
2 k
0

REV. 0

R5
50V

R6
50V

VDL

R7
50V

GND GND

J2

ENCODE B

AINB
SINGLE-ENDED

J1

GND

E3

T1

3
2
1

E7

GND

E14

GND

E16

CLKCONB

GND

E13

R15
00

E23

VD

CLKDACB

CLKLATB

GND

C13
0.1mF

GND

8 DB2P1
9 DB1P1

D0B
GND
GND

VDL

VREFB

VREFA

C27
0.1mF

E11

E22

GND

E12

E15

VDL

E29

E24

GND

7 DB3P1

C24
0.1mF

E18

E21 E19

E17

E41

GND

GND

12 NC1

11 NC

10 DB0P1

E20

GND

6 DB4P1

D1B

VDL

5 DB5P1

E38

GND

E37

E39

VDL

E30

GND

E27

E26

GND

VD

E25

CLKDACA

CLKLATA

GND

C25
0.1mF

GND

E28

14
VCC
13
4B
1B
12
4A
1Y
U5
4Y 11
2A
10
3B
2B
9
3A
2Y
8
3Y
GND

74LCX86

1A

VD
C12
0.1mF

GND

R4
25V

R2
25V

GND
C9
0.1mF

14
VCC
1A
13
4B
1B
12
4A
1Y
U6
4Y 11
2A
10
3B
2B
9
3A
2Y
8
3Y
GND

74LCX86

C10
0.1mF

4
5

C11
0.1mF

GND

R3
50V

E4

ENCB

E6

E8

6
T11T

GND

E10

E9

GND

AINB
DIFFERENTIAL

J6

GND

GND

E5

R1
50V

GND

GND

CLKCONA

E34

GND

E36

GND

E35

T11T
1
6
E2
2
E1 4 T2 3

GND

AINA
DIFFERENTIAL

J4

GND

AINA
SINGLE-ENDED

J5

GND

VDL

R11
50V

GND GND

J7

ENCODE A

R16
00

ENCA

4 DB6P1

MODE
AVDD

AD9763
U2

REFIO

GND

GND

C23
0.1mF

S2

S1

REFINB

REFOUT

REFINA

2COMP

AINAB

AINA

GND1

12 GND2

11 AINB

10 AINBB

48

13

14

16

46 45

15

47

44

NC6 35
NC5 34

NC7 36

43

GND

DB7P2 25

42

18

17

AD9288
U1

41

19

40

D2A
D3A

DB6P2 26

D6A
D7A

D4A
D5A

D1A

DB5P2 27

DB4P2 28

GND
GND
D0A

DB3P2 29

DB2P2 30

DB1P2 31

NC4 33
DB0P2 32

C22
0.1mF

13 14 15 16 17 18 19 20 21 22 23 24

NC2

GND
GND
GND

D3B
D2B

A1
B1

NC3
DCOM1
DVDD1

VDL

3 DB7P1

FSADJ1
WRT1/IQWRT

CLKDACA
CLKDACA

GND
C5
0.1mF

D4B

CLKDACB

GND
C7
0.1mF

VD
VD3
VD

VD

2 DB8P1

B2

CLK1/IQCLK
CLK2/IQRESET
WRT2/IQSEL
DCOM2

CLKDACB
GND
VDD
ENCA
ENCB

1 DB9P1

DVDD2

VDL
GND

ENCA
VDD3
VDD

ENCB

D7B
D6B
D5B

REFIO
FSADJ2

48 47 46 45 44 43 42 41 40 39 38 37

SLEEP

DB9P2
DB8P2

D7

VDL

GND

50V
GND
2kV
GND
C21 0.1mF
R13
R9

2kV
GND
50V
GND
R8
R10

J3 DAC OUTPUT A
GND
R12
50V
GND
GND
GND
A2
ACOM

VDD

D5
D7A

D4
39

38

20

21 22

23

D6A
D6B

C8
GND 0.1mF
GND
GND3

GND
C6
0.1mF

D9A

GND

D3
D5A
D5B

D6
D8A

D9B

13
D7B

D2
D4A
D4B

37

D0

Q4
Q5
Q6
Q7
CLOCK

D4
D5
D6

D2
D1

24

GND

GND

D1B 25

D0B 26

GND4 27

VDD1 28

GND5 29

VD1 30

VD2 31

GND6 32

VDD2 33

9 D7
10 GND

7 D5
8 D6

C3
0.1mF

GND

31
32
33
34

D3B
D4B

16
15

CLKLATA

C37DRPF
P2

37

E40

36

CLKLATB

35
D7B MSB

13
Q6
12
Q7
11
CLOCK

Q5

D6B
E42

30
D2B
17

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

D1B

CLKCONB

12
13

11
E31
E33

10

GND

E32

CLKCONA

GND

C26
10mF

VREFB
C19
10mF

VREFA
C18
10mF

18

VDL

C17
10mF

VDL

D0B

E43

C15
0.1mF

GND

VDD

VD

VD

VDD

D0A LSB

D2A
D1A

D3A

D4A

D5A

D6A

D7A

C16
10mF

VDD

D5B

Q4

Q3

Q2

VDL

VD

CLKLATA

C14
0.1mF

GND

20
19

14

U4

Q0

D0

Q1

VCC

74ACQ574

VREFA VREFB

GND

C1
0.1mF

C2
0.1mF

C4 GND
0.1mF

Q3

OUT_EN
D1
4 D2
5 D3
6 D4

GND

GND

GND

GND

GND
GND

GND
D1A 36

GND

GND

GND

D0A 35

D7

D0

U3

D3

D4

Q2

Q1

D1
D2
D3

D6
D5

Q0

D0

VDL

D7

74ACQ574

VDD

VCC

VD

P1

OUT_EN

GND

GND

GND7 34

D2A

D1
D3A
D3B

REV. 0
D8B

Figure 26 . Dual Evaluation Board Schematic

D2B

DAC OUTPUT B J8
GND
R14
50V
GND
VDL
C20
0.1mF
GND

AD9288

AD9288

Figure 27. Printed Circuit Board Top Side Copper

Figure 29. Printed Circuit Board Ground Layer

Figure 28. Printed Circuit Board Bottom Side Silkscreen

Figure 30. Printed Circuit Board Split Power Layer

14

REV. 0

AD9288

Figure 31. Printed Circuit Board Bottom Side Copper

REV. 0

Figure 32. Printed Circuit Board Top Side Silkscreen

15

AD9288
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

0.063 (1.60) MAX

0.354 (9.00) BSC

0.030 (1.45)
(0.75)
0.057
0.018 (1.35)
(0.45)
0.053

0.276 (7.0) BSC

0.276 (7.0) BSC

37
36

48
1

SEATING
PLANE
TOP VIEW
(PINS DOWN)

0 7

0 MIN
0.007 (0.18)
0.004 (0.09)

12
13

0.019 (0.5)
BSC

25
24

0.011 (0.27)
0.006 (0.17)

PRINTED IN U.S.A.

0.006 (0.15)
0.002 (0.05)

0.354 (9.00) BSC

0.030 (0.75)
0.018 (0.45)

C354684/99

48-Lead LQFP
(ST-48)

16

REV. 0

This datasheet has been download from:

www.datasheetcatalog.com
Datasheets for electronics components.