RTC/ECE/EC6302/DIGITAL ELECTRONICS/2014-2018

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SYLLABUS
EC6302

DIGITAL ELECTRONICS

LTPC
3003

OBJECTIVES:
To introduce basic postulates of Boolean algebra and shows the correlation between Boolean
expressions
To introduce the methods for simplifying Boolean expressions
To outline the formal procedures for the analysis and design of combinational circuits
and sequential circuits
To introduce the concept of memories and programmable logic devices.
To illustrate the concept of synchronous and asynchronous sequential circuits
UNIT I

MINIMIZATION TECHNIQUES AND LOGIC GATES

Minimization Techniques: Boolean postulates and laws De-Morgans Theorem - Principle of Duality Boolean expression - Minimization of Boolean expressions Minterm Maxterm - Sum of Products (SOP)
Product of Sums (POS) Karnaugh map Minimization Dont care conditions Quine - Mc Cluskey
method of minimization.
Logic Gates:
AND, OR, NOT, NAND, NOR, ExclusiveOR and ExclusiveNOR Implementations of Logic Functions
using gates, NANDNOR implementations Multi level gate implementations- Multi output gate
implementations. TTL and CMOS Logic and their characteristics Tristate gates.
UNIT II

COMBINATIONAL CIRCUITS

Design procedure Half adder Full Adder Half subtractor Full subtractor Parallel binary adder,
parallel binary Subtractor Fast Adder - Carry Look Ahead adder Serial Adder/Subtractor - BCD adder
Binary Multiplier Binary Divider - Multiplexer/ Demultiplexer decoder - encoder parity checker parity
generators code converters - Magnitude Comparator.
UNIT III

SEQUENTIAL CIRCUITS

Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation Application table
Edge triggering Level Triggering Realization of one flip flop using other flip flops serial
adder/subtractor- Asynchronous Ripple or serial counter Asynchronous Up/Down counter - Synchronous
counters Synchronous Up/Down counters Programmable counters Design of Synchronous counters:
state diagram- State table State minimization State assignment Excitation table and maps-Circuit

RTC/ECE/EC6302/DIGITAL ELECTRONICS/2014-2018
implementation - Modulon counter, Registers shift registers - Universal shift registers Shift register
counters Ring counter Shift counters - Sequence generators.

UNIT IV

MEMORY DEVICES

Classification of memories ROM - ROM organization - PROM EPROM EEPROM EAPROM, RAM
RAM organization Write operation Read operation Memory cycle - Timing wave forms Memory
decoding memory expansion Static RAM Cell- Bipolar RAM cell MOSFET RAM cell Dynamic RAM
cell Programmable Logic Devices Programmable Logic Array (PLA) - Programmable Array Logic (PAL)
Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using ROM, PLA,
PAL
UNIT V SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS 9
Synchronous Sequential Circuits: General Model Classification Design Use of Algorithmic State
Machine Analysis of Synchronous Sequential Circuits
Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits Incompletely
specified State Machines Problems in Asynchronous Circuits Design of Hazard Free Switching circuits.
Design of Combinational and Sequential circuits using VERILOG.
TOTAL: 45 PERIODS
OUTCOMES:
Students will be able to:
Analyze different methods used for simplification of Boolean expressions.
Design and implement Combinational circuits.
Design and implement synchronous and asynchronous sequential circuits.
Write simple HDL codes for the circuits.
TEXT BOOK:
1. M. Morris Mano, Digital Design, 4th Edition, Prentice Hall of India Pvt. Ltd., 2008 / Pearson
Education (Singapore) Pvt. Ltd., New Delhi, 2003.
REFERENCES:
1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2008.
2. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2006.
3. Charles H.Roth. Fundamentals of Logic Design, 6th Edition, Thomson Learning, 2013.
4. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6th Edition, TMH,
2006.
5. Thomas L. Floyd, Digital Fundamentals, 10th Edition, Pearson Education Inc, 2011.
6. Donald D.Givone, Digital Principles and Design, TMH, 2003.

RTC/ECE/EC6302/DIGITAL ELECTRONICS/2014-2018

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LESSON PLAN
Unit : I - V

LESSON PLAN JUNE 2016

Sub Code : EC6302
Sub Name : Digital Electronics
Staff In-Charge : Prakash A
Designation/ Department : Assistant Professor / ECE
Academic Year : 2016-2017

S.No

2
3

4
5
6
7

8
9
10

Topic

No. of Hours
Required

Handled

Date of
Handling

Text/ Ref.
Book

MINIMIZATION TECHNIQUES AND LOGIC GATES

Introduction to Digital
Electronics, Boolean
1
T1
postulates and laws, DeMorgans Theorem.
Principle of duality,
Minimization of expressions
1
T1
using Boolean laws.
Minterm, Maxterm, Sum of
Products (SOP), Product of
1
T1
Sums (POS).
Minimization of expressions
using Karnaugh map-3&4
2
T1
variable K-map.
5-variable K-map, K-map
2
T1
with dont care conditions.
Quine-McCluskey method of
2
T1
minimization.
Truth table, symbol and
expressions of AND, OR,
2
T1
NOT, NAND, NOR, ExOR
and ExNOR.
Implementation of logic
function using Universal
1
T1
gates, Multi level-output gate
implementations.
Tutorial
3
T1
Characteristics of TTL and
1
T1

Branch: ECE
Year : II
Semester : III
Date : 29.06.2016

Teaching
Mode

BB

BB
BB

BB
BB
BB
BB

BB
BB
BB

Status

Att
%

RTC/ECE/EC6302/DIGITAL ELECTRONICS/2014-2018
CMOS Logic, Tristate gates.
COMBINATIONAL CIRCUITS
1
2

3
4

5
6
7
8
9
10
1

Design of half adder and full

adder.
Design of half subtractor, full
subtractor and parallel binary
adder/subtractor.
Disadvantages of parallel
adder carry look ahead adder.
Design of serial
adder/subtractor and BCD
adder.
Binary multiplier and binary
divider.
Binary Divider
Design and implementation of
Multiplexer and
Demultiplexer.
Encoder and decoder. Odd,
Even: Parity generators and
checker.
Code converters.
2-bit, 4-bit Magnitude
comparator.
Latches, Characteristic table
and equation of SR, JK, D and
T flip flop.
Level triggering and edge
triggering of flip flop.
Conversion of one flip flop to
other flip flops
Realizations of one flip flop
using other flip flops, MasterSlave flip flop.

T1

NPTEL

T1

BB

T1

BB

T1

BB

T1

BB

1
1

T1
T1

BB
BB

T1

BB

T1

BB

T1

BB

T1

NPTEL

T1

BB

T1

BB

SEQUENTIAL CIRCUITS
2

Asynchronous: ripple counter,

Up/Down counter.

T1

BB

Synchronous: Up/Down
counters, Programmable
counters.

T1

BB

State diagram, minimization

and State assignment.
Excitation table and maps.

T1

BB

Design of Modulo-n counter.

T1

BB

RTC/ECE/EC6302/DIGITAL ELECTRONICS/2014-2018
8

10

Tutorial
Shift registers, SISO, SIPO,
PISO, PIPO ,Universal shift
registers
Shift register counters, ring
counter and shift counter.

T1

BB

T1

BB

T1

BB

MEMORY DEVICES

Classification of memoriesROM, RAM

T1

BB

ROM Organisation - PROM,

EPROM,
EEPROM,EAPROM

T1

NPTEL

RAM organization, - Write

and Read operation, Memory
cycle and Timing wave forms.

T1

BB

Memory decoding

T1

BB

Memory expansion.

T1

BB

Static RAM Cell, Bipolar

RAM cell ,

T1

BB

T1

BB

T1

BB

T1

BB

T1

BB

9
10

Dynamic RAM Cell and

MOSFET RAM cell.
Introduction to Programmable
Logic Devices.
Implementation of
combinational logic circuits
using PLA.
Implementation of
combinational logic circuits
using ROM,
PLA, PAL

SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

RTC/ECE/EC6302/DIGITAL ELECTRONICS/2014-2018
General sequential Model
Classification and design of
1
2
synchronous sequential
circuit.
Analysis of Synchronous
2
1
Sequential circuit.
3
4
5
6
7
8
9

Algorithmic State Machine.

Design of fundamental mode
Incompletely specified
State Machines
Design of Pulse mode Incompletely specified State
Machines
Problems in Asynchronous
Circuits - Hazards and types
of hazards.
Design of Hazard free
Switching circuits.
Design of Combinational and
Sequential circuits using
Verilog.
Design of Combinational and
Sequential circuits using
Verilog.

R1

NPTEL

R1

BB

R1

BB

R1

BB

R1

BB

R1

BB

R1

BB

R1

BB

R1

BB

RTC/ECE/EC6302/DIGITAL ELECTRONICS/2014-2018

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Unit : I - V

LESSON PLAN JUNE 2016

Sub Code : EC6302
Sub Name : Digital Electronics
Staff In-Charge : Prakash A
Designation/ Department : Assistant Professor / ECE
Academic Year : 2015-2016
Course Delivery Plan:
Weeks

Units

II

III

10

Branch: ECE
Year : II
Semester : III
Date : 29.06.2016

11

IV

12

13

TEXT BOOKS:
1. M. Morris Mano, Digital Design, 4th Edition, Prentice Hall of India Pvt. Ltd., 2008 / Pearson
Education (Singapore) Pvt. Ltd., New Delhi, 2003.

REFERENCE BOOKS:
2. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2008
3. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2006.
4. Charles H.Roth. Fundamentals of Logic Design, 6th Edition, Thomson Learning, 2013.
5. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6th Edition, TMH,
6. Thomas L. Floyd, Digital Fundamentals, 10th Edition, Pearson Education Inc, 2011
7. Donald D.Givone, Digital Principles and Design, TMH, 2003.
8. http://nptel.ac.in
9.http://distrct.bluegrass.kctcs.edu/kevin.dunn/files/shift_registers

2006