Beruflich Dokumente
Kultur Dokumente
2013
32-bit
8/16-bit
Industrial, 90nm
1mA/MHz, 100A standby
Wide
Format LCDs
350A/MHz, 1A standby
3
FLASH ROM
On chip RAM
Master
Slave
ROM I/F_1
Comparator Module
INT(INT_1)
SH-2A
CPU
(CPU_1)
ROM I/F_2
INT(INT_2)
SH-2A
CPU
(CPU_2)
F-Bus
C-Bus (32bit)
M-Bus
(32bit)
I-Bus
Bridge_1
MISG
AUD
JTAG
I-Bus
Bridge_2
UBC
I-Bus
(32bit)
DMAC_1
P-Bus
Bridge_1
DMAC_2
Comparator Module
P-Bus
Bridge_2
P-Bus
(16bit)
RSPI
MTU
A/D
RCAN
SCI
GPIO
Peripherals
10
Item definition
Part 3
Supporting processes
Safety Goal
Safety
Safety
Safety
Concepts
Concepts
Concepts
Safety assessment
Part 4
Part 4
Part 4
System (safety)
verification
Part 4
Part 4
System Integration
& testing
Part 5
HW design specification
Part 6
Item Integration
& testing
SW Design
Part 9
Part 4
Part 3
HW safety requirement
Specification and HSI
Part 4, 7
Part 2
Part 3
Analysis
ASIL
Part 8
Part 4
HW production
Part 5
Safety Analysis
HW Design
HW Verification
Part 5
Part 5
Part 5, 6
SW Verification
Part 6
Safety Concepts
Computation of HW metrics
Dependent failures
Interface to
our customers
13
14
From learning
First exposure
Acquired initial
background on
safety requirements
Worked with market
leaders in the area
Single DCLS
MCU for EPS
Gain of confidence
Exposure to
system aspects
Selected a group
of experts in
Renesas to join
ISO26262 and
IEC61508 WGs
MCU + ASIC
solution for Airbag
Focus on IEC61508
15
Strategy definition
Biz as usual
Definition of
internal safety
approach
Compliance as
part of normal
daily work
Received
acceptance from
the market
Continuing
cooperation in
ISO (and IEC)
WGs to improve
safety
General
All new products
Focus on ISO26262
Work product 1
Project classification
gate
Work product m
WW
Marketing
teams
Specification
definition
teams
Component
development
teams
16
QA
Work product n
Specification
Concept gate
Front-end gate
Back-end gate
Qualification gate
MP gate
MP request
An element can be
1. Already existing in the market (COTS)
COTS:
17
ISO26262 shall be adopted as state of the art flow even if some deviations with
respect to 3 applies
Applicability to MCUs
2 Management of
functional safety
3 Concept phase
4 Product development
at the system level
5 Product development
at the hardware level
Applicability to ASICs
Mostly applicable
7 Production and
operation
Mostly applicable
8 Supporting processes
Mostly applicable
Part 1 and 10 only containing informative requirements. Part 6 (SW) excluded in this presentation
18
Safety Concepts
Computation of HW metrics
Dependent failures
Interface to
our customers
19
Safety MCU
analysis
Safety system
analysis
MCU
S, SPF,
MPF,
DCRF,
DCLF
MCU
safety
database
Customer
20
22
Takashi Yasumasu
Manager for Chassis & Safety technical marketing
Renesas Electronics Corp. Automotive system div.
IEC61508
SIL2
SIL1
SIL3
ISO26262
Items safety goal
ASIL is applied on
the total system
Powertrain
37%
Chassis, Break
Steering
22%
Airbag
40%
Body+Others
52%
Car Audio
54%
Instrument
44%
Navigation*
75%
25
Lowest Power
Smallest Size
90nm
Process
40nm
Process
mA/MHz
1.08
0.51
90nm MCU
40nm MCU
Competitor
(90nm)
(90nm)
(40nm)
Safety assessment
Safety requirement
Coming from each
Applications safety
Concept is the key
Gap analysis is
Safety
validationat
necessary
integration in case of
using MCU SEooC
Is applied.
Item Integration
System verification
and validation
(OEM/Tier1)
Requirement derivation
and design for system
(OEM/Tier1)
Safety goal
HW safety Requirement
HW safety verification
Product verification
and validation
(MCU vendor)
Requirement derivation
and design for device
(MCU vendor)
Application
Hazardous Event
ASIL
Example
MCU
RH850
FTTI(1%)
Series
EPS
200us
1ms
ABS
1ms
1ms
Booster
(electrical Motor supporter)
1ms
Passive
Safety
Airbag
10ms
Active
Safety
10ms
Power
train
Powertrain
10ms
Transmission
10ms
Front beam
10ms
Brake lamp
10ms
Meter
10ms
Motor control
TBC
Chassis
Body
HEV/EV
Flash Memory
Flash Memory
Flash Memory
CPU
System BUS
System BUS
Flash Memory
CPU
Single Core
Airbag/Body
Central gateway
System BUS
30
Dual DCLS
ADAS, Server
DCLS
(Dual Core Lock Step)
Braking/Steering
Motor Control
Flash Memory
CPU
CMP
CPU
System BUS
Application
Independent Part
RH850/P1x
Memory
ROM : ECC (SECDED), CRC
Address Parity
RAM : ECC (SECDED)
M-BIST
Address Parity
EEPROM : ECC(SECDED)
Memory
Others
Bus : End to End S.M.
ECM : Control behavior
at Error
Clock Monitor
Voltage Monitor
31
Peripheral
Application
Dependent Part
Separation
ECM
Flash
2 clock
delay
Logic
BIST
ECC
SPF
V850
G3M MPU
INT
PBUS
I/F
ECC
Flash
I/F
CPU
Master
Flash
I/F
2 clock
delay
Compare Unit
CPU
Checker
DMA
DMA
RAM
I/F
RAM
I/F
ECC
SPF
Logic
BIST
V850
MPU G3M
INT
ECC
PBUS
I/F
2 clock
delay
ECC
RAM
BIST
WDT
Power
Supply
Standard MCU
Error Correction
CPU
ERROR
DMA detection
Failure
Systematic
Faults
Memory
and
correction
Fault
detection
Built
In
Self Test
Peripherals
Flash
ECC
Memory
Protection
RAM
ECC
Redundancy
Timing
Supervision
Latent
fault
detection
Peri.
MEM
ECC
Peri.
Protection
@
Start-Up
Lockstep
operation
Monitors
Clock
Watchdog
CPU
CoreCPU
MASTER
Volatile
Memories
ECM
CHECKER
CPU
Peripherals
H/W comparator
PLL
Common
Cause
Collection
Identical
inputs
Error
Main
Oscillator
Error
Management
Output
comparison
Ring
Oscillator
by
Inverted
signals
Interrupt
by
2-clock
delay
Reset
by
Layout
Separation
ERROR
output
Power separation
Cross talk analysis
Clock
Clock
Clock
Monitor
Monitor
Monitor
Peripherals
Logic
BIST
ECC RAM
BIST
Clock Gen.
Ring
OSC
In-/Outputs
Inputs
Outputs
Error
Clock
Safety Block
Functional Block
Clock Input
32
Input
Judge
Out
put
Braking
Wheel
Speed
Pulse
Input
Capture
Timer
PWM
Timer
EPS
Torque
Sensor
Motor current
12bit
SAR
ADC
PWM
Timer
ADAS
Vision
Rader
(LRR/MRR)
High
speed
Serial
ADC
Application
Dependent Part
RENESAS Group CONFIDENTIAL
CAN
Solenoid Control
(PWM)
Command via
CAN
Application
Dependent Part
EPS
100ms
20ms
ADAS
100ms
Input
Output
Test Pattern
Timer
(IC)
Timer
(PWM)
(Input)
ADC
Or Serial
Timer
(PWM)
(Input)
CAN
CAN
(Input)
34
Input
Out
put
Judge
L-RAM
Mission Logic
Timer (Input Capture)
Bus interconnect(Address/Data )
L-RAM
DCLS CPU
Internal connection
E2E
TIMER
INPUT
MONITOR
Merit
E2E from Input to L-RAM(read after write)
Easy implementation into application program
Effective for Transient fault
Timer
input1
Timer
input0
data path
Address path
L-RAM : Local RAM, tightly coupled RAM with Dual Core Lock Step
RENESAS Group CONFIDENTIAL
Input
Out
put
Judge
L-RAM
Mission Logic
Timer (PWM output)
Bus interconnect(Address/Data )
L-RAM
CPU
DCLS CPU
Internal connection
E2E
Safety Mechanism
Hardware :TIMER OURPUT MONITOR
Software :Read from Timer input
TIMER
OUTPUT
MONITOR
Merit
E2E from L-RAM to Timer Output
Easy implementation into application program
Effective for Transient fault
Timer
input
Timer
Output
data path
Address path
L-RAM : Local RAM, tightly coupled RAM with Dual Core Lock Step
RENESAS Group CONFIDENTIAL
Safety Manual
How to use safety mechanism
Recommendation of timing
for application usage
Qualitative DC
Concept
FMEDA
Work Products
Work Products
SEooC based
work products
Safety
Manual
ISO26262
Work
Products
Conclusion
38
Safety Hardware
and Work Products
e.g. H/W Safety Mechanism
by each product family
Independent Checks
i.e. Confirmation Measures done
by our internal independent
organization
39
Safety Software
and Work Products
e.g. Core Self Test Software
Safety
Consultancy
e.g. Workshops, GUI tool
Questions?
40