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I. INTRODUCTION
The number of devices having video capturing capability is
increasing every day. Especially, smart phones and tablets are
extensively used to capture and share video data. It is obvious
that, efficient compression methods are needed to store these
videos in a limited memory. Additionally, transmission of
captured raw video requires compression as well, for utilizing
available network bandwidth efficiently.
Starting from the introduction of first video coding
methods, motion compensated hybrid coding approach has
been extensively utilized. Today, H.264/AVC [1] and its
1
S. Yavuz, A. elebi and M. Aslam are with Kocaeli University Integrated
Systems Laboratory (KUTSAL), Electronics and Telecom. Eng. Dept.,
Umuttepe
Campus,
41380,
zmit/Kocaeli,
Turkey
(e-mail:
anilcelebi@kocaeli.edu.tr).
O. Urhan is with Kocaeli University Laboratory of Embedded and Vision
Systems (KULE), Electronics and Telecom. Eng. Dept., Umuttepe Campus,
41380, zmit/Kocaeli, Turkey (e-mail: urhano@kocaeli.edu.tr).
Contributed Paper
Manuscript received 12/31/15
Current version published 03/30/16
Electronic version published 03/30/16
are also developed based on the same concept where intraframe redundancies are exploited by making use of intra
prediction and transform coding whereas block-based motion
estimation techniques are employed to take advantage of
temporal redundancies. Statistical redundancies are exploited
by entropy coding techniques such as CALVC (Contextadaptive variable-length coding) and CABAC (Contextadaptive binary arithmetic coding). It is important to note that
the ME part is generally the most time consuming stage in a
video encoder [3].
In the block-based ME, each frame is divided into
non-overlapping blocks and each block in current frame is
searched around a wider area of the same location in reference
frame/s which is referred to as search window. Sum of
squared differences (SSD) or sum of absolute differences
(SAD) criterion is utilized to decide similarity between the
original and candidate blocks. Since the current block is
searched in all possible candidate locations within the search
range, the computational complexity of this process is quite
high. This method is referred to as full-search (FS) based ME
because all the candidate locations are checked.
There are several group of approaches in the literature to
reduce computational load and the hardware complexity of the
full search based ME method. The main motivation of the first
group of approaches is to check only a sub-set of all candidate
locations in search window. Three-step search [4], diamond
search [5] and hexagonal search [6] based ME methods are
members of this category where only pre-defined search
locations are checked. Adaptive search range determination
based approaches such as the method presented by Lee et al
[7] can be put into this group as well where only limited
number of candidates are checked based on a pre-decided
search range for each block.
The second group of approaches propose to reduce the
number of pixels utilized for computing the matching criterion
by making use of a specific sub-sampling pattern such as
quarter [8], quincunx [9], 8-Queen [10] and reconfigurable
boundary [11].
The third group targets to skip computation of matching
criterion for specific or all remaining candidate location/s. For
example, successive elimination algorithm (SEA) based
methods such as the approach presented by Li et al [12],
compute the lower bound of the matching criterion at lower
S. Yavuz et al.: Selective Gray-Coded Bit-Plane Based Low-Complexity Motion Estimation and its Hardware Architecture
77
SSE m, n I c i, j I r i m, j n ,
2
i 0 j 0
(1)
s m, n s
NNMP m, n B c i, j B r i m, j n
i 0 j 0
(2)
78
g7
g6
g5
g4
g3
g2
g1
g0
g K 1 aK 1
g k ak ak 1 , 0 k K 2
(3)
MC m, n
i 0 j 0 k NTB
2k NTB g kc i, j g kr i m, j n
(4)
S. Yavuz et al.: Selective Gray-Coded Bit-Plane Based Low-Complexity Motion Estimation and its Hardware Architecture
79
80
stage of addition for one pixel is ignored [43]. The last stage is
comparator where comparison operation is performed and
motion vectors of candidate block with minimum NNMP are
generated.
V. EXPERIMENTAL RESULTS
30
29
28
27
26
25
31
12
11
10
24
32
13
23
33
14
22
34
15
21
35
16
17
18
19
20
S. Yavuz et al.: Selective Gray-Coded Bit-Plane Based Low-Complexity Motion Estimation and its Hardware Architecture
81
TABLE I. PSNR PERFORMANCE (IN DB) OF DIFFERENT LOW COMPLEXITY ME METHODS IN OPEN LOOP SCHEME
Method
SAD (8-bit depth)
1BT [15]
MF-1BT [16]
2BT [17]
C-1BT [18]
GCBPM [22]
T-GCBPM [23]
Gray Coding 7th Bit Plane
Gray Coding 6th Bit Plane
Gray Coding 5th Bit Plane
Gray Coding 4th Bit Plane
Interlaced Gray-coding [37]
Regular Selection Test Pattern
elective Gray-coding (Proposed)
Football
22.88
21.83
21.81
22.06
22.10
21.87
22.59
21.66
20.79
20.31
19.54
21.94
22.09
22.24
32.09
30.32
30.38
30.70
30.86
30.96
31.32
28.46
27.92
29.27
28.70
30.92
30.62
31.03
29.45
28.11
28.18
28.46
28.71
28.24
28.78
27.49
27.34
27.44
26.52
28.47
28.46
28.69
( 352 240 )
(115 frames)
23.79
23.31
23.26
23.43
23.38
23.26
23.67
23.26
22.56
22.53
20.35
23.17
23.29
23.38
23.94
23.61
23.63
23.66
23.69
23.51
23.81
23.28
22.42
21.25
20.48
23.18
23.33
23.47
30.48
29.83
29.88
29.94
29.98
29.78
30.16
26.56
27.84
29.05
28.23
29.79
29.38
29.85
Average
of six video
sequence
27.11
26.17
26.19
26.38
26.45
26.27
26.72
25.11
24.81
24.98
23.97
26.25
26.22
26.44
ME
Approach
1BT [15]
MF-1BT[16]
2BT [17]
C-1BT [18]
T-GCBPM [23]
I-GCBPM [37]
Proposed
Transform
Matching
Addition Multiplication Shift Subtraction Comparison Boolean Op. Boolean Op. Shift Addition
(pp)
(pp)
(pp)
(pp)
(pp)
(pp)
(pp)
(pp)
(pp)
25
1
1
1
16
1
1
1
2.8125
1.0625
0.03125
3
1
3
16
1
1
2
3
2
3
3
3
1
4
2.5
1
1
5.6
2
1
-
82
Motion Vectors
hv_x
-3
3
4
8
9
9
-15
14
-12
hv_y
-3
2
0
7
-7
9
-11
-14
12
Average
Fig. 6. The data reuse scheme that proposed hardware architecture can
implement.
Control Signals
Processor
System
Control Signals,
Motion Vector
Control Signals
Video
Stream
Data
Stream
DMA IP
Data
Stream
Motion
Estimation IP
Bit depth
On chip memory
Area
Power
Maximum frequency
Technology
Search range
Search method
Proposed
3
0
8125 LUTs/7353 DFFs
8,5 mW@50MHz
243 MHz
FPGA 28 nm
[-16 16]
Spiral search
[39] Recompiled
1
24064
1121 LUTs/NAs
35,3 mW@50 MHz
218 MHz
FPGA 45nm
[-16,16]
Full search
[41]
1
4096
3914 LUTs/2517 DFFs
NA
192 MHz
FPGA 65nm
[-16,16]
Full search
[44] Recompiled
2
0
5413 LUTs/NA
30,7 mW@50 MHz
275 MHz
FPGA 45nm
[-1,1] to [-16,16]
Spiral search
S. Yavuz et al.: Selective Gray-Coded Bit-Plane Based Low-Complexity Motion Estimation and its Hardware Architecture
VI. CONCLUSIONS
In this paper, a selective Gray-coded bit-plane based
binarization approach for low complexity motion estimation
with its hardware architecture is presented. The proposed BPM
based ME method outperforms single bit-plane based methods
existing in the literature while providing similar or better
performance than the methods utilizing two bit-planes. It is
important to note that selective Gray-coded bit-plane based
method has the lowest binarization cost among the compared
methods except the conventional Gray coded BPM methods.
The proposed binarization approach is efficiently implemented
in hardware. It is shown that the architecture proposed is
suitable for seamless integration into state of the consumer
electronics devices by making use of a common bus
interconnect. Experimental results revealed that the proposed
architecture is capable of providing data reuse to reduce both
off chip data access time and power consumption dramatically.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
Joint Video Team (JVT) of ISO/IEC MPEG & ITU-T VCEG, Mart,
2003, "Draft ITU-T recommendation and final draft international
standard of joint video specification (ITU-T Rec. H.264/ISO/IEC 1449610 AVC)", JVT-G050.
ISO/IEC 23008-2:2013, High efficiency coding and media delivery in
heterogeneous environments -- Part 2: High efficiency video coding,
International Organization for Standardization. 2013-11-25.
T.C. Chen, Y.H. Chen, S.F. Tsai, S.Y. Chien, L.G. Chen, Fast
algorithm and architecture design of low-power integer motion
estimation, IEEE Trans. Circuits Syst. Video Technol., vol. 17, no. 5,
pp. 568-577, May 2007.
T. Koga, K. Linuma, A. Hirano, Y. Lijima, T. Ishiguro, Motion
compensated interframe coding for video conferencing, in Proc. Nat.
Telecommun. Conf., C9.6.1C9.6.5., 1981
S. Zhu, K.K. Ma, A new diamond search algorithm for fast blockmatching motion estimation, IEEE Trans. Image Process., vol. 9, no. 2
pp. 287-290, Feb. 2000.
C. Zhu C., X. Lin L.P. Chau, Hexagon-based search pattern for fast
block motion estimation, IEEE Trans. Circuits Syst. Video Technol.,
vol. 12, no. 5, pp. 349-355, May 2002.
J. Lee, M. Choi, Y. Cho, J. Kim, W.K. Cho, Fast H.264/AVC motion
estimation algorithm using adaptive search range, in Proc. 12th
International Symposium on Integrated Circuits, (ISIC '09); Singapore,
pp. 336-339, Dec. 2009.
M. Bierling Displacement estimation by hierarchical block matching,
in Proc. SPIE Conference on Visual Communications and Image
Processing; San Jose, CA, USA, pp. 942951, Oct. 1998.
K. Lengwehasatit, A. Ortega, Probabilistic partial-distance fast
matching algorithms for motion estimation, IEEE Trans. Circuits Syst.
Video Technol., vol. 11, no. 2, pp. 139-152, Feb. 2001.
C.N. Wang, S.W. Yang, C.M. Liu, T. Chiang, A hierarchical n-queen
decimation lattice and hardware architecture for motion estimation,
IEEE Trans. Circuits Syst. Video Technol., vol. 14, no. 4, pp. 429-440,
Apr. 2004.
A. Saha, J. Mukherjee, S. Sural, New pixel-decimation patterns for
block matching in motion estimation, Signal Process.-Image Commun.,
vol. 23, no. 10, pp. 725-738, Oct. 2008.
W. Li, E. Salari, Successive elimination algorithm for notion
estimation, IEEE Trans. Image Process., vol. 4, no. 1, pp. 105-107, Jan.
1995.
L. Yang, K. Yu, J. Li, S. Li, An effective variable block-size early
termination algorithm for H.264 video coding, IEEE Trans. Circuits
Syst. Video Technol., vol. 15, no. 6, pp. 784-788, June 2005.
J. Feng, K.T. Lo, H. Mehrpour, A.E. Karbowiak, Adaptive block
matching motion estimation algorithm using bit plane matching, in
Proc. of IEEE Int Conf. on Image Processing (ICIP), Washington DC,
USA. pp. 496499, Oct. 1995.
83
84
[37] T.Y. Kuo, C.H. Wang, Fast local motion estimation and robust global
motion decision for digital image stabilization, in Proc. Int. Conf. on
Intelligent Information Hiding and Multimedia Signal Processing,
Harbin, China. pp. 442-445, Aug. 2008.
[38] A. elebi, O. Akbulut, O. Urhan, I. Hamzaolu, S. Ertrk, An all binary
sub-pixel motion estimation approach and its hardware architecture,
IEEE Trans. Consum. Electron., vol. 54, no. 4, Nov. 2008.
[39] A. elebi, O. Urhan, I. Hamzaolu, S. Ertrk, Efficient hardware
implementations of low bit depth motion estimation algorithms, IEEE
Signal Process. Letts., vol. 16, no. 6, pp. 513-516, June 2009.
[40] A. Akn, Y. Doan, I. Hamzaolu, High performance hardware
architectures for one bit transform based motion estimation, IEEE
Trans. Consum. Electron., vol. 55, no. 2, pp. 941-949 , May 2009.
[41] A. Akn, G. Saylar, I. Hamzaolu, High performance hardware
architectures for one bit transform based single and multiple reference
frame motion estimation, IEEE Trans. Consum. Electron., vol. 56, no.
2, pp. 1144-1152, May 2010.
[42] S. K. Chatterjee, Implementation of weighted constrained one-bit
transformation based fast motion estimation, IEEE Trans. Consum.
Electron., vol. 58, pp. 646-653, May 2012.
[43] A. elebi, H. J. Lee, S. Ertrk, Bit plane matching based variable block
size motion estimation method and its hardware architecture, IEEE
Trans. Consum. Electron., vol. 56, pp. 1625-1633, Aug. 2010.
[44] A Celebi, O Urhan High performance hardware architecture for
constrained one-bit transform based motion estimation- Signal
Processing Conference, 2011 19th European, 2011.
[45] J. C. Tuan, T. S. Chang, and C. W. Jen, "On the data reuse and memory
bandwidth analysis for full-search block-matching VLSI architecture,"
IEEE Trans. Circuits and Syst. Video Technol., vol. 12, no. 1, pp. 61-72,
Jan. 2002.
BIOGRAPHIES
Seda Yavuz has been with the Department of
Electronics and Telecommunications Engineering,
University of Kocaeli, Turkey, where she is student of
bachelor degree since 2011. Her current research
interests include motion estimation algorithms and
their implementations using FPGA.