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for
Intro to SystemVerilog 1
Notes:
Slide 1
2
Intro to SystemVerilog 1
Notes:
Slide 2
Course Outline
SV background
Timeline
System Verilog 3.0 pedigree
System Verilog 3.1 adds much more
VCS 7.1 Simulator
SystemVerilog
Variables
19
Data Types
Data Types: Basic & Integer
Data Types: Casting
23
Arrays
Structures
Unions
Unpacked Structures & Unions
Packed Structures & Unions
Lab 1 Union
27
Ports
Port Connection Rules
Lab 2: beh_sram
Implicit port connections
57
Verification
Modeling Characteristics & Models
Black & White Box testing
Transaction-level Verification
Interfaces
System Example: UART
UART beh. interface with methods
65
Intro to SystemVerilog 3
Course Outline
82
Notes:
Slide 3
Hierarchy
Module-centric time specifiers
$root
95
Other Enhancements
True 2-state simulation
literals, string, constant, user, enum
Parameters and redefine-able data types
Enhanced directives
Operators, Event Control - iff
New assignment/increment operators
Procedural Assignments
Continuous Assignments
for loop
disable, break, continue & return
105
RTL ambiguity
New always derivatives
Case/ifelse (unique, priority qualifiers)
Lab 3: Updated FSM style
129
Subroutines
Tasks & Functions
Minilab: automatic tasks/variables
default arguments, explicit calls, pass by reference
Data Scope and Lifetime
139
Interfaces Revisited
Lab 3 (UART): beh_uart.sv
Modports
Lab 4 (UART) : rtl_uart_1.sv
159
Intro to SystemVerilog 4
Course Outline 2
Notes:
Slide 4
177
Course Outline 3
Background
SV 'Unified' Assertions
Immediate Assertions
Concurrent Assertions
Sequences
Operators
Properties
Assert / Cover
Binding
SV 3.1 Preview (Coming attractions)
237
$root in SV3.1
Explicit Hierarchy in SV3.1
Arrays dynamic & associative
Dynamic processes
Process control- wait/disable fork
Even more on interfaces
Classes / Randomization & Constraints
Program Block / Clocking Domains
Sample Solutions
267
285
Intro to SystemVerilog 5
Notes:
Slide 5
6
Intro to SystemVerilog 1
Notes:
Slide 6
SV background
In this section
Intro to SystemVerilog 7
Notes:
Slide 7
Timeline
80's Verilog (Gateway Design Automation)
89
90
91
95
00
01
02
Superlog (CoDesign)
OVL etc
03
Intro to SystemVerilog 8
SystemVerilog 3.0
SystemVerilog 3.1
Notes:
Slide 8
Verification
Engineers
Architects
Verilog
VCS
Hardware
Designers
Intro to SystemVerilog 9
Notes:
Slide 9
Architectural Modeling
Architects
Intro to SystemVerilog 10
Notes:
Slide 10
Hardware
Designers
RTL Design
Intro to SystemVerilog 11
Notes:
Slide 11
Verification
Engineers
Functional Verification
Intro to SystemVerilog 12
Notes:
Slide 12
Abstract Structures
Executable Spec
Interfaces/Protocols
Transaction-level Modeling
Architects
SystemC
Verification
Engineers
System Verilog
VCS
Hardware
Designers
High Level Models
RTL improvements
Timing
Intro to SystemVerilog 13
Notes:
Slide 13
C/C++
Data types
Structs & Unions
Dynamic memory
Intro to SystemVerilog 14
Notes:
Slide 14
Verilog 95
Concurrency & timing
Event Ordering
RTL/gate/switch simulation
Signal strength modeling
Verilog 2001
ANSI port/argument lists
Automatic tasks/functions
Generate statements
Signed Arithmetic
Configurations
Multi-dim arrays
C/C++
Data types
Structs & Unions
Dynamic memory
Intro to SystemVerilog 15
Notes:
Slide 15
Target audience
1.
2.
3.
Intro to SystemVerilog 16
Notes:
Slide 16
Verilog
Verilog
Code
Code
*.v
*.v
VCS 7.1
+v2k
Intro to SystemVerilog 17
+sysvcs
Notes:
Slide 17
Version compatibility
Watch for these icons to tell you where SystemVerilog versions
and tool versions differ
SV
3.1
Part of the SystemVerilog 3.0 language spec. but NOT in the VCS 7.1 beta
DC
Intro to SystemVerilog 18
Notes:
Slide 18
Intro to SystemVerilog 19
Notes:
Slide 19
Intro to SystemVerilog 20
Notes:
Slide 20
Variables
SystemVerilog is 100% backward compatible with Verilog 1995 and 2001.
In addition:
SystemVerilog inherits variables/types from C
SystemVerilog has additional types for system-level design and test
There are 2 types of variable in SystemVerilog
Static
Allocated and initialized at time zero
Exist for the entire simulation
Automatic
Intro to SystemVerilog 21
Notes:
Slide 21
22
Intro to SystemVerilog 1
Notes:
Slide 22
In this section
Intro to SystemVerilog 23
Notes:
Slide 23
string
variable size array of char
void
non-existant data, used for functions
Intro to SystemVerilog 24
char
shortint
int
longint
byte
bit
reg
logic
integer
2-state
( 1, 0 )
4-state
( 1, 0, X, Z )
Notes:
Slide 24
typedef delay;
// known as an empty typedef
delay sec = 1 ;
// declare/initialize even though we dont know yet what it is
typedef int delay;
Intro to SystemVerilog 25
Notes:
Slide 25
<type> (<value>)
Intro to SystemVerilog 26
Notes:
Slide 26
In this section
Multi-dimensional
Using Arrays
Supported datatypes
Supported operations
Array literals
Querying functions
Structure / Union
Initializing
Intro to SystemVerilog 27
Notes:
Slide 27
Arrays - Multidimensions
SystemVerilog supports multi-dimensional arrays just like Verilog
bit [7:0] mem [4:1]; // byte-wide memory with 4 addresses, like Verilog
mem[ i ] [6:1] = 0;
packed
unit
unpacked
SystemVerilog uses the terms packed and unpacked to refer to how the data is actually
stored in memory (e.g. packed => 8-bits to a byte, unpacked => 1 bit per word )
a0
a1
a2
a3
b3 b2 b1 b0
packed
Intro to SystemVerilog 28
unpacked
Notes:
Slide 28
(packed) data
address
(unpacked)
byte2
byte0
byte3
byte2
byte1
byte0
byte3
byte2
byte1
byte0
Intro to SystemVerilog 29
aa
bb[1]
bb[0]
Notes:
Slide 29
10
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
bb[10][1:0] = bb [9][3:2] ;
Intro to SystemVerilog 30
// copy 2 MS bytes
// from word 9 to word 10 (LS bytes)
10
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
10
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Notes:
Slide 30
7:0
10
9
7
6
5
7:0
7:0
7:0
packed
7:0
7:0
7:0
7:0
10
7:0
7:0
Intro to SystemVerilog 31
un
pa
ck
3
2
ed
7:0
7:0
7:0
7:0
NOTE
All unpacked indices must be provided, every time
Use packed indices as needed to slice the packed vector
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
10
7:0
7:0
7:0
Notes:
Slide 31
module use_arrays;
bit[3:0][7:0] bb [10:1];
bit[3:0][7:0] cc [10:1][3:1];
Part 1:
000000ff 00000055 00000022
00000077 00000055 00000022
Part 2:
NOTE
$monitor cannot display the
whole of arrays bb or cc,
but it CAN show the packed
dimensions if you fully
define the unpacked ones!
00000000
33221100
b3221100
aa221100
$monitorh(cc[9][1]);
#100 cc[9][1] = 'h33221100; // initialize 32-bit vector
#100 cc[9][1][3][7] = 1'b1;
// set MSB of MSbyte of 32-bit vector
#100 cc[9][1][3] = 8'haa;
// load MSbyte of 32-bit vector
#100 $display("\n\n");
end
endmodule
Intro to SystemVerilog 32
Notes:
Slide 32
unpacked
a0
a1
a2
a3
Packed
Only bit-level types (reg, wire, logic, bit)
Access whole array or slice as a vector
Compatible with $monitor/$display etc.
Allows arbitrary length integers/arithmetic
bit
packed
[3:0]
bit
b3 b2 b1 b0
[3:0]
Intro to SystemVerilog 33
Notes:
Slide 33
0
10
20
30
40
50
60
UA[4]:
UA[4]:
UA[4]:
UA[4]:
aa,
bb,
ab,
aa,
UB[4]:
UB[4]:
UB[4]:
UB[4]:
bb
bb
ba
ba
initial begin
$monitor($stime,,"PA: %h, PB: %h, UA[4]: %h, UB[4]: %h",PA,PB,UA[4],UB[4]);
Read/write
Read/write of a slice
Read/write of a variable slice
Notes:
Slide 34
module array_ops2;
bit[7:0] PA [3:0];
bit[1:0][7:0] PB [3:0]; // two pkd dimensions
byte UA [7:0];
byte UB [7:0][1:0];
initial
begin
#10 $readmemh("hex.dat",PA);
for(int i=0; i<=3;i++) $display("PA[%0h",i,"]: %b",PA[i]);
#10 $readmemh("hex.dat",PB);
$display("");
for(int i=0; i<=3;i++) $display("PB[%0h",i,"]: %b",PB[i]);
#10 $readmemh("hex.dat",UA);
$display("");
for(int i=0; i<=3;i++) $display("UA[%0h",i,"]: %b",UA[i]);
Intro to SystemVerilog 35
PA[0]:
PA[1]:
PA[2]:
PA[3]:
00000000
00000001
10101010
11111111
PB[0]:
PB[1]:
PB[2]:
PB[3]:
0000000000000000
0000000000000001
0000000010101010
0000000011111111
UA[0]:
UA[1]:
UA[2]:
UA[3]:
00000000
00000001
10101010
11111111
Notes:
Slide 35
Arrays - Examples
bit [2:0][7:0] m = 24b0;
Intro to SystemVerilog 36
Notes:
Slide 36
$bits:
${left|right}:
Bounds of a variable
bit [3:1] [7:4] bb;
bit [3:1] [7:4] cc [2:0];
initial begin
$display( $left(bb) , $right(bb) );
$display( $left(cc) , $right(cc) );
end
// prints 3
// prints 2
1
0
${low|high}:
$increment:
$length:
Intro to SystemVerilog 37
Notes:
Slide 37
2
1
2
3
4
2
1
2
3
4
4
4
4
4
4
32
4
32
768
6144
4
4
4
4
4
8
32
32
8
6
8
Intro to SystemVerilog 38
32
4
32
768
6144
8
32
32
bit [3:0][7:0] a;
bit
b [3:0];
bit
c [3:0][7:0];
bit
[5:0] d [3:0][31:0];
bit [7:0][5:0] d [3:0][31:0];
bit [3:0][7:0] a;
bit
b [3:0];
bit
c [3:0][7:0];
bit
[5:0] d [3:0][31:0];
bit [7:0][5:0] d [3:0][31:0];
6
8
Notes:
Slide 38
Structures
From C SystemVerilog has acquired the idea of a structure.
Think of a structure as an object containing members of any type.
struct { bit[7:0] my_byte;
int
my_data;
char
my_char;
} my_struct;
// my_byte, my_data and my_char are "members" of my_struct.
Intro to SystemVerilog 39
. operator) or altogether
Structures may:
be packed or unpacked.
be assigned as a whole
pass to/from a function or task as a whole
contain arrays
Notes:
Slide 39
Unpacked Structures
By default, structs are unpacked. Their implementation is tool dependant for maximum
flexibility.
a0
a1
Unpacked
a2
a3
struct { bit[1:0]
bit[2:0]
bit[5:0]
bit[8:0]
} u_pkt;
a0;
a1;
a2;
a3;
Intro to SystemVerilog 40
Notes:
Slide 40
Intro to SystemVerilog 41
Notes:
Slide 41
Packed Structures
Packed structs are more useful in hardware simulation. As with arrays, packing means
the elements of the structure are arranged in the form of a wide vector.
a0
a1
a2
a3
struct packed {
bit[1:0]
bit[2:0]
bit[5:0]
bit[8:0]
} p_pkt;
a0;
a1,
a2,
a3;
Intro to SystemVerilog 42
Notes:
Slide 42
Intro to SystemVerilog 43
Notes:
Slide 43
Uses of structures
Structures are ideal way to encapsulate data "packets"
Use as data or control abstraction in architectural models
Use as abstraction for top-down I/O design
Behavioral: pass structures through ports,
as arguments to tasks/functions etc.
Use to refine structure size/content
RTL:
Intro to SystemVerilog 44
Notes:
Slide 44
Lab 1 - Structures
Working directory: video1
Purpose: Declare and use structures
in a real video application
Background:
The file video.sv already contains the code to read in an image file i_mourne.bmp
and to write it out again as new_pic.bmp (using Verilog 2001 FileIO extensions).
The image i_mourne.bmp is 150x400 pixels and is a negative.
Your mission: Modify video.sv to develop the image and produce a positive
1.
2.
Intro to SystemVerilog 45
Notes:
Slide 45
R
R
R
R
150
vertical
R
R
R
R
"X" is unused
bytelane
R X G
R RX XG GB
R RX XG GB
R R
X RX
G XG
B GB
RX R
XG X
GB G
B B
R X X GGB B
R X XGGB B
R X G
X G B
R R X XG GB
R R X X G G B
R R
X RX
G XG
B GB
RX R
XG X
GB G
B B
R X XG GB B
RX XG GB B
X G B
B
B
B
B
B
B
B
B
400
horizontal
32 bits
Instructions:
1.
Intro to SystemVerilog 46
Notes:
Slide 46
invert;
saveimg;
$fclose(rfile);
$fclose(wfile);
$finish;
end
Intro to SystemVerilog 47
Notes:
Slide 47
Unions
This is another concept borrowed from C.
In C/C++
Union is a specialized form of struct
Memory footprint is the size of the largest member
All members begin at the same memory address
Only one member may be assigned/read
This also describes unpacked unions in SV (Not very useful for h/w)
Notes:
Slide 48
Packed Unions
A packed union contains 1 or more packed members
All members are the same size and occupy the same space
Data may be written via one member, read by another
The union may be accessed as a whole
union packed {
int
a;
integer b;
reg[31:0] c;
} p_union;
b
p_union
Characteristics
Easy conversion to bit-vectors
May be accessed as a whole
First member specified is most significant
May be declared as signed for arithmetic
Non-integer datatypes (e.g. real) are NOT allowed.
Unpacked arrays/structures are NOT allowed
if any member is 4-state, all members are cast to 4-state
Intro to SystemVerilog 49
Notes:
Slide 49
Intro to SystemVerilog 50
Given:
byte b;
b = u1.bits[87:80];
b = u1.bytes[10];
b = u1.mps.f2;
Notes:
Slide 50
Lab 2 - Union
Working directory: union
Purpose: Reinforce the syntax and usage of union
Instructions:
Modify the file: pu_bytex.sv as follows
1.
2.
64 bits
Write a function called bytext to extract the specified byte from a 64-bit value.
Use a union within the function to achieve the byte extraction.
i.e. write one member with 64 bits, read from another member (8-byte lanes).
Intro to SystemVerilog 51
Notes:
Slide 51
aabbccddeeff0011
8
64 bits
initial
begin
bus = 64'haabbccddeeff0011;
for(int i=8; i>0; i--)
$displayh(bytext(bus,i));
end
aa
aa
bb
bb
cc
cc
dd
dd
ee
ee
ff
ff
00
00
11
11
endmodule
Intro to SystemVerilog 52
Notes:
Slide 52
module mod1;
Structure Expressions
typedef struct {
logic [7:0] a;
int b;
} my_struct;
my_struct s1 ;
NOTE
SV distinguishes between structure expressions (as shown here)
and ordinary concatenations by the context.
If the LHS of an assignment is an unpacked structure,
its a structure expression. Otherwise, { } represent concatenation.
initial begin
$monitor("my_struct s1.a: %h, s1.b: %h",s1.a, s1.b);
Intro to SystemVerilog 53
// assign by position
// assign by name
// default: operator
// assign by type, others default
// assign by type and by name
my_struct
my_structs1.a:
s1.a:xx,
xx,s1.b:
s1.b:00000000
00000000
my_struct
s1.a:
05,
s1.b:
my_struct s1.a: 05, s1.b:00000006
00000006
my_struct
my_structs1.a:
s1.a:06,
06,s1.b:
s1.b:00000005
00000005
my_struct
my_structs1.a:
s1.a:07,
07,s1.b:
s1.b:00000007
00000007
my_struct
my_structs1.a:
s1.a:01,
01,s1.b:
s1.b:00000009
00000009
Notes:
Slide 53
Arrays - literals
Like C, SystemVerilog supports array literals but with the additional feature of
the replicate operator. The key to understanding array literals is to remember the
dimensions of the array and use { } to match those dimensions exactly.
// 3 groups of 4
// 2 groups of 3
Intro to SystemVerilog 54
// a group of 12 chars
Notes:
Slide 54
Arrays literals 2
Sometimes it is handy not to have to explicitly define each value of the array. For this
the default keyword is provided:
// All elements 5
Intro to SystemVerilog 55
Notes:
Slide 55
Intro to SystemVerilog 56
12
11
10
9
8
7
6
5
4
3
2
1
Notes:
Slide 56
In this section
Intro to SystemVerilog 57
Notes:
Slide 57
Module Ports
Like Verilog 2001 SystemVerilog allows co-declaration of port AND type
port_direction port_type port_name, port_name ... ;
input wire a, into_here, george;
output reg [8:31] out_bus;
Port declarations can also be made within the parentheses of the module
declaration (also in Verilog 2001).
module MUX2 (output logic [1:0]
input logic [1:0]
input
[1:0]
out,
in_a, in_b,
sel ) ;
Ports may be of ANY SystemVerilog type including events, structs, arrays etc.
typedef struct {
bit isfloat;
union { int i; shortreal f; } n;
} tagged; // named structure
module mh1 (input event e1, input int in1, output tagged out1);
...
endmodule
Intro to SystemVerilog 58
Notes:
Slide 58
net,
reg,
logic
etc.
net
reg,
net,
logic
tri
tri
Any
compatible type
non-wire
port type
(e.g. logic)
net
Any
SystemVerilog type
module
tri
tri
SystemVerilog only
Any
SystemVerilog type
Intro to SystemVerilog 59
Net type
only
Notes:
Slide 59
NOTE
SV3.0 implied a difference
between reg and logic types.
Under SV3.1 reg and logic
are semantically identical.
Intro to SystemVerilog 60
Notes:
Slide 60
Lab 3: beh_sram
Working directory: beh_sram
Purpose: Apply new features of SV like UDTs, structs, new SV port-types.
Instructions:
Write an abstract behavioral model of a syncrhonous sram memory
Intro to SystemVerilog 61
beh_sram
ip
op
32bits
clk
rw_
mem
array 1k
Notes:
Slide 61
Lab 3: beh_sram
beh_sram
ip
op
typedef struct {
logic [9:0] addr;
logic[31:0] data;
} packet;
32bits
clk
rw_
mem
array 1k
Question: Where do you declare the packet typedef? Think about it, experiment!
Intro to SystemVerilog 62
Notes:
Slide 62
40
40 Writing
Writing 0000000a
0000000a to
to address
address 005
005
80
Writing
00000002
to
address
001
80 Writing 00000002 to address 001
146
146 Read
Read successful:
successful: 0000000a
0000000a from
from address
address 005
005
186
Read
successful:
00000002
from
address
186 Read successful: 00000002 from address 001
001
200
Writing
0000aaaa
to
address
1ff
200 Writing 0000aaaa to address 1ff
266
266 Read
Read successful:
successful: 0000aaaa
0000aaaa from
from address
address 1ff
1ff
Intro to SystemVerilog 63
Notes:
Slide 63
64
Intro to SystemVerilog 1
Notes:
Slide 64
In this section
Modeling characteristics
Abstraction levels
White vs black box
Transaction level modeling
Interfaces
Who needs them and why
Simple bundled
Methods
Intro to SystemVerilog 65
Notes:
Slide 65
Intro to SystemVerilog 66
Notes:
Slide 66
Model Functionality
TF
BCA
Model Interface
PCA
Model types
Intro to SystemVerilog 67
Often
Oftenhave
haveoverlapping,
overlapping,
mixed,
definitions
mixed, definitions- source
sourceof
ofconfusion
confusion
Notes:
Slide 67
Model Functionality
TF
BCA
Model Interface
PCA
Intro to SystemVerilog 68
Notes:
Slide 68
Model Functionality
TF
BCA
Model Interface
PCA
Intro to SystemVerilog 69
Notes:
Slide 69
Model Functionality
TF
BCA
Model Interface
PCA
Intro to SystemVerilog 70
Notes:
Slide 70
Model Functionality
TF
BCA
Model Interface
PCA
Intro to SystemVerilog 71
Notes:
Slide 71
Model Functionality
RT
UT
TF
BCA
Model Interface
PCA
Every register, every bus, every bit described for every cycle
Intro to SystemVerilog 72
Notes:
Slide 72
Model Functionality
SAM
TF
RTL
RT
UT
TF
BCA
Model Interface
PCA
Model functionality
UTF
Algorithmic behavior
Sequential behavior modeled
Useful for
Architecture exploration
Algorithm determination & proof
Intro to SystemVerilog 73
Notes:
Slide 73
Model interface
TF or UTF
No pin-level detail
Communication protocols
Model Functionality
SAM
SPM
TF
RTL
RT
UT
TF
BCA
Model Interface
Model functionality
TF or UTF
Algorithmic behavior
Processes are assigned time
Concurrent behavior modeled
Not cycle accurate
Useful for high-level performance modeling and time budgeting
Intro to SystemVerilog 74
Notes:
Slide 74
TF
Not pin-level detail
Data transfer modeled as transactions
May or may not be BCA
Model Functionality
SAM
SPM
TLM
TF
RTL
RT
UT
TF
BCA
Model Interface
PCA
Model Functionality
TF
Not cycle accurate
Behavior described in terms of transactions
May have a system clock
Intro to SystemVerilog 75
Notes:
Slide 75
Model Functionality
Functional Model
UT
FM
SAM
SPM
TLM
TF
RTL
RT
UT
TF
BCA
Model Interface
PCA
Intro to SystemVerilog 76
Notes:
Slide 76
System Architectural
System Performance Models
Transaction Level Model
Functional Model
Model Functionality
SAM FLM
SLM
BLM
SPM
TLM
TF
RTL
RT
UT
TF
BCA
Model Interface
PCA
Intro to SystemVerilog 77
Notes:
Slide 77
Model Functionality
SAM FLM
SLM
BLM
SPM
BSyn
TLM
TF
RTL
RT
UT
TF
BCA
Model Interface
PCA
Module functionality
TF
Not cycle accurate
Intro to SystemVerilog 78
Notes:
Slide 78
Model interface
Model Functionality
SAM FLM
SPM
BSyn
TLM
TF
BFM
RTL
RT
UT
PCA
SLM
BLM
TF
BCA
Model Interface
PCA
Module functionality
Typically described as transactions
Intro to SystemVerilog 79
Notes:
Slide 79
Intro to SystemVerilog 80
Notes:
Slide 80
Classes
Semaphores & Mailboxes
Program blocks
Clock Domains
Constrained random-number generation & coverage
Intro to SystemVerilog 81
Notes:
Slide 81
Interfaces
Great simulation efficiency can be achieved by modeling the blocks of a system at
different levels of abstraction, behavioral, rtl, gate etc.
Traditionally, the interface between these blocks has always remained at the lowest
wire level. High-performance system-level simulation requires the abstraction of interblock communication. To this end, SystemVerilog introduces the concept of interfaces.
data
MMU
addr
rw_
MEM
ena
interface
At its simplest
an interface is
like a module
for ports/wires
Traditional
Verilog code
Intro to SystemVerilog 82
interface interf;
logic [7:0] data;
logic [15:0] addr;
logic ena, rw_;
endinterface
SystemVerilog
Notes:
Slide 82
What is an Interface?
An interface defines a set of signals via which two or more modules may
communicate as well as a set of methods or tasks by which those modules
can communicate over the interface.
Interfaces bring abstraction-level enhancements to ports, not just internals.
At its simplest, an interface is like a module for the wires between modules.
An interface may contain any legal SystemVerilog code except module definitions
and/or instances. This includes tasks,functions, initial/always blocks, parameters
etc.
Interfaces are defined once and used widely, so it simplifies design.
e.g. Changing a bus spec (add a new signal?) means editing the interface only.
Interfaces may be hierarchical. This can allow modeling the interface at different
abstractions with all the performance benefits we see in design abstraction changes.
Intro to SystemVerilog 83
Notes:
Slide 83
CPU
Intro to SystemVerilog 84
Peripheral
TB1
TB2
SYSTEM_TB
CPU
Peripheral
Notes:
Slide 84
Intro to SystemVerilog 85
FireW
PAR
USB
v2
SER
USB
V1
SYSTEM_TB
CPU
Communication
Interface
Peripheral
Notes:
Slide 85
RTL
UTF
TF
PCA
BCA
SYSTEM_TB
CPU
Interface
Peripheral
Notes:
Slide 86
module definition
module definition
module top;
logic req, gnt, start, rdy; // req is logic not bit here
logic clk = 0;
logic [1:0] mode;
logic [7:0] addr, data;
Complete portlist
Complete portlist
Instantiate/connect everything
endmodule
Intro to SystemVerilog 87
Notes:
Slide 87
endmodule
module cpuMod(simple_bus b, input bit clk);
...
endmodule
module top;
logic clk = 0;
Top-level module
simple_bus sb_intf;
// Instantiate the interface
memMod mem(sb_intf, clk); // Connect the interface to the module instance
cpuMod cpu(.b(sb_intf), .clk(clk)); // Either by position or by name
Instantiate/connect everything
endmodule
Intro to SystemVerilog 88
Notes:
Slide 88
Interface Ports
Ports may be defined to an interface. This allows external connections to the
interface to be made and hence automatically to all modules which instantiate
the interface This is most commonly used for clk nets.
interface simple_bus (input bit clk); // Define the interface
logic req, gnt;
logic [7:0] addr, data;
logic [1:0] mode;
logic start, rdy;
endinterface: simple_bus
2 simple_bus instances
cpu/memory pair 1
cpu/memory pair 2
Notes:
Slide 89
Modules with
simple_bus interface
module top;
logic clk = 0;
simple_bus sb_intf(clk); // Instantiate the interface
memMod mem(.a(sb_intf));
cpuMod cpu(.b(sb_intf));
endmodule
Intro to SystemVerilog 90
Notes:
Slide 90
Stimulus
generator
Serial link
Response
check
At the behavioral level, we might abstract the serial link to a ridiculously trivial level
bit [0:31][7:0] serial_link;
initial
serial_link = "Mr Watson, come here...");
always @(serial_link)
if (serial_link === "Mr Watson, come here...")
$display("Correct string received")'
This is a silly abstraction but it does make you think: What if, at the highest level
testing were as simple as this?
What if, as we progress from algorithm-model to RTL, we were able to always test
from such a familiar abstract level, freeing our test language from low-level details
of the UART interface etc
Intro to SystemVerilog 91
Notes:
Slide 91
I/F: rs232_beh
Serial link
stimgen
send_string
rcv_string
send_string
response_check
interface rs232_beh;
bit [0:31][7:0] string;
logic valid = 0;
bit reset;
module response_check(
endmodule
Intro to SystemVerilog 92
endtask
send_string
method
end
endmodule
rcv_string
rcv_string
method
endinterface
2003,2004 Willamette HDL, Inc.
Notes:
Slide 92
Instructions:
1.Edit the file "beh_uart.sv" and complete the behavioral model.
Add rcv_string method to interface (follow valid protocol)
Add response_check module (with calls to rcv_string)
Follow stimgen code as to structure.
Expected output
Correct
Correctstring
stringreceived:
received:
Correct
Correctstring
stringreceived:
received:
Intro to SystemVerilog 93
Mr
MrWatson,
Watson,come
comehere...
here...
I Iwant
wanttotosee
seeyou.
you.
Notes:
Slide 93
`timescale 1ns/1ns
interface rs232_beh;
bit [0:31][7:0] string;
logic valid = 0;
bit reset;
task send_string(input bit [0:31][7:0] text);
wait(valid ==0);
string = text;
valid = 1;
endtask
endinterface
rs232_beh IB();
stimgen ST1(IB);
initial
begin
repeat(20) @(negedge clk);
reset = 1;
repeat(50) @(negedge clk);
reset = 0;
end
endmodule // top_level
endmodule
Intro to SystemVerilog 94
Notes:
Slide 94
In this section
Enhancements
Time specifiers
$root
Intro to SystemVerilog 95
Notes:
Slide 95
Hierarchy
SystemVerilog adds several enhancements to design hierarchy:
Intro to SystemVerilog 96
Notes:
Slide 96
$root
In Verilog, all code (except `compiler directives) is contained in modules.
SystemVerilog defines a top-level called $root which exists outside of but
contains any/all design code. It typically spans multiple files.
$root may contain:
Explicitly declared & instantiated modules
Un-instantiated module declarations (auto-instantiated at $root)
Compatible with Verilog
Interfaces
Task, Function declarations, accessible throughout hierarchy
Constants, parameters and other global definitions
Gate, net, variable declarations, visible throughout design hierarchy
Typedefs in $root are allowed
$root variables may be accessed via $root.<var>
SV features unsupported in the current release
Procedural statement block (more later)
NOTE: In $root initial/always blocks are illegal
Intro to SystemVerilog 97
Notes:
Slide 97
Usefulness of $root?
1. As an abstract communication layer 'above' the hardware
behavioral modeling
testbench structure/control
2. Correct location for:
global functions & tasks
global typedefs
interface declarations
Implicit instantiation of global modules (Verilog 95 compat.)
NOTE
SystemVerilog encourages/expects the use of global typedefs (in $root).
BEWARE! This may require a specific order for file compilation!
Intro to SystemVerilog 98
Notes:
Slide 98
$root example
typedef in $root
global_pkt b;
local1 U1();
initial
begin
#10 b.data = 1; b.addr = 1;
global_task(b);
end
endmodule
module local1;
logic [7:0] x;
global_pkt y;
initial
begin
#20 y.data = 2; y.addr = 2;
global_task(y);
#20;
$root.root_pkt.data = 3;
$root.root_pkt.addr = 3;
global_task($root.root_pkt);
end
endmodule
Intro to SystemVerilog 99
Notes:
Slide 99
typedef in $root
module tb;
bit cs, rw_;
packet in_pkt, out_pkt;
beh_sram.sv
revisited
endmodule
Notes:
Slide 100
SystemVerilog adds two new ways to reduce the chore of instantiation for the
common situation where port and connected signal match in name and size.
Consider this 4:1 mux:
module mux (output logic [2:0] out, input logic [2:0] a, b, c, d, sel);
.* syntax instantiation
Notes:
Slide 101
Ports and their connecting variables must have same name and same width
Ports and their connecting variables must be of compatible type
Ports outside of the implicit list must be connected by port name (not order)
.* allows full wildcarding where listing port & signal names is not required
Notes:
Slide 102
initial
#5.19 $display(Current time is %f, $realtime); // SV3.1 will allow #5.19ns
endmodule
Current time is 5.200000
V C S S i m u l a t i o n
Time: 5200ps
R e p o r t
NOTE
timeunit & timeprecision are
local to a module, they are not
`directives that can affect
modules compiled later in
sequence.
Notes:
Slide 103
104
Intro to SystemVerilog 1
Notes:
Slide 104
Other
In this section
2-state simulation
C Operators
Event control
SV Event Queue
Reducing ambiguity
Combinational / Latch / Sequential
unique / priority qualifiers
Loops
break / return
Notes:
Slide 105
To speed up functional verification, simply code with bit and int types
Simulators (including VCS) have offered pseudo 2state modeling but
results are not portable across simulators and certain assumptions
are always made.
SV makes it simpler!
Notes:
Slide 106
Literals
SystemVerilog allows easy specification of un-sized literal values
with the ( ) apostrophe:
0, 1, x, X, z, Z
reg [23:0] a = z;
// vertical tab
// form feed
// bell
// hexadecimal number
Notes:
Slide 107
Constants
SystemVerilog defines 3 types of constant:
localparam char colon1 = ":" ;
specparam int delay = 10 ;
const logic flag = 1 ;
The const keyword effectively means the variable may not be written by user code.
It's value is set at run-time and it can contain an expression with any hierarchical path name.
const logic option = a.b.c ;
A const may be set during simulation within an automatic task (discussed later).
Notes:
Slide 108
String datatype
SV
3.1
String data type is a variable size array of characters, indexed from 0 to N-1 (N is array length).
Every element of the array is also a string
string st1, st2;
st1 = ;
st2 = abc;
st1 = { st1, st2 };
st2[0:1] = et;
// null string
// assigned from a string literal
// concatenation, st1 becomes abc
// st2 becomes etc
Supports relational operators (==, !=, <, <=, >, >=), concatenation ({}) and replication ({n{}})
e.g. (a<b) is true because a precedes b alphabetically.
By means of the . operator, strings support special methods:
len(), putc(), getc(), toupper(), tolower(), compare(), icompare(), substr(),
atoi(), atohex(), atooct(), atobin(), atoreal(),
itoa(), hextoa(), octtoa(), bintoa() and realtoa()
Notes:
Slide 109
Enumerated type
SystemVerilog provides enumeration as a very useful way of defining abstract variables.
Define an enumeration with enum (defaults to int type)
enum {red, green, yellow} traf_lite1, traf_lite2;
NOTE:
Default assigned values start at zero
0
1
2
enum {red, green, yellow} lite;
Enumerated Type
Notes:
Slide 110
Enumeration (2)
Consider this enumeration
enum {red, green, yellow} lite1, lite2;
NOTE
While int is the default type of an enum, all SV types are supported.
enum bit[7:0] {red = 7b0, grn, blu} RGB
Notes:
Slide 111
0000000000000000
00000000000000aa
bb000000000000aa
Notes:
Slide 112
Notes:
Slide 113
Enhanced directives
SystemVerilog extends `define macros to allow construction of strings and
identifiers.
For example:
module enh_direct;
bit[2:0][7:0]a[3:0];
int b;
byte c;
10 a[3][2]: 0 b: 1 c: 2
endmodule
Notes:
Slide 114
Operators
In addition to the standard Verilog operators, SystemVerilog adds C operators:
Assignment:
Bump:
+=, -=, *=, /=, %=, &=, ^=, |=, <<=, >>=, <<<=, >>>=
// Implemented as blocking assignments
++a, --a, a++, a
// available as blocking assignments only
NO RHS timing constructs
Power:
**
b = 1;
if( (a=b) )
WARNING: While 'cool' in principle, this creates a HUGE likelihood for mistakes
Notes:
Slide 115
a <<= b-1;
a >>= b;
a &= b;
a ^= b;
a |= b;
// a <- 16
// a <- 0
// a <- 2
// a <- 1
// a <- 3
3
6
0
2
5
-1
Notes:
Slide 116
SystemVerilog also adds bump operators ala C/C++. These may be used in expressions
but may NOT be associated with timing controls:
module pre_post_inc;
integer a;
++i
--i
// pre increment
// pre-decrement
i++
i--
// post-increment
// post-decrement
initial
begin
a = 3;
$display("%0d", a);
$display("%0d", a++, " <-post increment");
$display("%0d", a);
a = 3; $display("");
$display("%0d", a);
$display("%0d", ++a, " <-pre increment");
$display("%0d", a);
end
endmodule
Intro to SystemVerilog 117
3
3 <- post increment
4
3
4 <- pre increment
4
Notes:
Slide 117
q
Transp
latch
- Here the event expression triggers only if the conditional is met at that instant.
- Useful simulation speedup ( avoid unnecessary assignments to q )
Notes:
Slide 118
Notes:
Slide 119
Notes:
Slide 120
#2
10
20
40 41
1:
always @ (b)
a = b;
2:
always @ (b)
#2 a = b;
3:
always @ (b)
a = #2 b;
4:
always @ (b)
a <= b;
5:
always @ (b)
#2 a <= b;
6:
always @ (b)
a <= #2 b;
12
22
42 43
10
20
40 41
b
1
:
2
:
Notes:
3
:
4
:
5
:
always @ (b)
a = b;
always @ (b)
#2 a = b;
always @ (b)
a = #2 b;
always @ (b)
a <= b;
always @ (b)
#2 a <= b;
always @ (b)
a <= #2 b;
Slide 121
Procedural Assignments
WHDL's famous rules of thumb:
always @(a or b)
c = a & b;
Notes:
Slide 122
Continuous Assignments
In Verilog, continuous assignments apply only to wires.
SystemVerilog allows continuous assignments to all data types INCLUDING registers.
reg a, b;
bit enable;
assign a = enable ? b : z;
A variable may only be driven by a single continuous assignment or by one output port.
Variables may not also be initialized or assigned in procedural code
logic a = 0, b;
bit enable;
assign a = enable ? b : z; // ILLEGAL because a was initialized
module uu (input logic b, output logic a); // dummy module
endmodule
uu U1(.a(a), .b(b)); // ILLEGAL because a is driven by contin. assign above (and initialized )
Notes:
Slide 123
Loops
SystemVerilog supports standard Verilog loop constructs: repeat, forever, while and for
but also adds:
do <statement> while <expression>
Like a while loop, but evaluates after the loop executes rather than before.
examples
i = i +1;
end
do
begin
i = i +1;
end
while (i < 10) ;
Guaranteed to execute
AT LEAST once
Notes:
Slide 124
for loop
SystemVerilog allows the loop variable to be declared within the loop.
Verilog 2001:
int j;
initial
for ( j = 0; j <= 20; j = j+1) // j is global and could be accidentally
// modified elsewhere
$display(j);
SystemVerilog:
initial
for ( int j = 0; j <= 20; j++) // j is local
$display(j);
Never again worry about double-use of
a variable because of CUT/PASTE
Notes:
Slide 125
Notes:
Slide 126
return
Within a function we can specify a return value by assignment to the function-name
or by using the new C-like return.
Tasks containing a return statement will terminate when the return is executed.
Notes:
Slide 127
128
Intro to SystemVerilog 1
Notes:
Slide 128
RTL
In this section
Notes:
Slide 129
Latch logic:
always_latch <statement> // latch inference doesnt trigger a simulator warning
Notes:
Slide 130
end: hier_name
initial
fork: hier_name
a = 0;
$display(hello);
join: hier_name
end
label: syntax
b = bus_b;
NOTES:
1. begin or end statements may be labeled but NOT if
they are also named.
2. Verilog allows local variables to be defined within a
named_block. SystemVerilog allows local variables
to be declared inside ANY begin..end, fork..join block
Notes:
Slide 131
Example: always_comb
module test_always_comb;
logic [7:0] a=0,b=0,c,d;
always_comb
begin
$display($stime,,"always_comb: func(%d)",a);
c = func(a);
end
always @*
begin
$display($stime,,"always @*: func(%d)",a);
d = func(a);
end
function logic[7:0] func (logic[7:0] a);
return a & b;
endfunction
initial begin
$monitor($stime,,"a:%d, b:%d, | c:%d, d:%d \n",a,b,c,d);
#10 a = 1;
#10 b = 1;
#10 a = 0;
#10 a = 1;
#10 $stop;
end
endmodule
NOTE
always_comb is sensitive to
variable changes within
functions ( unlike @* )
0 always_comb: func(
0 always @*: func( 0)
0 always_comb: func(
0 always_comb: func(
0 a: 0, b: 0, | c: 0, d:
0)
0)
0)
0
10 always_comb: func( 1)
10 always @*: func( 1)
10 a: 1, b: 0, | c: 0, d: 0
20 always_comb: func( 1)
20 a: 1, b: 1, | c: 1, d: 0
30 always_comb: func( 0)
30 always @*: func( 0)
30 a: 0, b: 1, | c: 0, d: 0
40 always_comb: func( 1)
40 always @*: func( 1)
40 a: 1, b: 1, | c: 1, d: 1
Notes:
Slide 132
do_that
do_the_other
end
always_comb
begin
do_this_func();
do_that_func();
do_the_other_func();
end
Notes:
Slide 133
Verilog case statement variants case, casex & casez are enhanced to improve
synthesis results. This should allow identical interpretation by simulators, synthesis tools
and others without the ambiguities of Verilog 95:
bit[2:0] a
unique case(a)
// values for a of 3,5,6 or 7 produce runtime warnings
0,1: $display(0 or 1);
VCS7.1b does not give runtime warnings
2: $display(2);
4: $display(3);
endcase
// unique - checks to ensure no overlapping case values
priority casez(a)
3b00?: $display(0 or 1);
3b0??: $display(2 or 3);
default: $display(4, 5, 6 or 7);
endcase
// priority act on first match and ignore others if any.
NOTE
These qualifiers should obsolete the synthesis pragmas:
// syn parallel_case full_case
A good coding style is to avoid using ANY of these pragmas/qualifiers by writing
completely thorough case/if-else structures
Intro to SystemVerilog 134
Notes:
Slide 134
priority if (a[2:1]==0)
$display(0 or 1);
else if (a[2]==0)
$display(2 or 3);
else $display(4 to 7); // covers all possible values, so no error
If either unique or priority is used and there is no explicit else, a run-time error triggers
if no match occurs.
Notes:
Slide 135
Instructions:
Copy/modify the existing file to make fsm_ex.sv as follows:
1. Testbench: test_fsm_ex.sv
2. Implement fully ANSI compatible ports
3. Update data-types ( e.g. state variables to enum) as appropriate
4. Use new always block styles ( always_ff, always_comb )
5. Qualify the next_state logic using unique
6. Implement output decode logic using continuous assignments ( to a, b)
7. Compare the output between the old and new versions.
Are they identical?
Notes:
Slide 136
Notes:
Slide 137
138
Intro to SystemVerilog 1
Notes:
Slide 138
In this section
Task enhancements
Function enhancements
Recursion
Default arguments (3.1)
Explicit calls
Pass by reference (3.1)
Data scope and lifetime
Notes:
Slide 139
Notes:
Slide 140
Notes:
Slide 141
Tasks (Recursion)
SystemVerilog makes major extensions to basic Verilog syntax.
Supports automatic keyword (from Verilog 2001)
Unlike Verilog, all local variables are dynamically declared.
Full recursion is supported (automatic variables/arguments stored on stack)
task automatic my_task( input int local_a,
int local_b);
if (local_a == local_b)
begin
my_task(local_a-1,local_b+1);
return;
end
global_a = local_a;
global_b = local_b;
endtask
Notes:
Slide 142
Instructions:
Compile/simulate the two example modules in the working directory.
vcs R +sysvcs auto_task.sv
vcs R +sysvcs seq_task.v
See if you can understand what is going on in each case!
Notes:
Slide 143
task classic_task;
input [3:0] a;
output [3:0] b;
begin
#10 b = a;
$display ($stime,,"Input: %h,
Output: %h", a,b);
end
#10 b = a;
$display ($stime,,"Input: %h,
Output: %h", a,b);
endtask
endtask
initial
fork
classic_task (4, out_1);
// input value 4
#5 classic_task (8, out_2); // input value 8
join
initial
fork
super_task( 4, out_1 );
// input value 4
#5 super_task (8, out_2); // input value 8
join
10
10Input:
Input:8,8, Output:
Output:88
15
15Input:
Input:8,8, Output:
Output:88
25
25Input:
Input:4,4, Output:
Output:44
30
30Input:
Input:8,8, Output:
Output:88
Notes:
Slide 144
// input value 4
// input value 8
15
15Input:
Input:5,5, Output:
Output:55
25
25Input:
Input:6,6, Output:
Output:66
Notes:
Slide 145
Functions
function automatic int factorial (int n);
if (n==0) return(1);
// factorial 0 is 1
else return(factorial(n-1)*n);
endfunction
Notes:
Slide 146
Notes:
Slide 147
module super_func;
int n;
parameter MAX = 10;
initial
begin
$display("The factorials from 1 to %d", MAX);
for (n=0; n<=MAX; n=n+1)
$display("%d! = %d", n, factorial(n));
$display("And again, the factorials from 1 to %d", MAX);
v_factorial(MAX);
end
function automatic int factorial (int n);
if (n==0) return (1); // factorial 0 is 1
else return (factorial(n-1)*n);
endfunction
10
Notes:
Slide 148
SV
3.1
endtask
// both default to 0
// default to 2
Notice Verilog placeholder syntax has a new significance for default arguments:
initial
begin
do_this(5,2,0);
do_this(5,2);
do_this( , ,0);
end
Notes:
Slide 149
int a = 0,
int b = 1,
output int c );
if ( a === b )
c = 1;
else
c = 0;
endtask
int a = f_compare( x, y );
int b = f_compare( .m(5), .n(5) );
int c = f_compare( .n(3) );
initial begin
#10 t_compare( 1, 8, z );
#10 t_compare( .b(2), .a(4), .c(z) );
#10 t_compare( .c(z), .a(1) );
#10 vf_compare(.n(9) );
end
SV
3.1
implicit
explicit
explicit
explicit
NOTE
SystemVerilog 3.1 allows
tasks and functions to be
called with a syntax similar
to module instantiation-byport-name
Cannot mix explicit and
implicit parameter-passing
styles
Notes:
Slide 150
SV
3.1
end{task/function}
Tasks also support inout
Notes:
Slide 151
SV
3.1
Notes:
Slide 152
Static vs Automatic
In Verilog 2001 and of course in SystemVerilog, a variable can be:
static
automatic
As in Verilog, data items default to static, but SV allows use of the static
keyword within an automatic task/function/named block to override the
default for any variable.
Notes:
Slide 153
Data
Scope
Lifetime
global
local
duration of call **
local
static
**
static
Data declared as automatic, even if inside a static task, function or block will have a lifetime the
same as the call. Automatic variables may not be used to trigger event expressions or be written
by a non-blocking assignment.
Notes:
Slide 154
Notes:
Slide 155
Lab 6 histogram
Working directory: video6
Purpose: Derive histogram of the image.
Background:
In digital images, each pixel is described by 8-bit values of RED, GREEN & BLUE.
So, for a particular color plane, each pixel can be of value 0 (off) to 255 (full-on).
# of pixels
0 1 2 3
Intro to SystemVerilog 156
. . . .
...
255
(Dynamic range)
Notes:
Slide 156
# of pixels
Lab 6 histogram
Instructions:
1.
2.
3.
. . . .
...
255
(Dynamic range)
4.
5.
0 1 2 3
Walk the entire video array (150x400) and count the number of pixels of
each intensity (0-255)
Find the largest of these numbers (most common pixel intensity N)
Determine an int value called scale from the formula: scale = N / 72
This will be used when drawing the histogram to scale the graph.
Return int scale value from function buildhist as shown on next page
Compile/run video.sv and view output file new_pic.bmp
Notes:
Slide 157
Lab 6 histogram
module video6;
typedef struct packed {byte R, X, G, B;} RGB;
RGB vidbuf[1:150][1:400] ; // Unpacked array of RGB
byte hdr [1:56];
int rfile, wfile, ifs, i, scale;
int histogram [0:255]; // array to hold histogram data
// invert task not shown
// function saveimg not shown
function void painthist(input int scale);
// Paint histogram on top of image
//
int ver = 30, hor = 72; // centre hist on pic
for(int pixels=1; pixels<256; pixels++)
for(int i=1; i <= histogram[pixels]/scale; i++)
vidbuf[150 - ver - i][400 - hor - pixels] = 'hff;
endfunction
Expected output
initial
begin
rfile = $fopen("mourne_32.bmp", "r"); // Open the image file
wfile = $fopen("new_pic.bmp", "w"); // Open output img file
i = $fread(hdr, rfile, 0, 56);
// Read 56-byte header
i = $fread(vidbuf, rfile);
// Read the file into memory
ifs = $ftell(rfile);
// capture filesize in "ifs"
$display("Loaded %0d pixels \n", ifs);
invert;
scale = buildhist() ; // Build histogram and return scale factor
painthist(scale);
saveimg;
$fclose(rfile);
$fclose(wfile);
$finish;
end
endmodule
Notes:
Slide 158
Revisited
In this section
Mailbox
Modports
Controlling methods by modports
Method import & export
Notes:
Slide 159
stimgen
send_string
response_check
send_mailbox
rcv_string
rcv_mailbox
Mailboxes allow stimgen and response_check routines to operate independently but never get out of synch
For example, an attempt by response_check to read an empty rcv_mailbox will block until a string arrives
Stimgen can queue up as many send_string calls as desired, they will always execute in the right order
or it might be setup to block stimgen until each send_string completes (send_mailbox FIFO depth == 1)
Notes:
Slide 160
stimgen
clk
send_string
rs232_host_rx
rs232tx
clock_gen
rs232rx
rcv_string
response_check
Serial clk
Here, at a later stage in development, 3 RTL UART modules have been written
rs232tx (serial transmit), rs232rx (serial receive), clock_gen (support circuitry)
2 new interfaces ( rs232_host_tx and rs232_host_rx ) connect the RTL UART code
to the original stimgen and response_check modules from the behavioral model.
This means the same test harness can operate on a behavioral --or-- RTL model of the system.
All code contained in the file: interface/rtl_uart/rtl_uart.sv
Notes:
Slide 161
UART rs232_host_tx
load_request
rs232_tx
tx_data
serial_out
load
clk
reset
data_byte
start_bit
stop_bit
endtask
endinterface
Notes:
Slide 162
UART rs232_host_rx
data_ready
rs232_rx
serial_in
rx_data
Interface:
rs232_host_rx
read
clk
rx_clk
reset
error_over_run
error_under_run
error_all_low
serial_in
rx_data
data_ready
read
error_over_run,
error_under_run,
error_all_low
Notes:
Slide 163
RTL top_level
top_level
rs232_host_tx
stimgen
clk
send_string
rs232_host_rx
rs232tx
clock_gen
rs232rx
response_check
rcv_string
Serial clk
endmodule // top_level
Notes:
Slide 164
Minilab rtl_uart.sv
Working directory: interface/rtl_uart
Purpose: Verify correct simulation of the previous example...
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Instructions:
Compile/simulate the example design:
vcs R +sysvcs rtl_uart.sv
Expected output
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Notes:
Slide 165
NOTE
modports make most sense for larger complex interfaces and synthesis
Notes:
Slide 166
Modports
In any interfaced design, some modules drive the interface (master), some read from it
(slave) and some may do both. To keep things straight, SystemVerilog provides modport
lists. These can describe ports AND/OR interface access methods.
interface i2;
wire a, b, c, d, e, f;
modport master (input a, b, output c, d, e);
modport slave (output a, b, input c, d, f);
endinterface
Interface i2 with
master and slave modports
modport keyword implies how the ports are accessed
from the point of view of the module
module top;
i2 i;
m u1(.i(i.master));
s u2(.i(i.slave));
endmodule
Notes:
Slide 167
2 modports of simple_bus
module top;
logic clk = 0;
simple_bus sb_intf(clk); // Instantiate the interface
initial repeat(10) #10 clk++;
memMod mem(.a(sb_intf)); // Connect the interface to the module instance
cpuMod cpu(.b(sb_intf));
endmodule
Intro to SystemVerilog 168
Notes:
Slide 168
2 modports of simple_bus
module top;
logic clk = 0;
simple_bus sb_intf(clk); // Instantiate the interface
initial repeat(10) #10 clk++;
Master/slave association
Notes:
Slide 169
clk
response_check
rs232_if
rcv_string
send_string
txmit
recv
rs232tx
rs232rx
clock_gen
Serial clk
Notes:
Slide 170
clk
response_check
rs232_if
rcv_string
send_string
txmit
recv
rs232tx
rs232rx
clock_gen
Serial clk
Expected output
Instructions:
Edit the file "rtl_uart.sv" and make the following changes.
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Notes:
Slide 171
Notes:
Slide 172
Method calls
endmodule
Intro to SystemVerilog 173
Notes:
Slide 173
Notes:
Slide 174
endinterface: simple_bus
Example:
System with one master and N slaves (all connected via a common modport).
Each slave exports a reset method
Master invokes reset and invokes all slave reset methods at the same time.
Notes:
Slide 175
task a.Write;
avail = 0;
...
avail = 1;
endtask
endmodule
module cpuMod(simple_bus b);
enum {read, write} instr;
logic [7:0] raddr;
module top;
logic clk = 0;
simple_bus sb_intf(clk);
memMod mem(a.(sb_intf.slave));
cpuMod cpu(b.(sb_intf.master));
endmodule
Notes:
Slide 176
In this section
What is ABV
Types of Assertions
Accellera
Analysis
Formal
Notes:
Slide 177
The Challenge
19
98
19
96
19
94
19
92
19
90
19
88
160
140
120
100
80
60
40
20
0
19
86
19
84
19
82
33%
31%
31%
24%
October 2000
23%
Collett International
21%
14%
11%
10%
0% 10% 20% 30% 40% 50% 60% 70% 80% 90%
74%
19
80
Functional
Noise
Clocking
Slow Path
Race Condition
Yield
Mixed Signal Intf
Power
IR Drops
Firmware
Year
Notes:
Slide 178
Peripheral
TB1
CPU
Peripheral
TB2
What if an internal error occurred, but the design still had a proper
output response?
Notes:
Slide 179
Assertion-Based Verification
$root
Notes:
Slide 180
Types of Assertions
System Bus
(e.g. AHB or PCI)
I/O Assertions
uP Core
FIFO
Arbiter
Structural Assertions
Protocol Assertions
Intro to SystemVerilog 181
Notes:
Slide 181
Types of Assertions
Structural Assertions
Intended internal functionality of blocks
Designers can catch errors more quickly
I/O Assertions
Input combinational relationships (e.g. read_en, write_en)
Basic sequential behavior (e.g. reset, handshake)
Ensures block is being used correctly in external context
Protocol Assertions
Higher-level than interface
Transaction descriptions
Required responses
Ensures conformance to standards
Notes:
Slide 182
Examples of Assertions
I/O Assertions
"Reset must be held low for three rising edges of the clock."
Structural Assertions
Protocol Assertions
"If a master sets the transfer type to BUSY during a burst cycle, then in the
next cycle, the slave must assert HREADY and set HRESP to 'OKAY' ."
Notes:
Slide 183
White-box Monitoring
Assertions increase observability of errors in the DUT
"Open" the black box and observe internal behavior
Monitor
`ifdef MONITOR_ON
always @(state) begin
if ((state & (state - 1)) != 2'b0) begin
$display("STATE_NOT_ONE_HOT,%t",$time);
end
end
`endif
Notes:
Slide 184
Notes:
Slide 185
Notes:
Slide 186
Notes:
Slide 187
34%
9%
8%
7%
6%
4%
11%
7%
6%
8%
25%
Register Miscompare
Simulation "No Progress
PC Miscompare
Memory State Miscompare
Manual Inspection
Self-Checking Test
Cache Coherency Check
SAVES Check
22%
15%
14%
8%
6%
5%
3%
2%
[Krolnik 98]
Notes:
Slide 188
In this section
SVA Checker Library
Immediate / Concurrent
Boolean
Sequences
Repetition etc.
Property block
Sequence Implication
Assert/Cover blocks
VCS/Virsim and assertions
Notes:
Slide 189
assert_odd_parity
assert_one_cold
assert_one_hot
assert_proposition
assert_quiescent_state
assert_range
assert_time
assert_transition
assert_unchange
assert_width
assert_win_change
assert_win_unchange
assert_window
assert_zero_one_hot
Notes:
Slide 190
\
\
\
Notes:
Slide 191
$VCS_HOME/packages/sva/assert_mutex.v
/*
assert_mutex
Ensures that <a> and <b> never evaluate true at the same time. The check
is not enabled unless <reset_n> evaluates true (1). The checks is
performed on the active <clk> edge specification.
module test_design();
.
.
Failure modes:
The assertion assert_mutex will report failure when <a> and <b> are
both sampled 1 at the positive edge of <clk>.
design DUT (dat, addr, rd, wr, enable_1, enable_2, clk, rst_);
.
.
verifies that gnt[0] and gnt[1] are never 1 at the same time as
sampled by posedge of clk. The checker is always enabled because
<reset_n> is constant 1.
*/
Example:
`ifdef SVA_STD_INTERFACE
interface assert_mutex(clk, reset_n, a, b);
`else
module assert_mutex( clk, reset_n, a, b);
`endif
parameter
severity_level
= 0;
parameter
edge_expr
= 0;
parameter
msg
= "VIOLATION";
.
.
`ifdef SVA_STD_INTERFACE
endinterface
`else
endmodule
`endif
Notes:
Slide 192
Instructions:
Edit the design (file: fsm_ex.sv)
Use the "assert_one_hot" checker from the SVA Checker library to test for
one-hot behavior of the state vector state.
Verify your assertion in simulation by changing the states enumeration.
Notice the run.csh script which should make invoking vcs easier.
Notes:
Slide 193
Immediate
Simulation use primarily
Execute under simulator control inside a procedural block
Concurrent
Partial support
Usable by other tools as well ( e.g. formal verification )
Clocked/sampled paradigm
Distinguishable by the keyword property within assert or
cover verification statements
Conc. assertions may be
triggered in various ways
(including procedural code),
but time is spec'd internally
and may include sequential
checks over time
Notes:
Slide 194
Immediate Assertions
time t;
NOTE
assert statements resolve X and Z expression values
much like if-else statements they will fail on 0, X or Z
Notes:
Slide 195
Several new system tasks provide control over severity of a failing assertion.
These new tasks all follow $display symantics.
$fatal()
$error()
$warning()
$info()
$display()
Notes:
Slide 196
Concurrent Assertions
Partial support
Verification Statements
Property Declarations
Sequence Regular
Expressions
Boolean Expressions
Notes:
Slide 197
Boolean expressions
Basic building blocks of assertions.
Evaluate sampled values of variables used
0, X or Z interpret as false
Excludes certain types:
time, shortreal, real, realtime
string, event, chandle, class
Associative/dynamic arrays
Variables used must be static
Excludes these operators:
C-assignments (+=, -=, >>= etc)
Bump operators ( i++, i--, ++i etc)
Notes:
Slide 198
$onehot (<expression>)
Notes:
Slide 199
clk
clock ticks
ticks
simulation ticks
Notes:
Slide 200
req
ack
e1
e2
e3
e4
clk
Sequence
start
Events:
Remember, this diagram shows what the signals look like from
the point of view of the sampling clock which must be at least as
fast as the system clock
Assuming we start
with req and ack hi
SVA events are:
e1
e2
e3
e4
( !req )
( !ack )
( req )
( ack )
Notes:
Slide 201
Sequence
( !req )
( !ack )
( req )
( ack )
e1
e2
e3
e4
req
ack
clk
Sequence
start
Sequence
matches
Sequence
mismatch
Sequence
end
Notes:
Slide 202
Sequence Operators
Available sequence operators (in order of precedence):
[*
[*->
[*=
and
intersect
or
throughout
within
##
Notes:
Slide 203
Range:
a ##[3:5] b
a ##[3:$] b
Notes:
Slide 204
Sequence block
Sequence blocks identify and encapsulate a sequence definition
sequence s1;
@ (posedge clk)
a ##1 b ##1 c;
endsequence
sequence s2 (data,en);
// sequence with name AND arguments
(!frame && (data==data_bus)) ##1 (c_be[0:3] == en);
endsequence
Notice no clock is defined. This may be inherited from
a higher hierarchical statement like property or assert
(More on this later)
sequence s3;
start_sig ##1 s2 ##1 end_sig;
endsequence
// sequence as sub-expression
Where: s3 - is same as - start_sig ##1 (!frame && (data==data_bus)) ##1 (c_be[0:3] == en) ##1 end_sig
Notes:
Slide 205
Notes:
Slide 206
Non-consecutive repetition:
a ##1 b [*=min:max] ##1 c
- same as - a ##1 ((!b [*0:$] ##1 b)) [*min:max])
##1 !b [*0:$] ##1 c;
Notes:
Slide 207
Preponed
Pre-active
Current events
(processed in any order)
Events to be evaluated
after active events (e.g. # )
SystemVerilog
Event Scheduler
Active
Inactive
Pre-NBA
Non-blocking assignment
updates occur here
NBA
Post-NBA
Observed
Reactive
Post-observed
Postponed
Verilog 95
PLI
SystemVerilog
Verilog 2001+
Notes:
Slide 208
$fell (<expression> )
$stable ( <expression> )
- true if no change
Notes:
Slide 209
s1
s2 s2
o_s
sequence s2;
d ##[1:3] e ##1 f;
endsequence
a_s
i_s
s1 or s2
endsequence
sequence a_s;
s1 and s2;
endsequence
endsequence
// i_s matches only if e occurs 1 cycle after d
sequence i_s;
Notes:
Slide 210
Signals
module u_xmit
sys_clk
uart_clk
sys_rst_l
U1
done
uart_out
xmit
data
Checker routines
sys_clk
System clock
uart_clk
sys_rst_l
xmit
data
done
uart_out
16 )
Notes:
Slide 211
Reset
waveform
Timing diagram
uart_clk = sys_clk/16
sys_clk
uart_clk
sys_rst_l
1 sys_clk
xmit
1 sys_clk
data
XX
done
uart_out
byte
XX
b0
Notes:
Slide 212
Byte transmit
waveform
Signals
sys_clk
System clock
uart_clk
sys_rst_l
xmit
data
done
uart_out
16 )
Timing diagram
sys_clk
uart_clk
xmit pulse lasts 16 sys_clk
xmit
data
XX
byte
XX
done stays low
175 sys_clks
or 11 uart_clks
done
1 sys_clk
uart_out
Start
bit 0
b0
b1
b2
b3
b4
b5
b6
b7
Stop
bit 1
Notes:
Slide 213
Instructions:
XXXXXXXXXXXXX
XXXXXXXXXXXXX
XXXXXXXXXXXXX
1.
2.
3.
4.
Assume all 3 sequences use sys_clk for reference. Don't worry with how this is
accomplished or how the sequences are attempted, we will cover that in the next lab.
Intro to SystemVerilog 214
Notes:
Slide 214
sequence t1;
te1 ##[2:5]te2;
endsequence
sequence ts1;
first_match(te1 ##[2:5]te2);
endsequence
Each attempt of sequence t1 can result in matches for up to four cycles:
te1 ##2 te2
te1 ##3 te2
te1 ##4 te2
te1 ##5 te2
t1 s2
t1
ts1
But, sequence ts1 will match for ONLY the first of the four t1's.
Notes:
Slide 215
sequence burst_rule;
@(posedge clk)
$fell (burst) ##0
(!burst) throughout (##2 (!trdy [*4]);
endsequence
burst
trdy
burst1
Here, when burst goes true (low), it is expected to stay low for the next 2 ticks
and also for the following 4 clock ticks, during which trdy is also to stay low.
Notes:
Slide 216
Notes:
Slide 217
s1 ##1 s2.ended
sequence e1;
@(posedge clk) $rose(ready) ##1 proc1 ##1 proc2;
endsequence
sequence rule;
@(posedge clk) reset ##1 inst ##1 e1.ended ##1 branch_back;
endsequence
Here, sequence e1 must end one tick after inst.
Notes:
Slide 218
Property block
Property blocks describe behavior in a design, giving it a name for reference
and allowing a range of tools to test/check/cover/etc that behavior.
Properties are often built from sequences (though NOT vice-versa)
Properties can appear in modules, interfaces, programs, clocking domains
even in $root.
property p1(a,b,c,d);
@ (posedge clk) disable iff (reset)
(a) |-> not ( b ##[2:3] c ##1 d );
endproperty
implication
Notes:
Slide 219
// non-overlapping form
Notes:
Slide 220
property p_post_rst;
@(posedge sys_clk) (!sys_rst_l) |-> s_rst_pair;
endproperty
BUT thanks to the implication operator
sys_rst_l (active, low) is a prerequisite for testing the
sequences
This avoids countless "FAILS" earlier/later in simulation
Notes:
Slide 221
Multi-clock support
Most systems have more than a single clock and SV assertions allow
for this by supporting the use of multiple clocks, even within a single
property/assert. A new syntax ( ## ) is introduced:
sequence m_clk_ex;
@(posedge clk0) a ## @(posedge clk1) b
endsequence
NOTE: no N
Notes:
Slide 222
Multi-clock support 2
A particularly interesting case is detecting the endpoint of a sequence
running on a different clock. For this purpose, use the matched method
which is like the ended method but for multiple clocks.
NOTE: no N
sequence e1;
@(posedge clk) $rose(ready) ##1 proc1 ##1 proc2;
endsequence
sequence rule;
@(posedge clk2) reset ##1 inst ##1 e1.matched [*->1] ##1 branch_back;
endsequence
Here, sequence e1(evaluated on clk) must end sometime after inst (evaluated on
clk2).
NOTE: sequence rule verifies that sequence e1 has ended, it does NOT start e1
evaluating.
Notes:
Slide 223
Sequence verification is very useful, but data must be functionally verified too.
SV allows local variables to be defined/assigned in a sequence or property.
All SV types are supported and are dynamic across different attempts on the
sequence.
logic [7:0] d_1, d_2, d_3;
property e1;
logic[7:0] x;
@(posedge clk) ( valid, x = d_in )
|-> ##4 d_out = ~x;
endproperty
Notes:
Slide 224
Assert block
A property by itself does nothing. It must appear within a verification
statement to be evaluated.
Two types of verification statement
[always] assert property - enforces a property as "checker"
[always] cover property - tracks metrics (# attempts, # match, # fail etc)
Properties can appear in modules, interfaces, programs, clocking domains
even in $root.
property p1(a,b,c);
disable iff (a) not @clk ( b ##1 c );
endproperty
assert_p1: assert property (p1(rst,in1,in2))
$info("%m OK")
Notes:
Slide 225
Notes:
Slide 226
property p1;
@( posedge clk ) ( reset && mode && !arb ) |=> s1
endproperty
Intro to SystemVerilog 227
Notes:
Slide 227
Clock inference
Assertions embedded in procedural code may infer a clock.
property p1;
a ##1 b ##1 c;
endproperty
Inferred clock
NOTE
Assertions embedded in initial blocks
execute just once, at time t0
If the embedded property specifies a clock, it must match the inferred clock
Variables monitored by a property must not be used within the inferring block
Notes:
Slide 228
Clock specification
The clock a property works from may be specified in several ways
1.
2.
3.
4.
default clocking
master_clk @(posedge clk5);
Notes:
Slide 229
Bind directive
As we saw, embedded assertions have advantages/disadvantages.
Another approach is to keep verification code separate from the design
and use the bind directive to associate them.
bind can connect a module, interface or program instance (with checkers?)
to a module or module instance.
bind may appear in a module or in $root.
bind
<module>
<module_instance>
cpu1
cpu2
cpu_chk
<module_instantiation>
<program_instantiation>
<interface_instantiation>
<instance_name>
Notes:
Slide 230
Assertion Guidelines
Like any new methodology, ABV users can benefit from guidelines:
1.
2.
3.
Easy to write
4.
Follow up by writing assertions that only use two signals, plus a clock
(req and gnt, or mut-ex signals).
Continue this way before getting to the complex assertions.
Complex systems are often described using a flow chart.
In this case, write one assertion for each arrow in the flow chart.
(simpler assertions, easy estimation how many).
Consider the Checker Library (SVA Checker Lib) of functions
provided with VCS. These can help with common checker situations
like mutex, one-hot, handshake, fifo, memory etc.
5.
6.
7.
Notes:
Slide 231
success
maxfail=N
quiet
report[=<path/filename>]
- report file (default is: ./assert.report)
verbose
Notes:
Slide 232
Notes:
Slide 233
VirSim displays assertions like signals, but indicates their start/end times, not value.
It also indicates their status by color:
green - success
red - failure
grey - incomplete (Notice the X for finish time above)
Expand the assertion by double-clicking: revealing the clock ticks, result and end-time per attempt.
Notes:
Slide 234
Instructions:
Edit the design (file: test_u_xmit.sv)
Code up the following assertions:
1.
2.
3.
4.
5.
Notes:
Slide 235
236
Intro to SystemVerilog 1
Notes:
Slide 236
In this section
More on interfaces
More on $root
Dynamic / associative arrays
Dynamic processes
Process control
Classes
Randomization and Constraints
Clocking Domains
Notes:
Slide 237
More on interfaces
Notes:
Slide 238
Implicit ports
If an interface is given the same name in all the modules that use it
(instead of a and b as on previous example) then implicit ports can be used
to make instantiation much easier.
module memMod (simple_bus sb_intf, input bit clk);
...
endmodule
Notes:
Slide 239
Generic bundle
Use the generic interface keyword in module declaration and choose (for example)
which level of abstraction is desired for that interface at instantiation
// memMod and cpuMod can use any interface
module memMod (interface a, input bit clk);
...
endmodule
module top;
logic clk = 0;
simple_bus sb_intf; // Instantiate the interface
memMod mem (.a(sb_intf), .clk(clk));
cpuMod cpu (.b(sb_intf), .clk(clk));
endmodule
NOTE
implicit ports cannot be used
with generic interfaces
(use named ports)
Notes:
Slide 240
Hierarchical interfaces
Interfaces can be declared/used hierarchically.
interface i1;
interface i3;
wire a, b, c, d;
modport master (input a, b, output c, d);
modport slave (output a, b, input c, d);
endinterface
i3 ch1, ch2;
modport master2 (ch1.master, ch2.master);
endinterface
modport of i1
Notes:
Slide 241
module top;
logic clk = 0;
simple_bus sb_intf(clk);
// Instantiate the interface
memMod mem(sb_intf.slave); // Connect the modport to the module instance
cpuMod cpu(sb_intf.master);
endmodule
Notes:
Slide 242
Notes:
Slide 243
Notes:
Slide 244
Notes:
Slide 245
logic [7:0] a = 0;
event global_event;
Procedural code, implied initial block
$root in SV3.1
begin
$monitor("%2t: a =%d, U1.a =%d",$time,a,U1.a);
#20 -> global_event;
end
local1 U1;
module local1;
logic [7:0] a;
always @(global_event) begin
$display(" global_event detected in: %m");
a = 1;
end
local2 U2;
endmodule
module local2;
always @($root.global_event) begin
$display(" global_event detected in: %m");
#20;
a = 2;
// assign $root.a
#20;
U1.a = 2;
// assign U1.a
#20
$root.a = 4;
// assign $root.a
end
Alternative names for same global signal
endmodule
Intro to SystemVerilog 246
0: a = 0, U1.a = x
global_event detected in: $root.U1.U2
global_event detected in: $root.U1
20: a = 0, U1.a = 1
40: a = 2, U1.a = 1
60: a = 2, U1.a = 2
80: a = 4, U1.a = 2
Notes:
Slide 246
module test;
logic [7:0] a = 0, b = 0;
event global_event;
initial
begin
process $monitor(%2t: test.a =%d, test.b =%d, local1.a =%d",$stime,a,b,U1.a);
#20 -> global_event;
end
Simulator output...
local1 U1;
0: test.a =
module local1;
logic [7:0] a;
always @(global_event)
begin
$display(global_event detected in: %m");
a = 1;
b = 1;
end
0, test.b =
0, local1.a =
40: test.a =
0, test.b =
2, local1.a =
60: test.a =
4, test.b =
2, local1.a =
t20
local2 U2;
NOTES
module local2;
always @(global_event)
begin
$display(global_event detected in: %m");
#20 a = 2;
b = 2;
#20 test.a = 4; // Verilog hier. ref.
end
endmodule
endmodule
endmodule
Notes:
Slide 247
Arrays dynamic
This is another exciting feature of SystemVerilog 3.1, allowing declaration of a
one-dimensional array with no specific size. The size can change during
simulation and array space is allocated by method call.
Syntax:
data_type array_name [ ];
Example:
bit [3:0] nibble[];
integer mem[];
3 new methods support the creation, destruction and querying of dynamic arrays
new[ ]
size()
Notes:
Slide 248
Arrays associative
Associative arrays ( sometimes called indexed arrays ) go further than dynamic
arrays, they support situations where data set size is totally unpredictable and
elements may be added or removed individually to grow/shrink the array.
Associative arrays are implemented as a look up table and so require an index.
Syntax:
data_type array_id [ index_type ]; // index type is the datatype to use as index
// examples include string, int, class, struct
Example:
bit i_array[*];
Notes:
Slide 249
Processes
Verilog had simple process spawning capability via the fork-join statement.
For modern more sophisticated design and verification however, this isnt
enough.
SystemVerilog provides a much greater flexibility to spawn and control
Dynamic processes:
Spawning Dynamic processes: fork..join_any, fork..join_none
Process control wait_fork, disable_fork
Notes:
Slide 250
Dynamic processes
Inspired by Vera and other languages, SystemVerilog 3.1 defines 2 new
special cases of forkjoin with associated keywords join_any & join_none
join_any
join
fork
join
fork
join_none
fork
Notes:
Slide 251
forkjoin_any
Here, the parent process blocks until any one of the spawned processes
completes
fork
begin
#100
end
begin
wait (status == 0)
end
begin
@(sig)
end
join_any
Notes:
Slide 252
forkjoin_none
The SystemVerilog 3.0 spec. defined a process statement for spawning off
parallel processes. SystemVerilog 3.1 replaces process by join_none. This
allows any number of processes to be spawned simultaneously without any
impact on the flow of the main process.
fork
begin
#100
end
begin
wait (status == 0)
end
begin
@(sig)
end
join_none
@(sigb); // executes immediately
NOTE
The child processes spawned
by a forkjoin_none do not
start executing until the parent
process hits a blocking
statement
Notes:
Slide 253
// continue regardless
// block until tasks 1-4 complete
Notes:
Slide 254
Notes:
Slide 255
Classes
Object Oriented programming is a common programming paradigm based
on the idea that data and the means to manipulate it can be described
together in a formal structure called a class.
A class is a datatype, similar to a struct but in addition to data elements
(called properties) a class also contains functions and tasks (called methods)
through which class properties may be manipulated. An instance of a class
is referred to as an object.
SystemVerilog classes can be dynamically created and destroyed but unlike
their C++ cousins memory allocation and deallocation (garbage collection) is
handled automatically. Since pointers are a key ingredient in the flexibility
of classes, SystemVerilog implements them too, but in a safer form, called
handles.
Notes:
Slide 256
Class example
class Packet ;
//data or class properties
bit [3:0] command;
bit [40:0] address;
bit [4:0] master_id;
integer time_requested;
integer time_issued;
integer status;
// initialization
function new();
command = IDLE;
address = 41b0;
master_id = 5bx;
endfunction
// methods
// public access entry points
task clean();
command = 0; address = 0; master_id = 5bx;
endtask
task issue_request( int delay );
// send request to bus
endtask
function integer current_status();
current_status = status;
endfunction
endclass
Notes:
Slide 257
Directed Tests
Traditional method for testbenches
Weighted Randomization
Focuses stimulus on interesting cases
Constrained Randomization
Enables complex and thorough tests to be developed quickly
Combination of above
Notes:
Slide 258
$urandom_ range
$srandom
randc
Built-in methods
randomize()
pre_randomize
post_randomize
Notes:
Slide 259
Constraint Expressions
inside
dist
if..else
Built-in methods
randomize()with
rand_mode()
constraint_mode
enable/disable a constraint
Notes:
Slide 260
class Bus;
rand bit[15:0] addr;
rand bit[31:0] data;
constraint word_align {addr[1:0] == 2b0;}
endclass
Notes:
Slide 261
Preponed
Pre-active
Current events
(processed in any order)
Events to be evaluated
after active events (e.g. # )
SystemVerilog
Event Scheduler
Active
NOTE
SystemVerilog defines
a special timeunit 1step
defined as the smallest possible
timeunit (like delta time in VHDL)
Inactive
Pre-NBA
Non-blocking assignment
updates occur here
NBA
Post-NBA
Observed
Reactive
Post-observed
Postponed
Verilog 95
PLI
SystemVerilog
Verilog 2001+
Notes:
Slide 262
Program Block
In Verilog a testbench looks just like the DUT, yet requirements are different.
For example, testbenches require a stable time/place to drive/monitor/sample
in order to avoid race conditions.
SystemVerilog defines a programendprogram block.
PB Code executes in reactive region
Outputs transition together
Ideal location for code that reacts to assertion pass/fail
Notes:
Slide 263
NOTE
SystemVerilog simulation stops (i.e.
simulator will exit) when all initial
blocks inside program blocks have
finished. This occurs even if other
code is still executing.
end
endprogram
Notes:
Slide 264
Clocking Domains
In Verilog testbenches, race conditions on the ports of the DUT are a constant worry.
The classic workaround is to make testbenches operate on the opposite edge of clk
to the DUT. This isnt always practical however
SystemVerilog introduces a new block: clockingendclocking which identifies
clock signals and specifies explicit timing characteristics for all signals synchronous
to that clock.
By specifying skew values for driving and sampling, testbench code can simply
reference a clock edge and the simulator (observing skew specs) will sample
prior to and drive just after the active edge, avoiding race conditions with
the DUT.
output skew
input skew
Notes:
Slide 265
Notes:
Slide 266
Notes:
Slide 267
12
11
10
9
8
7
6
5
4
3
2
1
Notes:
Slide 268
`define INTEL
//`define SPARC
module video1;
typedef struct packed {bit[7:0] R, X, B, G;} RGB;
RGB vidbuf[1:150][1:400] ; // Unpacked array of RGB structs
bit[7:0] hdr [1:56];
int rfile, wfile, ifs, i, scale;
function void invert();
// Invert the image (pos-neg-pos etc)
for(int ver=1; ver <= 150; ver++)
for(int hor=1; hor <= 400; hor++) begin
vidbuf[ver][hor].X = 'hf;
vidbuf[ver][hor].R = 255 - vidbuf[ver][hor].R; // invert
vidbuf[ver][hor].G = 255 - vidbuf[ver][hor].G; // invert
vidbuf[ver][hor].B = 255 - vidbuf[ver][hor].B; // invert
end
endfunction
initial begin
rfile = $fopen("i_mourne_32.bmp", "r");// Open the image file
wfile = $fopen("new_pic.bmp", "w"); // Open output img file
i = $fread(hdr, rfile, 0, 56);
// Read 56-byte header
i = $fread(vidbuf, rfile);
// Read the file into memory
ifs = $ftell(rfile);
// capture filesize in "ifs"
$display("Loaded %0d pixels \n", ifs);
invert;
saveimg;
$fclose(rfile);
$fclose(wfile);
$finish;
end
endmodule
Intro to SystemVerilog 269
Notes:
Slide 269
Notes:
Slide 270
endmodule
Notes:
Slide 271
endmodule
module response_check( rs232_beh f);
rs232_beh IB();
// Behavioral RS232 interface
stimgen ST1(IB);
// Behavioral transmitting host
response_check RC1(IB); // Behavioral receiving host
initial
begin
@(posedge f.reset);
@(negedge f.reset);
f.rcv_string("Mr Watson, come here...");
f.rcv_string("I want to see you. ");
$stop;
interface rs232_beh;
end
bit [0:31][7:0] string;
endmodule
logic valid = 0;
bit reset;
initial
begin
repeat(20) @(negedge clk);
reset = 1;
repeat(50) @(negedge clk);
reset = 0;
end
endmodule // top_level
Notes:
Slide 272
#2
1:
always @ (b)
a = b;
2:
always @ (b)
#2 a = b;
3:
always @ (b)
a = #2 b;
4:
always @ (b)
a <= b;
5:
always @ (b)
#2 a <= b;
6:
always @ (b)
a <= #2 b;
10
20
40 41
b
ROT #1
ROT #2
12
22
42 43
Notes:
Slide 273
always_comb
begin
unique case (state)
S0:
begin
if(input_sig_1 == `TRUE)
next_state = S1;
else
next_state = S0;
end
S1:
begin
if(input_sig_2 == `TRUE)
next_state = S2;
else
next_state = S0;
end
S2:
next_state = S0;
endcase
end
NOTE
To compile this example:
endmodule
Notes:
Slide 274
Notes:
Slide 275
initial
begin
rfile = $fopen("i_mourne_32.bmp", "r");// Open the image file
wfile = $fopen("new_pic.bmp", "w"); // Open output img file
i = $fread(hdr, rfile, 0, 56);
// Read 56-byte header
i = $fread(vidbuf, rfile);
// Read the file into
memory
ifs = $ftell(rfile);
// capture filesize in "ifs"
$display("Loaded %0d pixels \n", ifs);
invert;
scale = buildhist(); // Build histogram and return scale factor
//
printhist(scale);
painthist(scale);
saveimg;
$fclose(rfile);
$fclose(wfile);
$finish;
end
endmodule
Notes:
Slide 276
Notes:
Slide 277
initial
begin
@(posedge f.reset);
@(negedge f.reset);
f.send_string("Mr Watson, come here..");
f.send_string("I want to see you. ");
end
bit clk,
reset;
wire sub_clk;
wire serial_link;
reg[4:0] freq;
rs232_if I2(.clk(clk), .reset(reset), .tx_clk(sub_clk),
.rx_clk(sub_clk)); // RTL UART interface
endmodule
rs232tx T1(.serial_out(serial_link), .tif(I2.txmit)); // RTL rs232 transmit
rs232rx R1(.serial_in(serial_link), .rif(I2.recv)); // RTL rs232 receive
stimgen ST1(I2); // RTL transmitting host (stimulus generator)
response_check RC1(I2); // RTL receiving host (response checker)
clock_gen CK(.clk(clk), .frequency(freq), .reset(reset), .clk_out(sub_clk));
initial
begin
clk = 0;
reset = 0;
freq = 4'd12;
forever #10 clk = !clk;
end
initial
begin
repeat(20) @(negedge clk);
reset = 1;
repeat(50) @(negedge clk);
reset = 0;
end
endmodule // top_level
Notes:
Slide 278
`ifdef SVA
assert_one_hot #(.width(2), .msg("state variable should be one_hot"))
A1 (.clk(clk), .reset_n(!rst), .test_expr(state));
`endif
endmodule
0 0 clk: 0 ,rst: 0 ,in1: 0 ,in2: 0 ,outa: 0 ,outb: 0
"/work/synopsys/vcs/packages/sva/assert_one_hot.v", 87: test_fsm_ex.u1.A1.assert_one_hot:
started at 100s failed at 100s, "state variable should be one_hot" Offending '$countones(test_expr)==1'
100 0 clk: 1 ,rst: 0 ,in1: 0 ,in2: 0 ,outa: 0 ,outb: 0
200 0 clk: 0 ,rst: 0 ,in1: 0 ,in2: 0 ,outa: 0 ,outb: 0
"/work/synopsys/vcs/packages/sva/assert_one_hot.v", 87: test_fsm_ex.u1.A1.assert_one_hot:
started at 300s failed at 300s, "state variable should be one_hot" Offending '$countones(test_expr)==1'
Notes:
Slide 279
Notes:
Slide 280
`ifdef SVA
test_u_xmit.sv
Sample Solution
Assertion Lab 3:
property p_uart_sys16;
@(posedge sys_clk) $rose(uart_clk) |-> ##8 $fell(uart_clk) ##8 $rose(uart_clk);
endproperty
// xmit and data checks
sequence s_val_bit_stream(x_byte);
bit[7:0] x_byte;
##8 (uart_out == 0) #16
(uart_out == x_byte[0]) ##16
(uart_out == x_byte[1]) ##16
(uart_out == x_byte[2]) ##16
(uart_out == x_byte[3]) ##16
(uart_out == x_byte[4]) ##16
(uart_out == x_byte[5]) ##16
(uart_out == x_byte[6]) ##16
(uart_out == x_byte[7]) ##16
(uart_out == 1) ##16 (uart_out == 1) #16
(done == 1);
endsequence
property p_val_bit_stream;
@(posedge sys_clk) ($fall(done) && xmit ) |-> s_val_bit_steam(data);
endproperty
Notes:
Slide 281
Sample Solution
Assertion Lab 3:
property p_xmit_done;
@(posedge sys_clk) $rose(xmit) |-> ##1 $fell(done) && $fell(uart_out);
endproperty
// Serial protocol checkers
property p_xmit_nc_data;
@(posedge sys_clk) $rose(xmit) |=> $stable(data) [*1:$] ##1 $fell(xmit);
endproperty
property p_done_175;
@(posedge sys_clk) ($fell(done) && sys_rst_l) |-> ##175 $rose(done);
endproperty
// assertions
assert_xmit_hi16: assert property (p_xmit_hi16) //$display("%m :OK!");
else $display("%m : Signal xmit should stay hi for 16 sys_clks");
assert_xmit_done: assert property (p_xmit_done) //$display("%m :OK!");
else $display("%m : Posedge xmit should take done and uart_out low.");
assert_xmit_nc_data: assert property (p_xmit_nc_data) //$display("%m :OK!");
else $display("%m : data should not change while xmit asserted");
assert_done_175: assert property (p_done_175) //$display("%m :OK!");
else $display("%m : Byte transmission (done low) should take 175 sys_clk");
Intro to SystemVerilog 282
Notes:
Slide 282
Sample solution:
Assertion Lab3
// uart_clk checkers
//####################
//
//
sequence s_val_bit_stream_uart_clk(x_byte);
bit[7:0] x_byte;
##1 (uart_out == 0) #1
assert_xmit_hi1: assert property (p_xmit_hi1)
(uart_out == x_byte[0]) ##1
else $display("%m : Signal xmit should stay hi for 1 uart_clk");
(uart_out == x_byte[1]) ##1
(uart_out == x_byte[2]) ##1
assert_done_11: assert property (p_done_11)
(uart_out == x_byte[3]) ##1
else $display("%m : Byte transmission (done low) should take 11 uart_clk"
(uart_out == x_byte[4]) ##1
assert_val_bit_stream_uart_clk: assert property (p_val_bit_stream_uart_clk)
(uart_out == x_byte[5]) ##1
else $display("%m : uart_out bitstream incorrect");
(uart_out == x_byte[6]) ##1
(uart_out == x_byte[7]) ##1
(uart_out == 1) ##1 (uart_out == 1) #1
(done == 1);
endsequence
`endif
property p_xmit_hi1;
@(posedge uart_clk) $rose(xmit) |-> ##1 $fell(xmit);
endproperty
property p_done_11;
@(posedge uart_clk) ($fell(done) && sys_rst_l) |-> ##11 $rose(done);
endproperty
property p_val_bit_stream_uart_clk;
@(posedge sys_clk) ($fall(done) && xmit ) |-> s_val_bit_steam_uart_clk(data);
endproperty
Notes:
Slide 283
284
Intro to SystemVerilog 1
Notes:
Slide 284
Appendix A
Notes:
Slide 285
VCS
VCS stands for Verilog Compiled Simulator
There are two different types of Verilog event based simulators:
Interpreted - example is Verilog-XL
Compiled - VCS
Depending upon platform, VCS first generates C code from the Verilog
source, then it compiles and links the object files to the simulation
engine to create an executable.
Win, Alpha, SGI, IBM
platforms only
Verilog
Source
(mem.v
cpu.v)
C language
files
(mem.c
cpu.c)
Object
files
(mem.o
cpu.o)
Link
simv
(executable)
Notes:
Slide 286
Notes:
Slide 287
Verilog
Source
(mem.v)
C language
files
(mem.c)
Object
files
(mem.o
cpu.o)
Link
simv
(executable)
Notes:
Slide 288
VCS -Mupdate
Creates a makefile that is built and maintained by vcs:
Example
vcs file1.v file2.v file3.v -Mupdate:
Compiles Verilog source files, puts c files in directory called csrc
Makefile created in csrc directory
C compilation accomplished via makefile
Object files linked to produce simv
Subsequent compilations will be incremental:
Appropriate c files updated
Makefile adjusted
Incremental C compilation as appropriate
Object files re-linked
Handy
Handytip:
tip: The
TheMupdate
Mupdateswitch
switchcan
canbe
beshortened
shortenedtotoM
Mbut
butthis
thiswill
willmake
makeuse
useofof
an
existing
makefile
whereas
Mupdate
generates
a
brand
new
makefile
an existing makefile whereas Mupdate generates a brand new makefile
Notes:
Slide 289
module simple;
reg clk, a;
wire b;
initial
// initialize registers and generate the clk
begin
a = 0;
clk = 0;
forever #25 clk = !clk;
end
always @ (posedge clk)
a = !a;
inv_things inv1 (a,b);
Parent
Module
always @ (b)
$display ("a = %b and b = %b",a,b);
initial
#1000 $stop;
simple.v
endmodule
module inv_things (a,b);
input a;
output b;
reg b;
always @ (a)
b<= #5!a;
Child
Module
// invert a, delay 5 and assign to b
endmodule
Quiz: What coding style problems can you see with this code?
Intro to SystemVerilog 290
Notes:
Slide 290
Simulator binary
Design file
Run & use the VirSim GUI
Allow line commands
Stop at time zero
Notes:
Slide 291
VirSim GUI
Other Window
launch buttons
VirSim Interactive
Window (IW)
User defined
Buttons
VCS Control
Notes:
Slide 292
VirSim: Waveforms
#1
#2
Answer: They show that no waveform data has been logged yet (Simulation hasnt started).
Question:
What do these gray bars in WW mean?
Notes:
Slide 293
Window Linking:
Some VirSim windows (Waveform Window, Source Window, Logic Browser,
and Register Window) may be linked in order to synchronize operations,such
as breakpoint searches, value changes, and change times.
For example, changing the time in one linked window automatically changes
the view in the other linked windows to that time. Linked windows display a
common link letter (A ,B etc.) in the upper-right corner of the window (next to
the chain icon). SIM is the main Simulator group.
Notes:
Slide 294
#4
#5
Notes:
Slide 295
#8
Answer: Its in several places, like the bottom pane of IW and its where waves end and gray bars begin in WW.
Question:
How can you tell the
current simulation time?
Time
Notes:
Slide 296
#9
#10
3 Cursors:
The main 2 cursors (C1 & C2) are user-controlled by a mouse
click close to a signal edge in WW:
LMB for C1, MMB for C2.
Current location (in time) for any 2 cursors is shown in the
pane at top-left (C1 & C2 show here).
The third cursor Icur shows current simulation time
when WW is linked with the SIM group (not shown here).
Delta indicates the time delta between the cursors
(handy for measuring pulse widths etc.).
These 2 gadgets allow a choice of which cursors to display.
Notes:
Slide 297
Notes:
Slide 298
#12
#13
#14
Notes:
Slide 299
#15
#16
16.
#17
Notes:
Slide 300
#19
Question:
What does an execution count
of zero tell us?
Answer: Well, perhaps there is some line of code that CANNOT be executed,
but more likely, they were missed by our test vectors. GOOD TO KNOW!
Notes:
Slide 301
#19
#20
#22
#23
Notes:
Slide 302
#25
#24
Just edit your code and save the changes.
Then, in the IW click the Sim pulldown &
choose Rebuild & Re-exec
25. Notice that the simulator exits but the GUI
remains open. Once the simulator has
recompiled your sourcecode, it reconnects
to the GUI. Next, click the green run arrow
in IW to rerun the simulation and update all
active GUI windows (SW, WW etc).
Notes:
Slide 303
Intro to SystemVerilog 1
Slide 304
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