International Conference on Communication and Signal Processing, April 3-5, 2014, India

Remote Reconfigurable Wireless Sensor Node

Design for Wireless Sensor Network
Natheswaran S, Athisha G

Abstract-Wireless

sensor

nodes

are

used

in

variety

of

applications and their requirements are not fully known to the

designer during the design and development stage. Similarly
wireless

sensor

components

node

which

consists

increases

of

the

number
power

of

off-the-shelve

consumption

of

the

wireless sensor node. So in this paper a wireless sensor node with

a soft core

processor

facilities is proposed.
over-the-air

remote

and

remote

hardware

reconfiguration

The proposed architecture will provide

modification

facilities

even

after

the

deployment of the wireless sensor node. FPGA is used in the

wireless sensor node design in order to increase the processing
capabilities of the system to meet the target applications. The
challenges and the design concept of the proposed wireless sensor
node are presented in this paper.

Index Terms- FPGA technology, multi cycle architecture,

Reconfiguration, Sensor network, Soft core processor.

I. INTRODUCTION
wireless sensor node is a device in Wireless Sensor

ANetwork, which consists of inbuilt sensors for monitoring

various environmental as well as physical conditions.
These devices are capable of sensing information, processing
the sensed information and sending the processed data to
neighbor nodes or some remote station(s).
Wireless sensor node consists of five important subsystems
as shown in the Fig.l. Sensing subsystem consists of sensors,

Communication
Subsystem

which are usually tiny devices which are capable producing

some measurable response (often a change in voltage). These
responses are usually fed to an Analog to Digital Converter
(ADC). The digitized signal is then sent to the processing unit
for further processing.
Processing subsystem is the heart of the wireless sensor
node. It is also known as the controlling unit. FPGA's are
preferred as the control unit in the wireless sensor node due to
it's unique features of reprogramming and reconfiguration.
Microcontrollers (f..lC), Microprocessor (f..lP), Digital Signal
Processor (DSP), Application Specific Integrated circuit
(ASIC) are also used as a processing unit in wireless sensor
node design.
Communication subsystem consists of a wireless antenna. It
makes use of RF (Radio Frequency), Optical Communication
or Infrared waves as the transmission media. The wireless
radio unit operates in the ISM band. The various
communication technologies used in WSN are ZigBee
(IEEE802.15.4), Wi-Fi, WiMax and Bluetooth.
Memory requirements are dependent on applications. There
are two categories of memory based on the purpose. User
memory is used for storing application related or personal
data. Program memory is used for programming the device.
Batteries are the main source of power supply for a wireless
sensor node. Due to the restriction in size, batteries used too
have to be in small size, which implies that the lifetime of a
wireless sensor node will be relatively low.
The paper is organized as follows. In section II, the
challenges in designing the wireless sensor node is analyzed.
The VHDL implementation of proposed wireless node and
comparisons are provided in section III. The conclusions are
presented in section IV.
II. CHALLENGES
The major challenges in designing remote reconfigurable
wireless sensor node architecture are as follows:
A. Power Consumption

Fig.1 General Sensor node architecture

Natheswaran S is PG scholar of ME VLSI DESIGN, PSNA college of

Engineering

and

Technology,

Dindigul-624

622,

Tamilnadu,

India,

Phone:960055140 I, email: nathes_waran@yahoo.com

Athisha

is

Professor

and

Head,

Department

of

Electronics

and

Communication Engineering, PSNA College Engineering and Technology,

Dindigul-624 622, Tamilnadu, India, email: hodece@psnacet.edu.in

Since all wireless sensor nodes are battery operated the

most important thing need to be considered is the power
consumption. The power consumption of the wireless sensor
node can be reduced by using different techniques [1]. First
one is to use a low power FPGA like Spartan 6 from Xilinx &
Igloo from Actel as a processing subsystem. Second is to use
partial reconfiguration techniques using FPGA design tools
like Xilinx Plan Ahead. The partial reconfiguration techniques
results in the reduction programming file size i.e., the BIT file

+-IEEE

978-1-4799-3358-7114/$31.00 2014 IEEE

Advancing Technology
for Humanity

649

used to program the FPGA [6]. The life time of the node can
also be increased by using a low cost solar recharging unit
whenever the node is used for environmental monitoring
applications.
B. Wireless JTAG Unit

The FPGAs are programmed through the JTAG port. The

configuration file is sent to the FPGA using the JTAG port to
perform hardware reconfiguration & software reprogramming.
In case of remote reconfigurable wireless sensor node
architecture a wireless JTAG unit has to be used in order to
perform remote hardware modifications and remote software
reprogramming. Since it is not commercially available [1] it is
necessary to design a wireless JTAG unit for the proposed
system.
C. Sensor interfaces

The interfaces for the sensors have to be designed so that

different sensors can be added to the final wireless sensor
node. The sensors are connected to the node using either SPI
or 12C interface. A library consisting of all the sensors that can
be integrated to the wireless sensor node has to be designed.

III. PROPOSED SYSTEM INFRASTRUCTURE

The remote reconfigurable wireless sensor node
architecture consists of a FPGA chip, wireless JTAG unit,
wireless transceiver and sensors as shown in the Fig.2.
The node's FPGA consists of soft components such as soft
core processor, sensor interfaces, JTAG unit and flash
memory. The soft core processor executes the program stored
in the flash memory and takes care of processing the sensed
information from the sensors. The sensor interfaces is used to
integrate the sensor to the wireless sensor node. Flash memory
holds the program and the application data.
The wireless JTAG unit and wireless transceiver is used to
provide communication between the node and the base station.
The VHDL hardware description language is used to design
all the soft components of the wireless sensor node. All the
components in the remote reconfigurable wireless sensor node
& the remote reconfiguration procedure are explained below.

ALU
01P
BUF

IM/
DM

Fig.3 Soft Core Processor Architecture

Hard core processors have more off-the-shelf components

and consume large energy. Soft core processors consume
lesser energy and provide optimal balance between design
flexibility & processing performance.
The proposed soft core processor is shown in the Fig.3. It is
based on the 32 bit non-pipelined MIPS processor [4]. The
data path of the processor consists of PC-Program Counter,
1M-Instruction Memory, DM-Data Memory, IR-Instruction
Register, REG FILE-Register files, ALU-Arithmetic and
Logical Unit and ALU O/P BUF-ALU Output Buffer.
The data flow is controlled by the CU-Control Unit. The
control unit will perform various operations like decoding the
instruction, selection of registers for source and the destination
operands, operation need to be performed by the ALU and
storing the ALU output in the registers.
The proposed soft core processor is capable of executing 15
instructions. Each instruction is 32 bits long. There are five
different types of instructions namely R-type, load &store
type, immediate type, branch type and jump type instructions.
1) R-Type Instructions: The R type instructions perform
basic logical and arithmetic operations like addition,
subtraction, logical AND, logical OR and logical XOR. For
these type of instructions only the top 16 bits will be used
while the remaining will be zero. The instruction format is as
shown below.
Opcode

A. Soft core processor

A soft core processor is a hardware description language

(HDL) model of a specific processor (CPU) that can be
customized for a given application and synthesized for an
ASIC or FPGA.

bits

Source
Register 1

Source
Register 2

Destination
Register

3 bits

3 bits

3 bits

2) Load & Store Type Instructions:

Load & store
instructions are used to read/write data in to the registers from
a memory location. The instruction format is as shown below.

Soft core

Opcode
7 bIts

SourcelDestination
register
3 bIts

Not
used

Not
used

3 bIts 3 bIts

16 Bit
Address
16 bIts

3) Immediate
Type
Instructions:
Immediate
type
instructions include load immediate, store immediate and
immediate and add immediate instructions. The last 16 bits
represents the immediate data. The instruction format is as
shown below.

Flash memory

FPGACIDP

Fig.2 Remote reconfigurable wireless sensor node architecture

650

B.

16 Bit
immediate data
16 bits
4) Branch Type Instructions: Branch type instruction is
used to change the control flow of the program. There are 3
types of branch instructions namely branch on equal, branch
greater than and branch less than. The instruction format is as
shown below.
16 Bit
address
16 bits

Register 1
3 bits

5) Jump & Return Instructions: The interrupts are

processed by using jump and return instructions. The
instruction format for jump & jump instruction is as shown
below.
16Bit
address
16 bits

16 bits
The processing performance of the soft core processor
designed above is enough for almost all the sensors used in the
current generation wireless sensor nodes. The fig.4 shows the
output for all the 15 instructions mentioned above.
The proposed processor architecture requires lesser area
compared to the traditional 32-bit MIPS processor
architecture. Therefore more number of components can be
added to the wireless sensor node compared to the existing
system. The power consumption of the proposed processor is
52mW.

i'-i;''"!-"I!'
i1

1II

---.l

LJ

LJ

0LX CW \
.... 'III!1 ll : OJ lOt.. 02Sl0000

t<1rW<{lS:OJ

1iI:I_Ulr(l;OJ

oooa

000 1

LJ

OOO9
IMCUIOC

LJ

llZ8000ll

IdlOOOCIo

Wireless JTAG Unit:

leOOOOOO

D. JTAG & Sensor Interface:

JTAG interface has to be defined for the FPGA in order to

reprogram it. JTAG interface is defmed using VHDL
hardware description language which allows programming of
FPGA, using the design files stored in the f..lC'S data memory,
through the JTAG cable. Similarly the sensor interface has to
be defmed in order to interface sensors to the wireless sensor
node. Normally the sensors are integrated to the wireless
sensor node using the SPI (Serial Peripheral Interface) and I2C
(Inter Integrated Logic). Both SPI and fc interfaces are
defined using VHDL hardware description language which
allows different sensors to be integrated to the wireless sensor
node.

",,0111115:0]

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iiIIIIiL(IS:0]
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0005

VHDL hardware description language is used to design the

physical layer of wireless transceiver. The physical layer of
the designed wireless transceiver uses DSSS (Direct Sequence
Spread Spectrum) similar to ZigBee to spread the given signal
which is followed by NRZ conversion & Upsampling. At the
receiver side RZ conversion is done on the down sampled
signal. The output of the RZ converter is given to the symbol
correlator to take soft decision for the received signal. The
proposed wireless transceiver consumes lesser power
compared to the conventional ZigBee wireless transceiver [2].
Table II shows the power consumption of existing and
proposed wireless transceiver.
The simulation screenshot of the designed wireless
transceiver is as shown in the fig.5.

Wireless JTAG unit assists the remote reconfiguration of

the FPGA. It consists of a microcontroller and a JTAG cable
connected to the FPGA. The design files received through the
wireless transceiver will be stored in the microcontroller's
data memory. The design file will also contain the controller
program needed to reprogram the FPGA.

Not used

.1O<I(iS:O
l
'I P<l15:01

Wireless Transceiver:

:-x""

lOt..

0000

",." .,
I
,

-X

"'"

.,l{n:o]
.r4[n:O)
.,S{U:O]

00"

.iS:OJ
.'1[15:0]
iiWimO!u:Ol

.
,

"t:jnr2l15:01
1ilIIim-3(15:0]
ip,og.-,mn.Jl[l1:{

001

"'"

."'"

omoJ!l

IIIP<09..troetI\.l. [)I:(

FigA Soft core processor simulation output

TABLET

Fig. 5 Wireless transceiver simulation output

DEVICE UTILIZATION SUMMARY

32-bit MIPS

Proposed

processor

processor

Number of slice registers

22 1

2 12

Number of Slice LUT's

783

685

Number of fully used LUT-FF

200

178

66

33

Slice Logic Utilization

pairs
Number of Bounded lOB's

TABLE II

POWER COMPARISON
Technique

ZigBee Wireless Transceiver

(Existing)
Designed Wireless Transceiver

651

Power Consumption

102mW
82mW

E.

Sensors

Different sensors are used in the wireless sensor node

depending on the type of the applications. For example, in
case of crop growth monitoring temperature sensor &
humidity sensors have to be used.
F. Remote Reconfiguration

core processor is not used in the proposed system. The

designed wireless sensor node components are synthesized
using Xilinx ISE and simulated using Modelsim successfully.
The remote reconfiguration procedure is also explained which
can be used to reprogram the FPGA wirelessly. The future
work involves implementation of the designed remote
reconfigurable wireless sensor node architecture in the
hardware.

The remote reconfiguration is done by ISP (In System

Programming) using an embedded microcontroller [13]. The
steps involved are as follows.
1) A virtual architecture (VA) has to be defmed on top of
the FPGA using User Constraint File (UCF) & FPGA
interfaces.
2) Synthesize the design and create programming file using
ISE design flow.
3) Create a boundary scan configuration file (.SVF) using a
JTAG programmer.
4) Send the boundary scan file obtained in the above step to
the node microcontroller.
5) Reconfigure the FPGA.
Remote FPGA reconfiguration can also be done using
CPLD, Micro blaze or Power PC processors but remote FPGA
reconfiguration using microcontroller is used in the proposed
system in order to reduce the power consumption.

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EIKateeb,

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IV. CONCLUSION

[81

In this paper remote reconfigurable wireless sensor node

architecture was proposed. All the components in the proposed
wireless sensor node architecture are designed using VHDL. A
soft core processor was designed to support the sensor
network node processing. The soft-core processor design is
optimized to the processing needs of the sensor node
application and therefore the node's size and power
consumption is minimized. The use of multi-cycle architecture
is suitable for the soft-core design since it will reduce the
power consumption, minimize the hardware required for the
processor design, and provide enough processing power
required by most of the sensor networks applications.
Therefore the soft core processor with pipelining architecture
or other architecture to increase the performance of the soft-

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Programming

Using

an