Mapua Institute of Technology

School of Electrical, Electronics and Computer Engineering

Muralla St., Intramuros, Manila

8 Bit Arithmic Logic Unit

in partial fulfilment of the requirements in

Logic Circuits and Switching Theory Laboratory
(COE117L/A4)

Submitted by:
Almario, Gian Carlo

De Guzman, Richard S.

Aggabao, Marc Christian R.

Narciso, Adrian G.

Cortezano, Russell Jan P.

Rabino, Eliza Marie

Delim, Carl Anthony H.

Raflores, Melvin

Submitted to:
Engr. Jose Lazaro

June 2016

ACKNOWLEDGEMENTS

After many weeks of hard work in different group acitivities, our group
would like to take this opportunity to express our sincerest gratitude to the
people who have helped and motivated us throughout the entire fabrication
of this prototype.

First, we would like to thank Engr. Jose Lazaro Jr., our instructor for this
course, for guiding and providing us the essential information in order to
establish our project. Second, we want to acknowledge our parent and
friends for their unending support. Also, our classmates in Logic Circuits and
Switching Laboratory for being good colleagues.

And above all, to the Lord Almighty, whom we have acquired our
greatest guidance and for the blessing of strength and wisdom to us.

TABLE OF CONTENTS

TITLE PAGE

ACKNOWLEDGEMENTS

TABLE OF CONTENTS

ABSTRACT

Chapter 1:
DESIGN BACKGROUND AND INTRODUCTION
Chapter 2:
DESIGN METHODOLOGY AND PROCEDURES
Chapter 3:
TESTING, PRESENTATION, AND INTERPRETATION OF DATA

14

Chapter 4:
CONCLUSION AND RECOMMENDATION
15

BIBLIOGRAPHY
APPENDICES

ABSTRACTS

An arithmetic logic unit (ALU) is a digital electronic circuit that performs

arithmetic and bitwise logical operations on integer binary numbers. An ALU
is a fundamental building block of many types of computing circuits,
including the central processing unit (CPU) of computers, FPUs, and graphics
processing units (GPUs). A single CPU, FPU or GPU may contain multiple
ALUs.

An ALU is a combinational logic circuit, meaning that its outputs will

change asynchronously in response to input changes. In normal operation,
stable signals are applied to all of the ALU inputs and, when enough time
(known as the "propagation delay") has passed for the signals to propagate
through the ALU circuitry, the result of the ALU operation appears at the ALU
outputs. The external circuitry connected to the ALU is responsible for
ensuring the stability of ALU input signals throughout the operation, and for
allowing sufficient time for the signals to propagate through the ALU before
sampling the ALU result.

In general, external circuitry controls an ALU by applying signals to its

inputs. Typically, the external circuitry employs sequential logic to control the
ALU operation, which is paced by a clock signal of a sufficiently low
frequency to ensure enough time for the ALU outputs to settle under worstcase conditions.

Chapter 1
Design Background and Introduction

The goal of this project is to design a 4-bit Arithmetic Logic Unit

which is capable of performing four operations. This operations are
Inverter, XOR, Adder and Subtractor. Inverter and XOR will be used for
the logical operation while Adder and Subtractor will be for arithmetic
operation. The last two circuits are shown in the book and are fairly
easy to create and use.

An Adder, also known as Summer, is a circuit capable of

performing addition of numbers; in our case we use binary. Although
we only dealt with the largest, being 3 inputs, this would really deem
us a huge challenge. A full Adder uses AND, OR and XOR gates.

A Subtractor circuit is capable of performing the subtraction of

binary numbers. Unlike the Adder circuit, which produces a SUM and a
CARRY bit when two binary numbers are added together, the binary
subtractor produces a DIFFERENCE, D by using a BORROW bit, B from
the previous column. The operation of these circuit just the opposite to
that of addition.

The main objective of this prototype is:

To be able to apply the concepts and theories learned in Logic Circuits

and Switching Theory.

To design an 8-bit arithmetic logic unit that involves four operations.
To be able to combine and relate the different logic gates and
components based on truth tables and logic tables.

This project will focus on creating what seems like a calculator

which is capable of operations that deal with 8-bit binary inputs. It will
consist of binary variables and a large set of logical operations. These
variables will represent the input for each bit and will pass through the
needed logical operations that the user will present to it. The variables
will then be evaluated and the results will be represented by the set of
LEDs that corresponds to output binary number.

Chapter 2
Project Development Procedures

A week prior, we were given handouts to lean back on and use as

guidance. In those pages truth tables, as well as circuit diagrams, were
shown which would serve as foundation on where we were to build on.

For the days prior, we discussed on what Arithmetic Operations

we would like for our project to do. Hence, we have chosen the Adders
and Subtractors as we were fairly familiar with them in the
experiments.

Here is the sample circuit shown in our handouts, which is only

for a 4-bit logic operator, we were to design an 8-bit logic operator.
This meant that our circuit had to be twice that of the given circuit in
our handout.

TRUTH TABLES

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

S2

S1

S0

Ai

Bi

Xi

Yi

Co

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
1
0
1
1
0
0
0
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

OPERATION
S
A AND B

Pass B to
output
A+B

A-B

B-1

B+1

K-Map

1.)
S1 S0\ Ai Bi

00

01

11

10

00

01

11

10

S1 S0\ Ai Bi

00

01

11

10

Xi (S2 = 0)

2.)

00

01

11

10

S1 S0\ Ai Bi

00

01

11

10

00

01

11

10

Xi (S2 = 1)

3.)

Yi (S2 = 0)

10

4.)
S1 S0\ Ai Bi

00

01

11

10

00

01

11

10

S1 S0\ Ai Bi

00

01

11

10

Yi (S2 = 1)

5.)

00

01

11

10

S1 S0\ Ai Bi

00

01

11

10

C0 (S2 = 0)

6.)

00

01

11

10

Yi (S2 = 1)

Xi = S1 Bi + S2Ai Bi + S2 S0 Bi + S2 S0AiBi + S2S0AiBi + S2 S1 S0 Ai

Yi = S2 S1 Bi + S2 S1 S0 + S2 S1 S0 Bi
C0 = S2 S0

11

Circuit Diagram
Xi
S2 S2 S1 S1

S0 S0

Ai Ai

Bi Bi

Yi
S2 S2 S1 S1

S0 S0

Ai Ai

Bi Bi

C0
12

S2 S2 S1 S1

S0 S0

Ai Ai

Bi Bi

13