Application Note

AN028 Apr 2014

Compensation Design for Peak Current-Mode Buck Converters

Abstract
Peak Current-Mode Controlled Buck Converters are currently very popular and widely adopted in consumer electronics and
computer peripheral power management. This application note presents a design procedure for feedback compensation of peak
current-mode buck converters, and also introduces the SIMPLIS tool for circuit simulations and the Mathcad mathematical
software for quantitative design, and finally provides the verified results by actual measurements.

Contents
1. Open-Loop Analysis of Peak Current Mode Buck Converters ...................................................................2
2. Compensation Design of Peak Current-Mode Buck Converters ................................................................7
3. The Closed-Loop Analysis of Peak Current-Mode Buck Converters ........................................................ 11
4. Conclusion ............................................................................................................................................. 13
5. References ............................................................................................................................................ 13

AN028

2014 Richtek Technology Corporation

Compensation Design for

Peak Current-Mode Buck Converters

1. Open-Loop Analysis of Peak Current Mode Buck Converters

Peak current-mode control is implemented by an inner current loop, composed of a current sensing circuit, Ri, with a slope
compensation (saw-tooth ramp) circuit. The sensed current ramp is summed with the saw-tooth ramp, and then is compared with
the output of the error amplifier, VC. And the result is used to control the ON-time, TON, of the MOSFET. The circuit diagram is
shown in Figure 1.

Figure 1. The circuit diagram of a peak current-mode buck converter

For peak current-mode, sub-harmonic oscillation may occur for duty cycle D > 0.5. In Figure 2, TON is the ON-time of the MOSFET,
and TS is the switching period; the dashed line is for the perturbed inductor current, and the solid line is for the ideal steady-state
inductor current. For D < 0.5, if a perturbation is initiated, it will be completely damped after a few cycles; that is, an unstable state
caused by the perturbation will gradually be stabilized. However, for D > 0.5, if a perturbation is initiated, it will continue to increase
for the next few cycles, which makes the system unstable. Slope compensation is therefore introduced to eliminate the risk of this
sub-harmonic oscillation so that the system can remain stable. Slope compensation is implemented by adding a saw-tooth ramp
of the same frequency as of the control circuit to the sensed inductor current ramp so that the system can still be stable at duty
cycle above 0.5.

Figure 2. The sensed inductor current ramps by Ri at duty cycles D < 0.5 and D > 0.5

AN028

2014 Richtek Technology Corporation

Compensation Design for

Peak Current-Mode Buck Converters
The small-signal model of a peak current-mode buck converter [1] [2] will be introduced in this section. The Buck PWM Switch
Model, proposed by V. Vorperian [1] and the small-signal model for peak current-mode control, by Raymond B. Ridley [2] are
displayed in Figure 3. The equations derived according to the model will be applied in compensation design for peak currentmode buck converters.

Figure 3. The Buck PWM switch model and the small-signal model for peak current-mode control
The open-loop transfer function of a peak current-mode buck converter is listed below [1], [2]:

Gd s

Ro
Ri

Ro Ts
L1

mc 1 D 0.5

Fp s Fh s

(1)

Fp (s) in Equation (1), which dominates the open-loop low-frequency characteristics of this configuration, is shown below, as
Equation (2), which has a zero and a pole.

Fp s

1 s Cout RC
s
1
p

(2)

Fh (s) in Equation (1) represents the high-frequency characteristics of this configuration, where the current-sense transformer Ri
plays an important role. Fh (s) is described below, as Equation (3) and it has two high-frequency poles.
Fh s

1
1

AN028

s
s

n Qp
n

(3)

2014 Richtek Technology Corporation

Compensation Design for

Peak Current-Mode Buck Converters
Figure 4 shows a low-frequency dominant pole (at a slope of -20dB / decade), and a high-frequency double pole (at a slope of 40dB / decade decaying). The ESR zero in between is from the ESR of the output capacitor.

Figure 4. The Bode plot of the open-loop peak current-mode buck converter
The equations for compensation design will be analyzed step by step as follows:
To begin with, the equation of the exact low-frequency pole is presented below:

fpole

Ts
1
1

mc 1 D 0.5

2 Cout Ro L1 Cout

(4)

Advanced computational tools will be needed to calculate for the above equation. However, the simplified equation, listed below,
is a close approximation, by which the pole can be found quickly.

fp_approx

1
2 Ro Cout

(5)

The equation below is for the output capacitor zero

fzero

1
2 Rc Cout

(6)

The following equation is for the double pole, positioned at the half of the switching frequency:
f
fn s
2

AN028

(7)

2014 Richtek Technology Corporation

Compensation Design for

Peak Current-Mode Buck Converters
With the equations above, a design example will be offered to describe the important characteristics of a peak current-mode buck
converter.
Figure 5 displayed the circuit diagram and the corresponding circuit parameters of a buck converter. The input voltage is 12Vdc,
the rated output current 3A, the output voltage 3.3V, the operating frequency 340kHz, the inductance 10H, the output capacitance
44F, and its ESR 5m.

S2

L1

RL

Iout

Rc
Vin

Ro

S2

Vout

Cout

Figure 5. The circuit diagram and the corresponding circuit parameters of a peak current-mode buck converter.
Substitute the above parameters to Equation (4) to obtain a more accurate low-frequency first-order pole, which is located at
4.3kHz.

fpole

Ts
1
1
3

mc 1 D 0.5 4.322 10

2 Cout Ro L1 Cout

Slope compensation factor, mc, is defined as mc 1

Se
, where Se is the slope of the added compensation
Sn

saw-tooth ramp and Sn the slope of the sensed current ramp when the switch is on.

Se

507 10-3 , T 1 , S Vin Vout R , R 1 192m

s
n
i
i
Ts
fs
L1
5.2

By Equation (5), the first-order pole, 3.3kHz, can be readily calculated as below.

fp_approx

AN028

1
3
3.288 10
2 Ro Cout

2014 Richtek Technology Corporation

Compensation Design for

Peak Current-Mode Buck Converters
Substitute the above parameters to Equation (6), and the exact location of the output capacitor ESR zero can be found as 723kHz.

fzero

1
3
723.432 10
2 Rc Cout

Then, by Equation (7), the high-frequency double pole is obtained as 170kHz.

f
fn s 170 103
2

Gain Plot

With all the parameters above plugged in, a Bode plot can be drawn by Mathcad as below.
In Figure
Gain
Plot6, it can be seen that a pole
20
occurs at low frequency (3.28kHz), and ESR zero (723kHz) occurs at20an even higher frequency than the double pole, since the

Gain Plot
Dominate pole

Gain / dB

60

20 20

20

Phase / degrees

40

60
1

10

100 110 110 110

Frequency
/ Hz

10
100 / Hz
110
Frequency

110

135
90

Two
poles

45
0
45
90

135 Control-to-output
3
4
5
1 225 180
10
100
110 110 ut110
Control-to-outp

110

Phase Plot

180

90

110

110

180

135

6 60
110

3
4
5
10 Control-to-outp
100 110ut ESR
110 zero
110

60

45

45

40

Double pole

40

Phase / degrees

20

225

Gain / dB

20

40

Phase Plot

Gain Plot

20

Gain / dB

Gain / dB

smaller ESR is used.

0

1 225 10
1

Frequency / Hz

100

110

110

110

3
Frequency
10
100 / Hz
110

Frequency / Hz

110
6

110

110

110

110

Frequency / Hz

Figure 6. The Bode plot of the open-loop peak current-mode buck converter in the design example

AN028

2014 Richtek Technology Corporation

Compensation Design for

Peak Current-Mode Buck Converters

2. Compensation Design of Peak Current-Mode Buck Converters

The previous section has described the characteristics of a peak current-mode buck. In this section, how to compensate peak
current-mode buck converters for system stability will be investigated. In Figure 7, the open-loop gain is plotted in red; at low
frequencies, the DC gain is low. Low DC gain at low frequencies can cause steady-state errors, which can be seen in Figure 10,
for which the frequency responses of two different DC gains with the same bandwidth and phase margin are displayed in Figure
9. For f > fc, the gain curve is at the slope of -40dB / decade, and the phase curve is at the slope of -90/ decade, which often
results in insufficient phase margin, illustrated in Figure 8, which furthermore causes system instability. The optimal closed-loop
gain is drawn in blue. Compared with the open-loop gain, the closed-loop gain manifests the following advantages: higher DC
gain at low frequency so that the steady-state errors can be minimized as in Figure 10, and for f > fc, the gain is at the slope of 20dB / decade, and the phase -45/ decade, as shown in Figure 7, thereby to improve the phase margin (P.M.).

Gain Plot
100
80

Gain Plot

Open-loop
Closed-loop

40

Gain / dB

Gain / dB

60 20High

DC gain

40

-20dB/decade

20
20

Wide BW

20 40
40

60

60

10

10

-40dB/decade
Noise3 Attenuation
4
5
110

100

110

110

100

110
4

110

Frequency / Hz

110
5

110

110

Figure 7. The comparison of the

open-loop
and closed-loop Bode plots
Frequency
/ Hz

dB
40

Single Pole
First Order

20

-20 dB/ decade

0
fp/10

fp

dB

degree
180o

135o

135o

90o

90o

10fp 100fp

fp

10fp

System could oscillate.

45o

P.M. > 45
fp

180

fp/10

-40 dB/ decade

20

fp/10

10fp 100fp

degree

45o

Double Pole
Second Order

40

P.M. < 45

0
fp/10

fp

10fp

Figure 8. Single pole vs. double pole

AN028

2014 Richtek Technology Corporation

Compensation Design for

Peak Current-Mode Buck Converters

Effect of DC Gain

Phase / degree

Gain / dB

Phase(Loop Gain) / degrees Gain(Loop Gain) /

Higher
80
DC gain
40

BW

0
-40

The same bandwidth and phase margin,

-80

but the different DC gains.

160
120
80
40
-0

P.M.
1

10 20 40

100 200 400

1k 2k 4k

10k 20k 40k 100k

400k 1M

Frequency / Hz
freq / Hertz

Figure 9. Different DC gains with the same bandwidth and phase margin

Vout / V

Iout / A

3
2.5

0.5
3.345
3.34

Vout / V
GainGain
/ dB/ dB
Gain / dB

Vout / V

Dynamic Load

31.5

2.50.5
3.6
23.5
3.4
1.53.3
3.2
3.1

Vout / V

I(S3-P) / A

I(S3-P) / A

In Figure 10, it can be seen load regulation is better with higher DC gain, and worse with lower DC gain.

Control-to-Output
Gain
Control-to-Output
Gain
Control-to-Output Gain Time / mSec

0.2

120120
time/mSecs

0.4

0.6

0.8

200uSecs/div

w/ Higher DC Gain
100
100100
80
80 80

3.335

60 60
60
40 40
3.325
w/ Lower DC Gain
40
3.32
20 20 0.2
0
0.4
0.6
0.8
1
20
0
0
time/mSecs
200uSecs/div
Figure010. The effect of DC gains on load regulation
20 20
Control-to-Output
Control-to-Output
20
40
Loop
Gain
40
Control-to-Outp
Loop
Gain ut
Based on the above analysis of the circuit60
parameters
on Gain
system performance, what is needed for a compensator is a zero to
40
Loop
60
3.33

3 3
4 4
5 5
6 6
cancel the low-frequency pole of a peak current-mode
buck
as
100converter,
10
110
10
100110
1101
1 in
10Figure
110 111,
1so
10 that the gain curve will be at the slope
601 1 10 10
3
4
5
6
10 to 100
110
110 phase
110 margin.
110 At high frequencies, a high-frequency
of -20dB / decade at the crossover frequency,1 thereby
achieve
a better

Frequency
/ Hz
Frequency
/ Hz

Gain
/ dB
Gain
/ dB
Gain / dB

compensator pole can help filter out high-frequency noises.Frequency / Hz

100100
100
80 80
80
60 60
60
40 40
40
20 20
20
0 0
0
20 20
201 1
1

Compendator
Gain
Compendator
Gain
Compendator Gain

-20dB/decade

Pole
Zero
Compendator
Gain
Compendator
Gain
Compensator Gain
3

4
5
1310110
1
10110
1
10 110
1610
10 10 100100110
3
4
5
6
10
100 110 110 110
110

Frequency
/ Hz
Frequency
/ Hz
Frequency / Hz
Figure 11. A compensator offers a zero and a pole
AN028

2014 Richtek Technology Corporation

Compensation Design for

Peak Current-Mode Buck Converters
Take a GM-Type compensator below as an example. Since a GM-Type compensator has one zero and two poles, it is quite
suitable to compensate peak current-mode buck converters. First pole can be obtained from Rgm and Ccomp, the other pole from
Rcomp and Cgm, and a zero from Rcomp and Ccomp.

Figure 12. A GM-Type compensator

Compensator Design Procedure :

Step 1 :
Set the crossover frequency (i.e. the bandwidth). In the example above, the operating frequency is 340kHz, and the bandwidth is
usually set as 1/10 of the operating frequency.

fc 34 10

(8)

Step 2 :
Set the zero of the compensator to cancel the pole of the peak current-mode buck topology.
3

fz fpole 4.322 10

(9)

Step 3 :
The compensator pole is set to the lower frequency among the ESR zero and 1/2 of the operating frequency. In this example, 1/2
of the operating frequency is lower than the ESR zero, so set the compensator pole to 1/2 of the operating frequency.

fp

1
fs 170 103
2

(10)

Step 4 :
By Mathcad, the phase margin of 48 can be obtained by the following equation. Usually for stability, the phase margin should be
greater than 45.

M fc 180 90 atan

AN028

f
fc 180

atan c
fz

fp

180
48.918

2014 Richtek Technology Corporation

(11)

Compensation Design for

Peak Current-Mode Buck Converters
Step 5 :
From Equation (12), the DC gain, increased by the compensator at the crossover frequency, can be calculated as17.4dB.

f
VREF
f
20 log ceil c 20 log ceil z 17.371 (12)
Vout
fc

fp

GA Gfc 20 log

Step 6 :
The parameters of the compensator in this example, such as Rcomp = 5.9k, Ccomp = 6.23nF, Cgm = 158pF, can all be obtained
as follows.
3

-3

Rgm 200 106

Ccomp

20

Vc

gm
VREF

GA

GA
Rcomp
101

Rcomp 10 20

VFB

Rgm 200 10

g m 1.25 10
gm 1.25
10

Rcomp
Rgm

Cgm

5.911
3 10

Ccomp

gm
5.911
10

gm

1
1
-9 9
6.23
Ccomp 2 f R 6.23
10 10
2 fz Rcomp
z comp

fP1
fP2

1
1 158.393 10-12 12
Cgm C
158.393 10
gm fp 2
2
Rcomp
f R

fZ

p comp

Step 7 :
Substitute all the above numbers into Equation (13), then enter the equation into Mathcad, and the Bode plot of the compensator
can be drawn, seen in Figure 13.

p1

1
Rgm Ccomp

p1
-3
127.741 10
2

1
Rcomp Ccomp

z
4.322 103
2
p2
3
170 10
2

s
z

Gain Plot

s
s
1 1
p120
p2
0

Gain Plot

Compensator Bode Plots:

20
60
40

60

180

fP1
100
80

80

Gain / dB

40

Gain Plot

Gain / dB

100

Gain / dB

Gain / dB

Gain / dB

Gain Plot

60
40

40

20

10
0

0.01

fP2

20

60
0.1
1

100
1

0
0.01

110
0.1

fZ1104
10
3

100
4

10
100 110 1103
Frequency
10
100 / Hz
110

(13)

Phase Plot

120

120

20

Gain Plot
20

110
3

135
135

90
135

90

45 6
110 110
0.1 6 1
5

110

110

90

45
90
135

60
5

45
0

40

110
110
5
6
110 1410

10
Frequency 1/
Hz
Frequency / Hz

225
Phase Plot Phase Plot
180

180

20

110
4

Phase / Degrees

A gm Rgm

20

Phase / degrees

1
Rcomp Cgm

Phase / Degrees

p2

3
4
5
6
180 100 Control-to-outp
10
110 110 1ut
10
110
3
4
5
6
1
10 3 100 4 110 5 110 6 110 110
225100
110
110
110
1103
4
5
/ Hz
1 Frequency
10
100
Frequency
/ Hz 110 110 110

45
0.1
10

110

Frequency / Hz

Figure/13.
Frequency
Hz The Bode plot of the compensatorFrequency / Hz
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Compensation Design for

Peak Current-Mode Buck Converters

3. The Closed-Loop Analysis of Peak Current-Mode Buck Converters

In this section, the SIMPLIS tool is used to simulate the peak current-mode buck converter and to substantiate the closed-loop
frequency response analysis. The SIMPLIS schematic is displayed in Figure 14. The closed loop of this current-mode buck
converter incorporates a current sensor, a compensator, and a slope compensation circuit.
Comp

H1
192.3m

Vout
IN

IC=1
S1
R4

GND

FB

Comp

OUT

IN

=OUT/IN

Vac

OUT

IN

=OUT/IN

VCS

Vout
OUT

=OUT/IN

Vout

Current Sensor

12
V1

10m

10u

R2

L1

U2

10m
R10

10m
R1

22u
C5

22u
C1

Dynamic Load

IC=1
S2
R5

R3S3
1.1

GND

V6
AC 1m 0
V5

Vac
U3
X1

OSC

POP

Clock

Slope Comp.

U1

Scomp

U4

Comp

GND

1.25m
G1

GND

V2

FB

R9
26.1k

0.925
V4

R8
10k

6.23n
Ccomp

GND

POP
V3

Compensator

Scomp

RT N

Q
QN

OSC

VCS

158.39p Rgm
Cgm
200Meg

Rcomp
5.91k

Current-Mode
Modulator

Figure 14. The SIMPLIS simulation shematic (the closed-loop peak current-mode buck converter)
In Figure 15, the equation from the previous section (red line) is drawn by Mathcad, which is verified with the simulation result
(blue dots) of the SIMPLIS schematic in Figure 14. It demonstrates that the simulation result closely aligns with the analytical
result, derived by Mathcad, and the bandwidth and phase margin are 34kHz and 48.9, respectively.

Gain Plot

Phase Plot

100

135

80

90

Phase / Degrees

Gain / dB

60
40
20

20
40
60
1

34kHz

BW

Predicted Curve
Simulated Curve
10

100

110

45

P.M.
0
45

110

Frequency / Hz

48.9

110

110

Predicted Curve
Simulated Curve

90
1

10

170kHz

100

110

110

110

110

Frequency / Hz

Figure 15. The comparison of theoretical analysis with the Matchcad and the SIMPLIS simulation
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Compensation Design for

Peak Current-Mode Buck Converters
Figure 16 has exhibited the benefits a compensator can provide. First, a compensator (black dashed line) enhances DC gain in
the low frequency range. The open loop response (red line), combined with the compensator response (black dashed line), makes
the closed loop response (blue line). Second, a compensator increases bandwidth, as in Figure 16, the crossover frequency in
blue is greater than that in red. Third, a compensator adds one high-frequency pole, which improves high-frequency noise
immunity (at high frequency, the blue line drops faster than the red line). Fourth, the zero of a compensator helps achieve a
sufficient phase margin.

Gain Plot
Gain Plot

20
100
100

20

180
180
225

Gain
Gain
/ dB/ dB
Gain / dB
Phase / degrees

Gain
Gain
/ dB/ dB
Gain / dB
Gain / dB

080
80
6060

4040
20
20
20
20

0 0
40
20 40
20
40
40

60

Gain Plot
Phase Plot

20

Open-loop
Open-loop
Closed-loop
Closed-loop
Compensator
Compensator

3
4
5
6
60
60
1 60 10
100 110 1310 1410 5110 6
3 1310 4 1410 5 1510 6 1610
100100
10
10 1110
10 1110
10
1 1 1 1010 10100
1110
1110

180
135
0135
135
9090
90
4545
20
45
000
4545

45

40

9090

90
135
135

135
60 180

180
180
1225
11

Frequency / Hz
Frequency
Frequency
/ Hz/ Hz
Frequency
/ Hz

Open-loop
Open-loop
Closed-loop
Closed-loop
Compensator
Compensator
Control-to-outp ut
10
1

110

100

110 4 1105

1106

3
4
5
6
4110
5110
6
100 1110
10
10
10
10
101010 100
13110
1
1
100 110
110
110
110

Frequency / Hz

Frequency/ Hz
/ Hz
Frequency
Frequency
/ Hz

Figure 16. The comparison between the open loop and the closed loop
An actual measurement setup is presented in Figure 17, and an AC perturbation signal is injected into point R. The gain and
phase plot can be obtained by measuring the output (point A) versus the input (point R). From the right-hand plot of Figure 17,

Gain Plot

the measured result (green line) shows good agreement with the analytical result (red line).
20

Gain Plot

80
60

Vin

Ro

Vout

v o

Gain / dB

Perturbation
Injection Circuit

20

Gain / dB

Iout

R
R
1

d
Duty Cycle

Q R
gm

QS

Clock

Vc

VREF
Rcomp
Ccomp

Cgm

Rgm

R2

60
80 225
135
100
1

180

20

Phase / Degrees
Phase
/ degrees

v i

Gain Plot

20

20 40 40
60

Gain / dB

Sensed Current Ramp

Sn

20

50
Ri
Slope
Compensation

40

40

60

90

Predicted Curve
Simulated Curve
M easured CurvePhase

Plot

Phase Plot
3

11010

1100
10

4 1106

110

110 110
110

110

110

Frequency / Hz

135

Frequency / Hz

90
45

45

45

45

90 Predicted Curve

135

1 90 180
10

Simulated Curve
M easured Curve 3
3

110

225

100

Control-to-outp
100
110 110 ut110
4

110

110

3
Frequency
/1Hz
10
100/ Hz
10
Frequency

110

110

110

Figure 17. The experimental results verify the closed loop frequency response
Frequency / Hz
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110

Compensation Design for

Peak Current-Mode Buck Converters

4. Conclusion
At low frequencies, an open-loop peak current-mode buck converter is still a single-pole system since the loop control is
realized by injecting current signals into the loop only.

Its compensator is easy to design. The compensator zero is designed to cancel the dominant pole of a buck converter for
system stability.

In order to assure sufficient phase margin, the design goal is that the gain curve is at the slope -20dB / decade, when passing
the crossover frequency.

5. References
[1] V. Vorperian, Simplified analysis of PWM converters using model of PWM switch part I:
continuous conduction mode, IEEE Trans. on Power Electronics, vol. 26, no. 3, pp. 490-496,
May 1990.
[2] Raymond B. Ridley, A New Small-signal Model for Current-mode Control, Ph.D. Dissertation,
Virginia Polytechnic Institute and State University, Nov. 1990.

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