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shekhavl123@gmail.com
+91-8141924263
M.Tech from Nirma University with excellent academic record and keen interest and practical exposure in the field of
Physical Design, Signal Integrity & Power Integrity, Antenna Design, Verification, Automation and Wireless
Communication.
Core Competency
Good understanding of inputs and outputs of all the stages in the physical design flow i.e. floor planning, power
planning, clock tree synthesis, signal integrity, routing, design rule check and parasitic extraction (Making SPEF
file).
In clock tree synthesis, good understanding of clock tree quality check parameters (skew, latency, transition
variation etc...), H Tree, modelling of clock tree and buffered H Tree.
In signal integrity, good understanding of impedance mismatch, crosstalk, glitch effect, timing windows, crosstalk,
crosstalk delta delay analysis, noise protection technique, rail collapse noise, EMI, radiation issue, power supply
noise and power mesh solution.
Work Experience
STMicroelectronics India Ltd. (1 Year-Full Time)
June15- June16
June14- May15
Technical Skills
Programming Languages
Scripting Languages
Education
M.Tech EC- (Communication Engineering)
IT-NU, CGPA 7.9/10
2014-16
2009-13
Web Presence
Declaration
I hereby declare that the above written particulars are true and correct to the best of my knowledge and
belief.