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Table of Contents
1. Introduction
1.1
codes ............................................................................1
Error
correction
1.2
correction........................................................................................2
Error
3.
Design
of
Hamming
code .................................................................8
3.1
Origin
Code.........................................................................8
of
Hamming
3.2
Basic
Theory ...........................................................................................8
3.3
Designing
(n,
k,
t)
Hamming
code .........................................................10
3.4 Methodology of operation of a simple ( 7, 4 , 1 ) hamming
code..........12
3.5 Design of the Hamming code Encoder and
Decoder ............................17
3.6
Pin
Descriptions .....................................................................................23
4. Implementation
4.1
The
(11,
code.................................................................24
7,
1)
4.2
Results..................................................................................29
4.3
report .....................................................................................31
Hamming
Simulation
Synthesis
of
the
hamming
5.2
Applications.............................................................................................32
Future
7. Source code
7.1
Hamming_encoder.v ...............................................................................36
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7.2
Hamming_decoder.v ..............................................................................37
References
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Introduction
1.1 Error correction codes
In computer science and information theory, the issue of error correction
and detection has great practical importance. Error correction codes ( ECCs)
permit detection and correction of errors that result from noise or other
impairments during transmission from the transmitter to the receiver. Given
some data, ECC methods enable you to check whether data has been corrupted,
which can provide the difference between a functional and nonfunctional system.
Error correction schemes permit error localization and also give the
possibility of correcting them. Error correction and detection schemes find use in
implementation of reliable data transfer over noisy transmission links, data
storage media (including dynamic RAM, compact discs), and other applications
where the integrity of data is important. Error correction avoids retransmission of
the data, which can degrade system performance.
RAM Devices
RAM devices do not as such support error control codes. There are no
mandatory requirements for ECC support on RAM/DRAM devices. Memory
suppliers are generally not in favor of implementing a complex logic function like
ECC onto a RAM die. It is costly, inefficient, and leads to an expensive memory
subsystem. Where enhanced reliability is a requirement, the standard technique
is to use a wider interface. In the context of SDRAMs, DIMMs come in two widths:
64 and 72 bits. The 72-bit DIMMs are targeted for use with ECCs, because of the
extra 8 bits. The extra 8 bits are merely extra data bits , in reality you can use
any of the bits. An extra 8 bits of parity on 64 bits of data allows you to employ a
two-bit error detection. single bit correcting Hamming code.
Hamming code
Hamming code is an error-correction code that can be used to detect
single and double-bit errors and correct single-bit errors that can occur when
binary data is transmitted from one device into another.
Hamming codes provide for FEC using a "block parity" mechanism that
can be inexpensively implemented. In general, their use allows the correction of
single bit errors and detection of two bit errors per unit data, called a code word.
The fundamental principal embraced by Hamming codes is parity.
Hamming codes, as mentioned before, are capable of correcting one error or
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Hamming Code
detecting two errors but not capable of doing both simultaneously. You may
choose to use Hamming codes as an error detection mechanism to catch both
single and double bit errors or to correct single bit error. This is accomplished by
using more than one parity bit, each computed on different combination of bits in
the data.
This report presents design and development of (11, 7, 1) Hamming code
using Verilog hardware description language (HDL). Here, 11 corresponds to
the total number of Hamming code bits in a transmittable unit comprising data
bits and redundancy bits, 7 is the number of data bits while 1 denotes the
maximum number of error bits in the transmittable unit. This code fits well into
small field-programmable gate arrays (FPGAs), complex programmable logic
devices (CPLDs) and application-specific integrated circuits (ASICs) and is ideally
suited to communication applications that need error-control.
1. 2 Error correction
Use of simple parity allows detection of single-bit errors in a received
message. Correction of these errors requires more information, since the position
of the corrupted bit must be identified if it is to be corrected. (If a corrupted bit
can be detected, it can be corrected by simply complementing its value.)
Correction is not possible with one parity bit since any bit error in any position
produces exactly the same information, i.e., error. If more bits are included in a
message, and if those bits can be arranged such that different corrupted bits
produce different error results, then corrupted bits could be identified.
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2 . 2 Verilog Overview :
Introduction :
Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). A hardware
description Language is a language used to describe a digital system, for
example, a microprocessor or a memory or a simple flip-flop. This just
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means that, by using a DL one can describe any hardware (digital ) at any
level.
One can describe a simple Flip flop as that in above figure as well as one
can describe a complicated design having 1 million gates. Verilog is one of the
HDL languages available in the industry for designing the Hardware. Verilog
allows us to design a Digital design at Behavior Level, Register Transfer Level
(RTL), Gate level and at switch level. Verilog allows hardware designers to
express their designs with behavioral constructs, deterring the details of
implementation to a later stage of design in the final design.
Verilog provides both behavioral and structural language structures. These
structures allow expressing design objects at high and low levels of abstraction.
Designing hardware with a language such as Verilog allows using software
concepts such as parallel processing and object-oriented programming. Verilog
has syntax similar to C and Pascal.
2 . 3 Design Styles
Verilog like any other hardware description language permits the designers to
Bottom-Up Design
The traditional method of electronic design is bottom-up. Each design is
performed at the gate-level using the standard gates. With increasing complexity
of new designs this approach is nearly impossible to maintain. New systems
consist of ASIC or microprocessors with a complexity of thousands of transistors.
These traditional bottom-up designs have to give way to new structural,
hierarchical design methods. Without these new design practices it would be
impossible to handle the new complexity.
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Top-Down Design
The desired design-style of all designers is the top-down design. A real
top-down design allows early testing, easy change of different technologies, a
structured system design and offers many other advantages. But it is very
difficult to follow a pure top-down design. Due to this fact most designs are mix
of both the methods, implementing some key elements of both design styles.
Complex circuits are commonly designed using the top down methodology.
Various specification levels are required at each stage of the design process.
Behavioral level
This level describes a system by concurrent algorithms (Behavioral). Each
algorithm itself is sequential, that means it consists of a set of instructions that
are executed one after the other. Functions, Tasks and Always blocks are the
main elements. There is no regard to the structural realization of the design.
Register-Transfer Level
Designs using the Register-Transfer Level specify the characteristics of a
circuit by operations and the transfer of data between the registers. An explicit
clock is used. RTL design contains exact timing possibility; operations are
scheduled to occur at certain times. Modern definition of a RTL code is "Any code
that is synthesizable is called RTL code".
Gate Level
Within the logic level the characteristics of a system are described by
logical links and their timing properties. All signals are discrete signals. They can
only have definite logical values (`0', `1', `X', `Z`). The usable operations are
predefined logic primitives (AND, OR, NOT etc gates). Using gate level modeling
might not be a good idea for any level of logic design. Gate level code is
generated by tools like synthesis tools and this Netlist is used for gate level
simulation and for backend.
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4 . 2 Basic Theory
Hammings development [Ham] is a very direct construction of a code that
permits correcting single-bit errors. He assumes that the data to be transmitted
consists of a certain number of information bits u, and he adds to these a
number of check bits p such that if a block is received that has at most one bit in
error, then p identifies the bit that is in error (which may be one of the check
bits).
Specifically, in Hammings code p is interpreted as an integer which is 0 if
no error occurred, and otherwise is the 1-origined index of the bit that is in error.
Let k be the number of information bits, and m the number of check bits used.
Because the m check bits must check themselves as well as the information bits,
the value of p, interpreted as an integer, must range from 0 to which is distinct
values.
Because m bits can distinguish cases, we must have
2m m+k+1.
Where
k = Number of information or message bits.
m = Number of parity-check bits (check bits, for short).
n = Code length, n = m + k.
u = Information bit vector, u0, u1, uk1.
p = Parity check bit vector, p0, p1, , pm1.
s = Syndrome vector, s0, s1, , sm1.
This is known as the Hamming rule. It applies to any single error correcting
(SEC) binary FEC block code in which all of the transmitted bits must be checked.
The check bits will be interspersed among the information bits in a manner
described below.
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Because p indexes the bit (if any) that is in error, the least significant bit of
p must be 1 if the erroneous bit is in an odd position, and 0 if it is in an even
position or if there is no error. A simple way to achieve this is to let the least
significant bit of p, p0, be an even parity check on the odd positions of the block,
and to put p0 in an odd position. The receiver then checks the parity of the odd
positions (including that of p0). If the result is 1, an error has occurred in an odd
position, and if the result is 0, either no error occurred or an error occurred in an
even position. This satisfies the condition that p should be the index of the
erroneous bit, or be 0 if no error occurred.
Similarly, let the next from least significant bit of p, p1, be an even parity
check of positions 2, 3, 6, 7, 10, 11, (in binary, 10, 11, 110, 111, 1010, 1011,
), and put p1 in one of these positions. Those positions have a 1 in their second
from least significant binary position number. The receiver checks the parity of
these positions (including the position of p1). If the result is 1, an error occurred
in one of those positions, and if the result is 0, either no error occurred or an
error occurred in some other position. Continuing, the third from least significant
check bit, p2, is made an even parity check on those positions that have a 1 in
their third from least significant position number, namely positions 4, 5, 6, 7, 12,
13, 14, 15, 20, , and p2 is put in one of those positions.
Putting the check bits in power-of-two positions (1, 2, 4, 8, ) has the
advantage that they are independent. That is, the sender can compute p0
independently of p1, p2, and, more generally, it can compute each check bit
independently of the others.
Hamming Code
24 7+4+1
Parity Bits
A parity bit is the extra bit included to make the total number of 1s in the
resulting code word either even or odd.
With Odd
Parity
1000001
7bits
1010100
01000001
8 bits
11010100
11000001
01010100
For a 7-bit number there are 7 possible one bit errors. 64 different binary
permutations can be recognized in a string of length 6 bits. However, another
state is needed to represent the case when a detectable error has not occurred.
The number of parity bits, m, needed to detect and correct a single bit
error
in a data string of length n is given by the following equation:
m = log2n +1
The ECC block uses the Hamming code with an additional parity bit, which
can detect single and double-bit errors, and correct single-bit errors. The extra
parity bit applies to all bits after the Hamming code check bits have been added.
This extra parity bit represents the parity of the codeword. If one erroroccurs, the
parity changes, if two errors occur, the parity stays the same. In general the
number of parity bits, m, needed to detect a double-bit error or detect and
correct a single-bit error in a data string of length n, is given by the following
equation:
m = log2n +2
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4.4
of operation of
simple ( 7 , 4 ,
code :
P1
P2
P3
D1
Yes
Yes
No
D2
Yes
No
Yes
D3
No
Yes
Yes
D4
Yes
Yes
Yes
Methodology
a
1 ) hamming
The goal of Hamming codes is to create a set of parity bits that overlap
such that a single-bit error (the bit is logically flipped in value) in a data bit or a
parity bit can be detected and corrected. While multiple overlaps can be created,
the general method is presented in Hamming codes.
This table describes which parity bits cover which transmitted bits in the
encoded word. For example, p2 covers bits 2, 3, 6, & 7. It also details which
transmitted by which parity bit by reading the column. For example, d1 is
covered by p1 and p2 but not p3. This table will have a striking resemblance to
the parity-check matrix ( ) in the next section.
Furthermore, if the parity columns in the above table were removed then
resemblance to rows 1, 2, & 4 of the code generator matrix ( G) below will also
be evident.
So, by picking the parity bit coverage correctly, all errors of Hamming
distance of 1
can
be
Bit#
1
2
3
4
5
6
7
detected
and
corrected,
p2
d1 p3 d2 d3 d4
which is the Transmitted p1
point
of
using
a bit
Hamming
code.
P1
Yes
No Yes No Yes No Yes
Hamming
matrices
P2
P3
No
No
Yes
No
Yes
No
No
Yes
No
Yes
Yes
Yes
Yes
Yes
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H:
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Hamming Code
And
Channel coding
Suppose we want to transmit this data over a noisy communication
channel. Specifically, a binary symmetric channel meaning that error corruption
does not favor either zero or one (it is symmetric in causing errors). Furthermore,
all source vectors are assumed to be equi probable. We take the product of G
and p, with entries modulo 2, to determine the transmitted codeword x:
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Hamming Code
Parity check
If no error occurs during transmission, then the received codeword r is identical
to the transmitted codeword x:
r=x
The receiver multiplies H and r to obtain the syndrome vector , which indicates
whether an error has occurred, and if so, for which codeword bit. Performing this
multiplication (again, entries modulo 2) :
Since the syndrome z is the null vector, the receiver can conclude that no error
has occurred. This conclusion is based on the observation that when the data
vector is multiplied by G, a change of basis occurs into a vector subspace that is
Error correction
Otherwise, suppose a single bit error has occurred. Mathematically, we can Write
R = x + ei
modulo 2, where ei is the ith unit vector, that is, a zero vector with a 1 in the ith,
counting from 1
Thus the above expression signifies a single bit error in the ith place. Now, if we
multiply this vector by H:
Since x is the transmitted data, it is without error, and as a result, the product of
H and x is zero. Thus
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Hamming Code
Now, the product of H with the ith standard basis vector picks out that
column of H, we know the error occurs in the place where this column of H
occurs. For example, suppose we have introduced a bit error on bit #5
Now,
Decoding
Once the received vector has been determined to be error-free or corrected if an
error occurred (assuming only zero or one bit errors are possible) then the
received data needs to be decoded back into the original 4 bits.
First, define a matrix
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R:
13
Hamming Code
number of bits in the input data. The generated code word is then
transmitted to the destination.
The receiver receives the code word and decodes it. Information obtained
by the decoder determines whether or not an error is detected. The decoder
detects single-bit and double-bit errors, but can fix only single-bit errors in the
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corrupted data. This kind of ECC is called Single Error Correction Double Error
Detection (SECDED).
The general block diagram of a Hamming code encoder and decoder is
shown below :
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Hamming Code
The parity bit derivation uses an even-parity checking. The additional 1 bit
(shown in Table 11 as +1) is appended to the parity bits as the MSB of the code
word. This ensures that the code word has an even number of 1s.
For example, if the data width is 4 bits, 4 parity bits are appended to the
data to become a code word with a total of 8 bits. If 7 bits from the LSB of the 8bit code word have an odd number of 1s, the 8th bit (MSB) of the code word is 1
making the total number of 1s in the code word even.
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Hamming Code
Inp(10:0)
outp(6:0)
reset
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Hamming Code
19
Hamming Code
Pin
Name
Inp
In/Out
Width
Module
Description
In
6:0
(7 bits)
Encoder
Reset
Outp
In
Out
Encoder
Encoder
Inp
In
Decoder
Reset
Outp
In
Out
10:0
(11 bits)
10:0
(11 bits)
6:0
(7 bits)
Decoder
Decoder
Implementation
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Hamming Code
MSB
LSB
11 10
9
8
7
6
5
4
3
2
1
d7 d6 d5 p4 d4 d3 d2 p3 d1 p2 p1
Fig. 5.1 : Positions of parity bits and data bits in hamming code
5.1.1 Example 1:
Let us assume that the data word is the ASCII Value of A i.e.
65 hex = 41octal = 101 decimal = 1000001 binary = capital A ( ASCII )
11 10
9
8
7
6
1 0 0 p4 0 0 0
5
4
p3 1
3
2
p2 p1
Calculating parity bits ( even parity ) for the above data word:
P
P
P
P
1
2
3
4
=
=
=
=
XOR
XOR
XOR
XOR
of
of
of
of
Bits
Bits
Bits
Bits
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(
(
(
(
3,
3,
5,
9,
5, 7, 9, 11) = 1 0 0 0 1 = 0
6, 7, 10, 11) = 1 0 0 0 1 = 0
6, 7) = 0 0 0 = 0
10, 11) = 0 0 1 = 1
21
Hamming Code
The 7-bit data word is written into the memory together with the 4 parity bits as
a 11-bit composite word. Substituting the 4 parity bits in their proper positions,
we obtain the 11-bit composite word.
11 10
9
8
7
6
1 0 0 1 0 0 0
5
0
4
1
3
0
The final 11 bit hamming code that is generated from the 7 bit data word and the
4 bit parity word is = 10010000100 = 484 h = 1156 d.
The above code is now ready for transmission.
11 10
9
8
7
6
1 0 0 1 0 0 0
5
0
4
1
3
0
11 10
9
8
7
6
1 0 0 1 1 0 0
5
0
4
1
3
0
22
Hamming Code
The error can now be corrected by complementing the corresponding bit. After
correction, we get the hamming code as
11 10
9
8
7
6
1 0 0 1 0 0 0
5
0
4
1
3
0
5.1.2 Example 2:
Let us repeat the above process with another data word, but in a tabular fashion.
Let the data word be 1101101 b, which is the ASCII equivalent of lowercase M.
Changing bases, 109 d = 6D h = 155 o = 1101101 b = lowercase M = m.
Bit Positions
Generic Name
Data Word(without
parity
Calulating parity 1
Calulating parity 2
1
1
d
7
1
10 9
d6 d
5
1 0
p
4
d
4
1
d
3
1
d
2
0
p
3
d
1
1
p2 p
1
1
1
1
1
1
1
Calulating parity 3
Calulating parity 4
Data
parity)
word(with
1
1
1
1
0
0
0
0
1
1
1
0
1
1
Now, taking the above hamming code and determining the parity bits again so
that the erroneous bit can be detected and then corrected.
Bit
Position
s
1
1
1
0
Generic
Name
d
7
d
6
d
5
p
4
d
4
d
3
d
2
p
3
d
1
p
2
p
1
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23
Parit
y
chec
k
Parity
Bit
Hamming Code
Received
Data
Word
Calulatin
g parity
1
Calulatin
g parity
2
Calulatin
g parity
3
Calulatin
g parity
4
1
1
1
0
1
Fail
Pass 0
Pass 0
Fail
24
Hamming Code
Test 4 - > Error in the 8th bit of the transmitted Hamming code.
Test 5 - > Error in the 11th bit of the transmitted Hamming code.
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26
Hamming Code
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.771ns
Timing Detail:
-------------All values displayed in nanoseconds (ns)
==============================================================
==========
Timing constraint: Default path analysis
Total number of paths / destination ports: 34 / 11
----------------------------------------------------------------------Delay: 6.771ns (Levels of Logic = 4)
Source: inp<0> (PAD)
Destination: outp<1> (PAD)
Data Path: inp<0> to outp<1>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O 2 1.106 0.532 inp_0_IBUF (inp_0_IBUF)
LUT3:I0->O 2 0.612 0.383
Mxor_mux0000_xor0001_xo<1>1 (mux0000_xor0001)
LUT4:I3->O 1 0.612 0.357 outp_1_mux00001
(outp_1_OBUF)
OBUF:I->O 3.169 outp_1_OBUF (outp<1>)
---------------------------------------Total 6.771ns (5.499ns logic, 1.272ns route)
(81.2% logic, 18.8% route)
==============================================================
==========
CPU : 42.92 / 48.01 s | Elapsed : 43.00 / 48.00 s
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Hamming Code
6 . 2 Applications
The first IBM computer to use Hamming codes was the IBM Stretch
computer (model 7030), built in 1961 [LC]. A follow-on machine known as
Harvest (model 7950), built in 1962, was equipped with 22-track tape
drives that employed a (22, 16) SEC-DED code. The ECCs found on
modern machines are usually not Hamming codes, but rather are codes
devised for some logical or electrical property such as minimizing the
depth of the parity check trees, and making them all the same length.
Such codes give up Hammings simple method of determining which bit is
in error, and instead use a hardware table lookup.
Server-class computers generally have ECC at the SEC-DED level. In
the early solid state computers equipped with ECC memory, the memory
was usually in the form of eight check bits and 64 information bits. A
memory module (group of chips) might be built from, typically, nine eightbit wide chips. A word access (72 bits, including check bits) fetches eight
bits from each of these nine chips. Each chip is laid out in such a way that
the eight bits accessed for a single word are physically far apart. Thus, a
word access references 72 bits that are physically somewhat separated.
With bits interleaved in that way, if a few close together bits in the same
chip are altered, as for example by an alpha particle or cosmic ray hit, a
few words will have single-bit errors, which can be corrected.
Some larger memories incorporate a technology known as Chipkill.
This allows the computer to continue to function even if an entire memory
chip fails, for example due to loss of power to the chip.
The interleaving technique can be used in communication
applications to
correct burst errors, by interleaving the bits in time.
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Hamming Code
In modern server-class machines, Hamming ECC may be used in
different levels of cache memory, as well as in main memory. It may also
be used in non-memory areas, such as on busses.
Hamming codes can also be used for data compression allowing a
small amount of distortion (loss of information) by running the machine
backwards.
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Hamming Code
7. 2Future work
Today the Hamming ECC are used in memories and its organization
is often more complicated than simply having eight check bits and 64
information bits. Modern server memories may have 16 or 32 information
bytes (128 or 256 bits) checked as a single ECC word. Each DRAM chip
may store two, three, or four bits in physically adjacent positions.
Correspondingly, ECC is done on alphabets of four, eight, or 16 characters
a subject not discussed here. Because the DRAM chips usually come in
8- or 16-bit wide configurations, the memory module often provides more
than enough bits for the ECC function. The extra bits might be used for
other functions, such as one or two parity bits on the memory address.
This allows the memory to check that the address it receives is (probably)
the address that the CPU generated.
Turbo codes are built out of Hamming codes. Using the Hamming
code from this page, you'd have a 15x15 matrix of bits. That's 11 data
rows and 4 check rows, and 11 data columns and 4 check columns. Fill in
the (data,data) positions with data. Fill in (data, check) positions in data
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Hamming Code
rows by filling in the check bits for a 15-bit Hamming code for that row,
and fill in the (check, data) bits in data columns the same way. Now the
data bits are filled for the check rows and check columns. Fill in the
(check, check) positions by filling in the check bits for the 15-bit Hamming
code for their row. You'd get the same results for (check, check) bits if you
did the Hamming code for their column, because the value is really the
XOR of a bunch of (data, data) bits, and it's the same set of (data, data)
bits either way. You could even go hog-wild and build N-dimensional Turbo
codes, or Turbo codes with different Hamming codes in different
dimensions. Decoding Turbo codes well requires more tricks.
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Hamming Code
Source code
8.1 Hamming_encoder.v
module hamm_enc(outp,inp,reset);
parameter n=11,k=7;
output [n-1:0] outp;
input [k-1:0] inp;
input reset;
reg [n-1:0] outp;
integer i,j;
always @(inp or reset)
begin
if(reset)
outp = 0;
else
begin
i=0; j=0;
while((i<n) || (j<k))
begin
while(i==0 || i==1 || i==3 || i==7)
begin
outp[i] = 0;
i=i+1;
end
outp[i] = inp[j];
i=i+1;
j=j+1;
end
if(^(outp & 11'b101_0101_0101))
outp[0] = ~outp[0];
if(^(outp & 11'b110_0110_0110))
outp[1] = ~outp[1];
if(^(outp & 11'b000_0111_1000))
outp[3] = ~outp[3];
if(^(outp & 11'b111_1000_0000))
outp[7] = ~outp[7];
end
end
endmodule
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8.2 Hamming_decoder.v
module hamm_dec(outp,inp,reset);
parameter n=11,k=7;
output [k-1:0] outp;
input [n-1:0] inp;
input reset;
reg [k-1:0] outp;
reg r1,r2,r4,r8;
reg [3:0] r;
reg [n-1:0] IN;
integer i,j;
always @(inp or reset)
begin
if(reset)
outp=0;
else
begin
r1 = ^(inp & 11'b101_0101_0101);
r2 = ^(inp & 11'b110_0110_0110);
r4 = ^(inp & 11'b000_0111_1000);
r8 = ^(inp & 11'b111_1000_0000);
r = {r8,r4,r2,r1};
IN = inp;
IN[r-1] = ~IN[r-1];
i=0; j=0;
while((i<n) || (j<k))
begin
while(i==0 || i==1 || i==3 || i==7)
i=i+1;
outp[j]=IN[i];
i=i+1;
j=j+1;
end
end
end
endmodule
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Hamming Code
References
1. R. W. Hamming "Error Detection and Error Correction Codes" Bell
Systems Tech. Journal, vol 29, pp 147-160, April, 1950
2. Hamming Code. http://en.wikipedia.org/wiki/Hamming_code, May 2009
3. Hill, Raymond. A First Course in Coding Theory. Clarendon Press, 1986.
4. Roman, Steven. Coding and Information Theory. Springer-Verlag, 1992.
5. PETERSEN W.W and E.J.WELDON Error-correcting Codes MIT Press. 2nd
edition 1972 pp 256- 261.
6. Agrell, Erik. http://www.s2.chalmers.se/~agrell/bounds/, October 2003.
7. Lin, Shu and Costello, Daniel J., Jr. Error Control Coding: Fundamentals
and Applications. Prentice-Hall, 1983.
8. IEEE Standard Verilog Hardware Description Language, New York, 2001
9. Palnatkir S. Verilog HDL: A guide to Digital Design and synthesis.
Prentice
Hall, Engelwood Cliff, New Jersey.
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