Revision

Chapter 1
Semiconductor Diode

Atomic Theory

Atom is the smallest particle of an element

3 particles: proton, neutron and electron
Conductivity depends on # of electrons in
outermost shell.
1 electron, perfect conductor
Full electron, insulator
2n

N
Example:
Carbon (6 electron)
3

Semiconductor

Atom that contain four valence electrons

Ex: silicon (Si), germanium (Ge), and carbon (C)
Si, Ge : production of solid state components
C : production of resistors, potentiometer

Cont..
Energy
Free electron
Conduction band

Energy gap
Valence band

Heat
Energy

Hole

N-type Semiconductor

N: Negative charge of electrons

Created by adding pentavalent impurities element
[Pentavalent atom/Donor atoms (5 valence
electrons)] into pure Si, Ge base.
Result: 1 abundance electron
Pentavalent Impurities: Bismuth (Bi), Arsenic (As),
Phosphorus (Ph), Antimony (Sb)
Impurities donate weakly-bound outer electrons to
semiconductor atoms (donor atom)
Holes in N-type are called minority carriers and
electrons are the majority carriers
Fermi level lies closer to conduction band
6

Cont..

P-type Semiconductor

P: Positive charge of holes

Created by adding those trivalent impurities element
[Trivalent atoms / acceptor atoms with (3 valence
electrons)] into Si or Ge base through doping
process.
Result: create an abundance of holes
Trivalent Impurities: Boron (B), Aluminium (Al),
Gallium (Ga), Indium (In)
Impurities accept weakly-bound outer electrons
from semiconductor atoms (acceptor atom)
Hole are majority carrier while electron minority
carrier
8

Cont..

PN Junction

Is formed when half of a block of silicon is doped

half with trivalent impurity and other half with
pentavalent impurity
N region has free electrons and P region has
holes.
PN junction is the fundamental to operation of
diodes, transistors and other solid-state devices.

10

Cont..

Region with free carriers

No external voltage:

Electron in n-region wander/diffuse across into p-region

to combine with the hole
Once electron jump, n-region loss electrons and create
positive charge near junction.
P-region loss holes and create negative charge near
junction
As result, large amount of +ve and ve ion build near pn
junction (depletion region)
So, other electron have to overcomes this region in
order to migrate to p-region
Thus, no flow of charge, no current etc
11

Ideal Diode

A two-terminal device that act as switch

and can conduct current in only one
direction
N-region: cathode
P-region: anode
Forward bias

Reverse-bias

ON

OFF

12

Cont...
Small bias,
small forward
current

Causes large
increase in
current (eand holes
created),
reverse
voltage
clamped

Small reverse
saturation
current (uA),
temperature
dependent

Diode
presents a
very low
resistance

Cut-in
voltage /
diode
forward
voltage
drop 0.6
to 0.7
13

Half-Wave Rectifier

When the sinusoidal input voltage (Vin) is at the

positive cycle, the diode is forward biased and
conducts current through the load resistor.
The current produces an output voltage across
the load RL, which has the same shape as the
positive half cycle of the input voltage.

Half-Wave Rectifier

When the practical diode model is used, the

barrier voltage must be taken into consideration.
For a silicon diode: V p( out ) V p( in ) 0.7 V

Half-wave rectifier with capacitor-input filter

Full Wave Rectifiers

Full wave rectification allows the voltage on both

the positive and negative cycle to be used.

Full wave Center Tapped Rectifier

During positive half cycle, D1 is forward biased

and D2 is reversed biased.

For the negative half cycle, D1 is reverse biased

and D2 is forward biased.

Full wave center tapped rectifier

Full wave center tapped rectifier

Diode reverse voltage (D2 shown reversebiased and D1 shown forward-biased).

Vsec
0.7 ( for silicon)
2
V
Vout sec 0.3 ( for germanium)
2

Vout

Full Wave Bridge Rectifier

Full wave bridge rectifier uses 4 diodes. At each

cycle though, only 2 diodes are active.

Ideal Model

Full Wave Bridge Rectifier

During positive cycle:

D1 and D2 are ON.

Current moves
through these 2
diodes.

Full Wave Bridge Rectifier

During negative cycle:

D3 and D4 are ON and conducting current. The

other 2 diodes are in reverse bias.

Full Wave Bridge Rectifier

During positive cycle:

Full Wave Bridge Rectifier

During negative cycle:

Rectifier Waveform Comparison

Comparison of ripple voltages for half-wave and full-wave

rectified voltages with the same filter capacitor and load
and derived from the same sinusoidal input voltage.

Diode Clipper Circuits

These circuits clip off portions of signal voltages above or

below certain limits, i.e. the circuits limit the range of the
output signal.
Such a circuit may be used to protect the input of a CMOS
logic gate against static.
Clipper circuits have the ability to clip off a portion of the
input signal without distorting the remaining part of the
alternating waveform.
There are two types of clipper circuit, namely series and
parallel.

Clippers/Limiters

Half-wave rectifier is a clipper that eliminates one

of the ac signal
Function: altering the shape of waveform, circuit
transient protection and detection
Vin(P) = 10V
Positive (diode reverse bias)
Vo(p)=100k/(100k+10k)]x10
=9.09V
Negative (diode forward bias)
Vo(p)=-0.7V
28

Clampers / DC restorers

To shift a waveform either above or below

reference voltage without distorting waveform
Purpose: add DC level to an AC signal
Build by a C, R, diode and dc voltage supply for
shifting
Time constant, = RC large enough to ensure
voltage does not discharge when through
capacitor
Good clamper, at least 10 times T of input
frequency
29

Positive Clamper
+

+ve cycle:

-ve cycle:

-Vi + Vc + Vo = 0
-Vi + Vc 5 = 0
Vc = Vi + 5 = 25

(-Vi) Vo Vc = 0
Vo = -20 25 = -45

Bipolar Junction Transistor

collector

base

emitter

31

PNP and NPN transistor

structure
P

Ic(mA)
IB(A)

IC(mA)
IB(A)

IE(mA)

Arrow shows the current flows

IE(mA)

NPN Transistor Structure

The collector is lightly doped.

The base is thin and

is lightly doped.

The emitter is heavily doped.

NPN Transistor Bias

No current flows.

The C-B junction

is reverse biased.

NPN Transistor Bias

The B-E junction

is forward biased.

Current flows.

NPN Transistor Bias

IC
Current flows
everywhere.

When both junctions

are biased....

Note that IB is smaller

than IE or IC.

IB

IE

Note: when the

switch opens, all
currents go to zero.

IC

Although IB is smaller
it controls IE and IC.

IB
Gain is something small
controlling something large
(IB is small).

IE

IC = 99 mA

The current gain from

base to collector
is called b.
IB = 1 mA

b =

99
ICmA

1IBmA

= 99

IE = 100 mA

C
P

IC = 99 mA

Kirchhoffs
current law:
IB = 1 mA

C
P

IE = I B + I C

= 1 mA + 99 mA
= 100 mA
IE = 100 mA

IC = 99 mA

In a PNP transistor,
holes flow from
emitter to collector.
IB = 1 mA
Notice the PNP
bias voltages.

C
B

IE = 100 mA

BJT symbols and conventions

Both the
input and
output
share the
base in
common

Both the
input and
output
share the
emitter in
common

Both the
input and
output
share the
Collector
in common
41

Transistors have three terminals:

Collector
Base

Emitter
Active: Always on
Ic=BIb

Transistors work in 3 regions

Saturation :Ic=Isaturation
On as a switch

Off :Ic=0
Off as a switch

Transistor as a Switch
Transistors can be used as switches.1

Transistor

Switch

Transistors can either

conduct or not conduct current.2
ie, transistors can either be on or off.2

Amplifier example:
As you see, the transistor is
biased to be always on. The input
signal is amplified by this circuit.
The frequency of output is the
same as its input, but the polarity
of the signal is inverted.

The measure of amplification is

the gain of transistor.

Example:
Input Amplitude =0.2v
Output amplitude=10v
Gain=10/0.2=50

DC load line

45

Cont..

46

1. Fixed Bias Circuit

AC output signal
AC input signal

For the DC analysis the network can be isolated from the indicated AC levels
by replacing the capacitors with an open circuit equivalent.
In addition, the DC supply VCC can be separated into two supplies (for
analysis purposes only).
47

Fixed Bias Circuit

Base-Emitter loop
Using Kirchhoff's Law:

VCC VRB VBE 0

VCC I B RB VBE 0
VCC VBE
IB
RB
48

Fixed Bias Circuit

Collector-Emitter loop
Using the current gain, beta (b):

I C bI B
Using Kirchhoff's Law:

VCC VRC VCE 0

VCC I C RC VCE 0
VCE VCC I C RC
49

Transistor Saturation
The term saturation is applied to any
system where levels have reached their
maximum values.
For a transistor operating in the saturation
region, the current is a maximum value, IC
max.
VCE = 0, transistor become short circuit.
VCC saturation
We can predict collectors
I Csat
current, ICsat:
RC

50

2. Emitter Stabilized Bias Circuit

Adding a resistor (RE) to the emitter circuit, stabilizes the bias

circuit.
(replacing the capacitors with an open circuit equivalent)

51

Emitter Stabilized Bias Circuit

Base-Emitter Loop
Using Kirchhoff's Law:

VCC I B RB VBE I E RE 0
and :
I E b 1I B
substitute in equation :
VCC I B RB VBE b 1I B RE 0
gives :
IB

VCC VBE
RB b 1RE

52

Emitter Stabilized Bias Circuit

Collector-Emitter loop
Using Kirchhoff's Law:

VCE VCC I C RC I E RE
but IC IE ,

VCE VCC I C RC RE
VE I E RE

VBC= VB - VC

VC VCE VE
VB VBE VE

53

3. Voltage Divider Bias Circuit (a)

Exact method
Step 1: replace all C by open circuit
Step 2: redraw circuit

54

Voltage Divider Bias Circuit (a)

Step 3: Thevenin equivalent circuit

RTH = R1||R2
VTH = VCC . R2
(R1+R2)

Step 4: Replace RTH

and VTH in circuit

55

Voltage Divider Bias Circuit (a)

Step 5: derive equations

Since, I E I C I B and I C bI B
I E I B b I B ( 1 b )I B
Can derive:

56

Voltage Divider Bias Circuit (b)

Approximation method: for IB very
small value due to large value of R from
Base to Ground
Check Condition: RE 10 R2 (meet)
Base and ground resistance is very high,
so IR1=IR2.

57

4. DC Bias Voltage Feedback

Bias arrangement with feedback
Stability improved by feedback from C to
B
-ve feedback connection

58

DC Bias Voltage Feedback

Base-Emitter Loop
Using Kirchhoff's Law:
VCC I B RB VBE I E RE 0
and :

I E b 1I B

substitute in equation :
VCC I'C RC I B RB VBE I E RE 0
given :
I C bI B and assume I'C I C , and I E I C
VCC bI B RC I B RB VBE b I B RE 0
Re arrange :
IB

VCC VBE
RB b RC RE

59

DC Bias Voltage Feedback

Collector-Emitter loop
Using Kirchhoff's Law:

VCE VCC I C RC RE

60

FET
Voltage-controlled device
FET is a uni-polar device depend solely on
either electron (n-channel) or hole (pelectron) conduction
FET higher input impedance, but BJTs
have higher gains.
FET less sensitive to temperature
variations and because of the
construction, they are more easily
integrated on ICs.
FET more static sensitive than BJT.

61

(a) JFET
3 terminals: gate(G), source(S) &
drain(D)
D & S are connected to n-channel (Ntype)
G connected to the p-type material

Nchannel

Pchannel

62

JFET Operation
+ve VDS applied across
the channel and set VGS
= 0 V.
Gate and source at the
same potential.
Once VDD (=VDS) is
applied, the electrons
will be drawn to the
drain terminal along
the channel, and
produce drain current,
ID.

63

JFET Operation
If

VGS = 0 and VDS is

further increased to a
more positive voltage, the
depletion zone gets so
large that it pinches off
the n-channel.

Also

known as saturation
of FET.

Voltage

increases, current
remains at IDSS
(maximum JFET current).

Can

act as a current

64

JFET Operation
As VGS (the controlling voltage) becomes more
negative:
The JFET experiences pinch-off at a lower
voltage.
ID decreases (ID < IDSS) even though VDS is
increased.
Eventually ID reaches 0 A VGS at this point
is called Vp or VGS(off).
Also note that at high levels of VDS the JFET
reaches a breakdown situation VDS(max)
ID increases uncontrollably if VDS > VDS(max).
65

JFET Characteristic
N-channel JFET
with
IDSS = 8 mA & VP =
4V

66

JFET as Variable Resistor

The region to the left of the
pinch-off point is called the
ohmic region.
The JFET can be used as a
variable resistor, where VGS
controls the drain-source
resistance (rd). As VGS
becomes more negative, the
resistance increases.
where ro is the resistance with VGS =0 V
and rd the resistance at a particular level
of VGS.

67

JFET Transfer Characteristic

The transfer characteristic of input-to-output

is not as straight forward as in a BJT.
In a BJT, indicates the relationship between
IB (input) and IC (output).
In a JFET, the relationship of VGS (input) and
ID (output) is a little more complicated:

Shockleys
Equation

68

JFET Transfer Curve

69

Plotting JFET Transfer Curve

Long way (more points better result)

Referring to the Shockleys equation, we can

use 3 steps to plot the curve.
Step 1: Solving for VGS = 0 V & ID = IDSS
Step 2: Solving for VGS = Vp (VGS(off)) & ID =
0A
Step 3: Solving for VGS = 0 V to Vp
70

Plotting JFET Transfer Curve

Short hand method

4 calculations / points are needed:

71

(b) MOSFETs
MetalOxideSemiconductor Field Effect Transistors

Types of MOSFETs
Depletion n-MOSFET

Enhancement n-MOSFET

Why MOSFETs?
Smaller in size and fewer processing steps.
72

Basic Structure of MOSFETs

Depletion n-MOSFET
S

Enhancement n-MOSFET
S

SiO2

SiO2
n

n
p-substrate

n
p-substrate

Enhancement type does not has channel

connecting drain and source.
73

(b) Depletion-type MOSFET

P-type portion formed from a silicon base
as substrate
S and D connected through metallic
contacts to
n-doped regions
G connected to a metal contact surface but
insulated from n-channel by silicon dioxide
layer (SiO2)
More higher input resistance than JFET

74

Physical Operation of D-MOSFETs

Depletion n-MOSFET
ID=IS

+
n

p-substrate

VDD

For example: gate-to-source voltage (VGS) is set to

zero and voltage is applied across the drain-to source
terminals (VDS)
75

D-MOSFET Construction

76

Depletion n-MOSFET
The gate is insulated from the channel. Therefore, the gate

current is negligible regardless of the gate-to-source

voltage.

The channel has finite conductivity and majority carriers

(electrons) allows the current to flow from drain to source

via the channel when the drain is at a positive potential
with respect to the source.

This make it as a normally ON device.

By controlling the voltage at gate terminal, this enables us

to control the current in the device until the gate voltage

reaches a value at which the device will turns OFF.

Actually voltage at the gate controls the concentration of

the majority carriers that also determines the width of the

channel.

77

Depletion n-MOSFET

The smaller the channel width, the smaller is the

drain current and more negative the gate-tosource (VGS) voltage is.

The channel width disappears when VGS reaches

its pinch-off value and enters the cut-off mode.

The decrease in the width of the channel is

viewed as the depletion in the majority-charge
carriers in the channel.

It is for this reason, MOSFET is said to operate in

the depletion mode when VGS is less than or
equal to zero. When VGS is larger than zero, it is
said to be operating as in enhancement mode.

78

D-MOSFET Characteristic

79

D-MOSFET Operation

Basic curve similar to JFET.

Positive VGS at G will draw additional
electrons from p-type substrate due to
reverse leakage current and establish new
carriers through collisions
Drain current increase
Thus, region of +ve gate voltage on G as
enhancement region
Region between cut-off and saturation level
of IDSS as depletion region
80

(c) Enhancement-type MOSFET

The Drain (D) and Source (S) connect to
the to n-doped regions.
The Gate (G) connects to the p-doped
substrate via a thin insulating layer of
SiO2
There is no channel
The n-doped material lies on a p-doped
substrate that may have an additional
terminal connection called the Substrate
(SS)

81

E-MOSFET Construction

82

Physical Operation of MOSFETs

Enhancement n-MOSFET
VGS

ID

IS = ID

+ + G+ +
+
+

+
n

e
e

p-substrate

VDS

n
_

For example: Both (VGS) and (VDS) is set to certain

value > 0.
83

Enhancement n-MOSFET

Voltage at gate controls the flow of current between drain

and source.

When VGS = 0, no current flows between drain and source

MOSFETs is said to be in cut-off mode.

Transistor will start to activate at its threshold voltage. VT =

the value of VGS where the drain current just begins to flow.
Typical values = 0.3 to 0.8 volts.

When VGS> 0, holes will repels under the gate and attracts
electrons from source and drain. This will create a channel
connecting both terminals.

At VGS= VT the n-channel under the gate will complete the

circuit. This channel is also called inversion layer.
84

Enhancement n-MOSFET

As VGS is increased slowly above threshold, a deeper

channel is induced to allow more current to flow.

For a small value of VDS and a constant VGS, current

will flow from drain to source (ID = IS) proportionally
to VDS. At this point, MOSFETs acting in triode region
and behave like a voltage-controlled resistors.

Further increase in VDS, will create a voltage drop

across the channel and cause a taper in the channel
depth. As the gate-channel voltage drops to VT,
channel pinches off. This leads to saturation and no
further increase in current for increase in VDS.

85

E-MOSFET Characteristic

VGS is positive va

86

E-MOSFET Characteristic

enhancement type MOSFET operates only

in the enhancement mode

VGS is always positive

As VGS increases, ID increases

As VGS is kept constant and VDS is

increased, then ID saturates (IDSS) and the
saturation level, VDSsat is reached

87

E-MOSFET Characteristic
For values of VGS less than the threshold
level VT, the drain current of an
enhancement-type MOSFET is 0 mA.
For VGS > VT,

88

E-MOSFET Characteristic

89

DC Analysis of FET
The general relationships that can be
applied to the DC analysis of all FET are:

For JFETs and D-MOSFET:

For E-MOSFET:

FET DC Biasing
We will discuss on the following types of
biasing:
1)

Fixed-bias

2)

Self-bias

3)

Voltage Divider

1. Fixed-bias configuration

Open circuit all

capacitors

Short circuit the

gate resistor,
RG, since IG =
0A.

Fixed-bias configuration
Method 1: Mathematical
approach

Using KVL equation:

Drain current, ID is now controlled

by Shockley's equation:

Fixed-bias configuration
Method 1: Mathematical approach

point:

At the output

Fixed-bias configuration
Method 2: Graphical method

Step 1:Plot the transfer curve using

Shockleys equation. 3 points are
already sufficient.

Fixed-bias configuration
Method 2: Graphical method

Step 2: Draw a vertical line when VGSQ

= -VGG

2. Self-bias configuration
Eliminates the need for two DC supplies
Controlling gate-to-source voltage
determine by voltage across RS

Self-bias configuration
Method 1: Mathematical
Approach
Open circuit all capacitor,
short circuit gate resistor.
Using KVL:

Self-bias configuration
Method 1: Mathematical
Approach
Drain current can be derived
from Shockley's equation,
and substitute the VGS value:

Self-bias configuration
Method 2: Graphical Approach
Step 1: Draw the transfer curve.
Step 2: Draw DC load line.
Step 3: Find VGSQ and IDQ

3. Voltage-divider Biasing
Open circuits for all Capacitor

Voltage-divider Biasing
Using KCL:

And using KVL:

Voltage-divider Biasing
Plotting transfer characteristic curve and DC
load line:
Using the same Shockley's equation to
plot the characteristic curve (3 points is
sufficient).
For DC load line, plot using these 2 points:

Voltage-divider Biasing
Once the Q points is found, the rest of the
values can be calculated using:

Introduction

Op-amp has two input terminals.

Symbol:

The negative terminal is known as an

inverting input, V-.
The positive terminal is known as noninverting input, V+.
The third terminal is known as the output.
105

Basic Configuration of Op-Amp

Configuration

Non-inverting
Inverting
Unity-Follower
Summing

Its constructed using negative feedback

to stabilize the gain.

106

Ideal Op-Amp Characteristics

Open loop gain, A =

Input impedance, Zi =
Output impedance, Zo = 0
Bandwidth =
Explanation:

Zi is infinite, the signal current flow into the

inverting and non-inverting terminals are both zero.
Therefore, voltage between output and input will
always equal to Vo = (V+) (V-).
Zo is supposed to be zero.
The bandwidth is because an ideal op-amp has a
gain A that remains constant at zero frequency to
infinite frequency.
It shows that ideal op-amp will amplifiers signals of
any frequency with equal gain.
107

Non-Ideal Op-Amp Characteristics

High voltage gain ~ 106
High input impedance ~ 2 M
Low output impedance ~ 75
Explanation.

Non ideal op-amp will limit the range of

operation.

108

Non-inverting Amplifier

Vf creates voltage divider circuit that

reduces Vo

Virtual ground concept, Vf = Vi

R1
Vf
Vo
R1 R f

Rf
Vo
A
1
Vi
R1

Vf

109

Inverting Amplifier

current through Ri and Rf is equal

I1 I f
I1

V1
R1

If

Vo
Rf

V
V1
o
R1
Rf

Rf
Vo
A

V1
R1
110

Unity-Follower

Gain, A = 1

Vo V1

111

Summing Amplifier
Rf
Rf
Rf
Vo V1
V2
V3
R2
R3
R1