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BEE-307 VLSI DESIGN LAB

Format & Language (5%)

Originality (5%)
Conclusion - Knowledge Applied (5%)
Discussion - Results Analysis (5%)
Results (5%)
Participation and management (5%)
Workstation safety, health, societal and cultural
(5%)

Matric
No.

143013923

Nur
Farah
Diana
Binti
Abd
Rahm

142913282

Moua
wia
Moha
mmad

Circuit Construction/ Demonstration/ Simulation

(5%)

Nam
e

TOTAL
(10%)
TOTAL
(40%)
No
.

Report (30%)
Practical (15%)

Lab No

SCHOOL OF ENGINEERING AND TECHNOLOGY INFRASTRUCTURE

BACHELOR OF ELECTRONICS ENGINEERING (HONS)
Subject name: VLSI DESIGN LAB
Subject code: BEE 307
Name of the Lecturer: Jebashini ponnian
Experiment
1

Design an inverter circuit and simulate the design

using ASIC Design Kit (ADK3) for Mentor
Graphics
Design a NAND gate circuit and simulate the
design using ASIC Design Kit (ADK3) for Mentor
Graphics.
Design a NOR gate circuit and simulate the design
using ASIC Design Kit (ADK3) for Mentor
Graphics.
Design a half adder circuit and simulate the
design using ASIC Design Kit (ADK3) for Mentor
Graphics.
Design a full adder circuit and simulate the design
using ASIC Design Kit (ADK3) for Mentor
Graphics.
Design a 2-1 multiplexer circuit and simulate the
design using ASIC Design Kit (ADK3) for Mentor
Graphics.
Design Project

Lab No. 3

Objective:
To design the NOR gate circuit using mentor graphics software and simulate the design.

Software Required:
Mentor Graphics software

Theory:
The Logic NOR Gate or Inclusive-NOR gate is a combination of the digital logic OR
gate with that of an inverter or NOT gate connected together in series. The NOR (Not
OR) gate has an output that is normally at logic level 1 and only goes LOW to logic
level 0 when ANY of its inputs are at logic level 1. The Logic NOR Gate is the
reverse or Complementary form of the OR gate.

NOR Gate Logic/Boolean Expression:

NOR Gate Logic symbol:

NOR Gate Truth table:

A

Y (Output)

Schematic:

Figure 1. NOR gate circuit designed in Pyxis Schematic.

A CMOS NOR gate circuit uses four MOSFETs just like the NAND gate, except that it is
transistors are differently arranged. Instead of two paralleled sourcing (upper) transistors
connected to Vdd and two series-connected sinking (lower) transistors connected to
ground, the NOR gate uses two series-connected sourcing transistors and two parallelconnected sinking transistors.

NOR Symbol .

Figure 2. We can obtain this symbol by generate the Figure 1.circuit diagram, then let the
shape option as buffer. We retrieve this symbol by select it from our file name. This
symbol is basically is the NOR logic gate that already been simplified to become a
symbol. It will be used in the test bench schematic.

Test bench:

Figure 3. In this test bench schematic, dc_v_source, pulse_v_source and symbol that
generated earlier will be connected, then we will simulate this schematic to get the output
result. We add two pulse_v_source with different value of delay time, width and period.
Both pulse_v_sources positive terminal will be connected to the input A and B at the
symbol part.

Design specification:
Simulation Result

Figure 4. As we can see the output Y is giving the correct result corresponding to the
input A and B which is following the NOR truth table.

Procedure:
The connection in series of PMOSs in series (top) and the NMOSs in parallel (bottom)
with two input A,B, output Y is added as Fig.1.We create the symbol for NOR gate..
The test bench with dc_v_source where dc were changed from 1V to 1.2V, also two
pulse_v_source with pulse value of 1.2V, V1 with delay=2.1ns, width=10ns,period=20ns,
V2 with delay=1ns, width=20ns, period=40ns is added as Fig.3.Then run the simulation.

Discussion:
The truth table theory for the NOR gate is proven precise based on the simulation result
as Fig.4. The schematic design as Fig. 1 is designed accordingly to the NOR function.
When we design the NOR gate, we should know that we needed to add two PMOS
devices in series in the pull up part of the circuit since if in series, both of the transistor
need to be on to produce the output high (1) and the two NMOS devices in parallel in
the pull down section because we need only one on to produce the output low (0).
Based on test bench schematic as Fig.3, the width and period that we enter are helping us
to get the perfect simulation waveform result. At the first try, we put the exact same
width and period for both pulse_v_source for the test bench schematic, then we end up
get the wrong output result. After five time of trying, then only we manage to get the
correct output waveform simulation that are reflect accordingly to the truth table theory.

Conclusion:
From this lab, we understand how to design the NOR gate circuit using Mentor Graphics
software and also we learn the appropriate value will give us the correct result when we
simulate the design. We can see that the design of the NAND gate from the previous lab
and NOR gate is almost similar but we must not get confused because both gate are
approaching to get the output by using different kind of concept. We also learn so many
new thing on how we can design NOR gate circuit by using CMOS which is combined of
pair of PMOS and pair of NMOS in Mentor Graphics software.