Beruflich Dokumente
Kultur Dokumente
S.NO.
PAGE
1.
2.
3.
13
4.
TRANSISTOR AS A SWITCH.
17
5.
20
6.
29
7.
ASTABLE MULTIVIBRATOR.
36
8.
MONOSTABLE MULTIVIBRATOR.
40
9.
BISTABLE MULTIVIBRATOR.
43
10.
SCHMITT TRIGGER.
47
11.
51
12.
55
:
Design a RC LPF and HPF at various time constants and verify the responses
for Square wave input (choose C = 0.1f, Vi = 4 VP-P, f = 10 K Hz).
Apparatus:
1.
2.
3.
4.
5.
6.
CRO
Signal Generator
Bread board
Capacitor (0.1f)
Resistors (100, 1K, 10 K)
Connecting wires.
Circuit Diagram:
HPF:
Design / Calculations:
a) RC = T
Given T = 1/10KHz = 0.1 mSec
V1 = V / (1 + e-T/2RC) = 2.49 V
V1| =
V
1+ e
= 1.51V
2 RC
V1 V1|
%tilt =
V
2
= (2.49 1.51)/2 = 49%)
T1 = T2 = T/2
b) RC >> T
Choose RC = 10T = 1 mSec
R=
10 3
= 10K
0.1x10 6
T1 = T2 = T/2
c) RC << T
RC = 0.1 T
R=
LPF:
a) RC = T
0.1x10 4
= 100
0.1x10 6
C = 0.1f, R = 1K
V T 2 RC
1
e
= 0.49V
2
V2 =
T
e 2 RC + 1
V1 = -0.49 V
b) RC >> T
R = 10 K, C = 0.1 f
V T 2 RC
1
e
= 0.05V
2
V2 =
T
e 2 RC + 1
V1= 0.05v
c) RC << T
R = 100,
C = 0.1 f
Note:
Low Pass Filter allows the DC component of I/P signal and High Pass Filter
block the DC component of I/P Signal.
Procedure:
3. Observe the output waveform for (a) RC = T, (b) RC>>T, (c) RC>>T
4. Verify the values with theoretical calculations
Precautions:
Use two CRO probes and observe I/P & O/P waveforms simultaneously by
putting CRO on DC modes.
Result:
LPF and HPF are designed at various time constants and the responses for
square wave input is observed & hence plotted.
Questions:
1. When HP-RC circuit is used as Differentiator?
2. Draw the responses of HPF to step, pulse, ramp inputs?
3. Draw the responses of LPF to step, pulse, ramp inputs?
4. Define % tilt and rise time?
5. When LP-RC circuit is used as integrator?
6. Why noise immunity is more in integrator than differentiator?
7. Why HPF blocks the DC signal?
8. Define 1db?
9. What is meant by linear wave shaping?
10. Write the formula for rise time tr?
Signal Generator.
Bread board
Connecting patch cards.
CRO
DC power supply (dual)
Resistors (1 K, 10K)
Diodes (1N4007)
Clipping circuits basically limit the amplitude of the input signal either below
or above certain voltage level. They are referred to as Voltage limiters, Amplitude
selectors or Slicers. A clipping circuit is one, in which a small section of input
waveform is missing or cut or truncated at the out put section.
Clipping circuits are classified based on the position of Diode.
1.Series Diode Clipper
2.Shunt Diode Clipper
Procedure:
1.
2.
3.
4.
5.
6.
Circuit Diagram
Circuit diagram
Circuit Diagrams
Transfer Characteristics
Result: Different types of clipping circuits have been studied and observed the
responses for various combinations of VR and clipping diodes.
Questions:
Apparatus:
1.
2.
3.
4.
5.
6.
7.
8.
Signal Generator.
Bread board
Connecting patch cards.
CRO
DC power supply (dual)
Resistors ( 100 K )
Diodes (1N4007)
Capacitor (0.1f)
Theory:
Procedure:
1. Connect the circuit as shown in fig.1.
2. Apply a Sine wave of 10VP-P, 1KHz at the input terminals with the help of
Signal Generator.
3. Observe the I/P & O/P waveforms of CRO and plot the waveforms and
mark the values with VR = 2 V, 3V
4. O/P is taken across the load RL.
-5V
C1
V1
10V
7.07V_rms
1000Hz
0Deg
V0
0.1uF
D1
1N4007GP
R1
100kohm
0.5V
-
-9.5V
C1
V1
10V
7.07V_rms
1000Hz
0Deg
V0
0.1uF
D1
R1
100kohm
9.5V
5V
1N4007GP
-0.5V
V0
C1
V1
10V
7.07V_rms
1000Hz
0Deg
0.1uF
1N4007GP
D1
R1
100kohm
V2
2V
-15V
-6.5V
-11.5V
Circuit diagram
Result:
Different types of clamping circuits are studied and observed the response
for different combinations of VR and diodes.
Questions:
1.What are the applications of clamping circuits?
2.What is the synchronized clamping?
3.Why is a clamper called a dc inserter?
4.What is clamping circuit theorem. How dose the modified clamping
Circuit theorem differs from this?
5. Differentiate ve clamping circuit from +ve clamping circuits in the
above circuits?
6. Describe the charging and discharging of a capacitor is each circuit?
7. What is the function of capacitor?
8. What are the effects of diode characteristics on the output of the
Clamper?
TRANSISTOR AS A SWITCH
Aim:
Design Transistor to act as a Switch and verify the operation. Choose VCC =
10V, ICmax = 10 mA, hfe = 50, VCESat = 0.2, Vin = 4Vp-p, VBESat = 0.6 V
Apparatus:
1.
2.
3.
4.
5.
6.
7.
Theory:
When the I/P voltage Vi is negative or zero, transistor is cut-off and no current
flows through Rc hence V0 VCC when I/P Voltage Vi jumps to positive voltage,
transistor will be driven into saturation. Then
V0 = Vcc ICRC VCESat
Design procedure:
When Q is ON RC =
VCC VCESat
I C max
= (10-0.2) / 10 mA
= 1K
IB ICmax / hfe
10mA / 50
IB 0.2 mA
To keep transistor
Ibmin = 0.2mA
remain
in
ON,
IB
should
be
greater
than
Circuit diagram:
Procedure:
1. Connect the circuit as shown in figure.
2. Apply the Square wave 4 Vp-p frequency of 1 KHz
3. Observe the waveforms at Collector and Base and plot it.
Precautions:
1. When you are measuring O/P waveform at collector and base, keep the
CRO in DC mode.
2. When you are measuring VBE Sat, VCE Sat keep volts/div switch at either 0.2
or 0.5 position.
3. When you are applying the square wave see that there is no DC voltage in
that. This can be checked by CRO in either AC or DC mode, there should
not be any jumps/distortion in waveform on the screen.
Expectedwaveforms:
Result:
Transistor as a switch has been designed and O/P waveforms are observed.
Questions:
1.
2.
3.
4.
5.
6.
LOGIC GATES
Aim: 1) Study of logic gates using ICs & discrete components.
2) Realization of basic gates using NAND & NOR gates (Universal gates).
Apparatus:
1.
GATE
NAND
IC 7400
SYMBOL
INPUTS
C= A B
A
B
2.
NOR
IC 7402
AND
IC 7408
A
B
C= A + B
3.
OUTPUT
C=AB
4.
OR
IC 7432
NOT
C=A+B
5.
C= A
IC 7404
6.
EX-OR
IC 7486
A
B
OR GATE
C=A
AND GATE
AB
NAND GATE
Fig (2.1)
REALIZATION USING NAND GATE:
NOT GATE:
A
AND GATE:
AB
AB
B
OR GATE:
A
A
A+B
NOR GATE:
A+B
A+B
Fig (2.2)
REALIZATION OF BASIC EX-OR GATE USING NAND & NOR GATE:
BASIC CONFIGURATION OF EX-OR GATE:
AB
A
B
AB
C= AB + A B
A+B
C = AB + A B
B
B
A+B
EX-OR
OR USING ONLY NOR GATES:
AND GATE:
OR GATE:
NOT GATE:
NAND GATE:
NOR GATE
Procedure:
f = A BC + A B C + AB C
5. Explain the operation of NAND gate when realized using discrete components.
6. In what regions does the transistor is operated such that it behaves like a
Switch.
7. What are the logic low and High levels of TTL ICs and CMOS ICs.
8. Compare TTL logic family with CMOS family.
9. Which logic family is called fastest and which logic family is called low power
dissipated.
10. Explain the operation of OR, NOR gates when realized using discrete
Components
11. Why the transistor operates as NOT gate.
FLIP FLOPS
Aim: To Construct different types of Flip Flops and verify their truth tables.
Apparatus: 1. Flip Flop experiment kit
2. Connecting Patch chords.
RS FLIP-FLOP BASIC VERSION:
Q
S
Fig (1.a)
TRUTH TABLE FOR RS FLIP FLOP:
Inputs
Outputs
Indeterminate
Q0
(Previous state)
CLK
Q
R
Fig (1.b)
SYMBOL:
R
Q
FF
CLK
Q
S
Inputs
Outputs
CLK
Q0
Indeterminate
state
SD
CP
16
15
FF
7476
14
CD
3
7
SD
CP
12
11
FF
7476
10
CD
Fig (1.c) 8
TRUTH TABLE FOR JK-FLIP FLOP (IC 7476); -
SD
Preset
CD
Clear
OUTPUTS
Clock
H*
H*
Q0
Q0
TOGGLE
Q0
Q0
*Unstable condition.
It will not remain
after Cn and Pn inputs
return
to
their
inactive (high) state
CLK
FF
Q
FF
CLK
SD
Q
CP
FF
7476
CLK
CD
INPUTS
OUTPUTS
Preset
Clear
Clock
Q0
Q0
Q
FF
Q
SD
Q
FF
CLK
CP
K
T-FLIP
FLOP
USING JK
CD
INPUTS
OUTPUTS
Preset
Clear
Clock
TOGGLE
H
TOGGLE
Procedure:
Result:
Questions:
1.Difference between latch and flip-flop.
ASTABLE MULTIVIBRATOR
Aim :To desian Astable Multivibrator to generate a Square wave of 1KHz frequency.
Choose C = 1nf, 10nf, 100nf.
Apparatus :
1.
2.
3.
4.
5.
1 no
1 no
each 2 nos
3 nos
2 nos
Circuit diagram :
Theory:
The astable circuit has two quasi-stable states. Without external triggering
signal the astable configuration will make successive transitions from one quasistable state to the other. The astable circuit is an oscillator. It is also called as free
running multivibrator and is used to generate Square Wave. Since it does not
require triggering signal, fast switching is possible.
Design :
= 1.38 RC
10 3
= 72.4 K (when c=10nf)
1.38 x10 x10 9
R = 7.24K
(when c=100nf)
RC 1K
Procedure:
Expected Waveforms:
Result :
An Astable Multivibrator is designed, the waveforms are observed and
verified the results theoretically.
Questions:
MONOSTABLE MULTIVIBRATOR
Aim : To design a monostable multivibrator for the Pulse width of 0.03mSec.
Apparatus:
Resistors(10k,1k,43.2k,100k)-2nos,2nos,1no,1no.
Capacitors(0.047f)-2nos
Diodes(1N4007)-1no.
Transistors(BC107)-2nos.
Function Generator.
CRO.
Regulated Power Supply.
Connecting wires.
Circuit diagram :
Theory:
The monostable circuit has one permanently stable and one quasi-stable
state. In the monostable configuration, a triggering signal is required to induce a
transition from the stable state to the quasi-stable state. The circuit remains in its
quasi-stable for a time equal to RC time constant of the circuit. It returns from the
quasi-stable state to its stable state without any external triggering pulse. It is also
called as one-shot a single-cycle, a single step circuit or a univibrator.
Design :
To design a monostable multivibrator for the Pulse width of 0.03mSec.
Choose ICmax = 15mA, VCC = 15V, VBB = 15V, R1 = 10K.
T = ln 2
T = 0.69 RC
Choose C = 10nf
0.3 x 10-3Sec = 0.69 x R x 10 x 10-9
R = 43.47 K
RC =
VCC VCESat
I C max
V BBR1 VCESat R2
+
R1 + R2 R1 + R2
-1.18 =
15 R1 + 0.2 R2
; given R1 = 10K
R1 + R 2
R2 = 100K
Procedure:
1. Switch ON the trainer kit and observe power indication.
2. Wire the circuit as shown in the circuit diagram.
3. Calculate the pulse width (T) of the Monostable O/P with the selected
values of R & C on the CRO. See that CRO is in DC mode.
4. Select the triggering pulse such that the frequency is less than 1/T
5. Apply the triggering input to the circuit and to the CROs channel 1 .
Connect the CRO channei-2 to the collector and base of the
TransisterQ1&Q2..
6. Adjust the triggering pulse frequency to get stable pulse on the CRO and
now measure the pulse width and verify with the theoretical value.
7. Obtain waveforms at different points like VB1, VB2, VC1 & VC2.
Result :
A collector coupled Monostable Multivinbrator is designed, the waveforms
are observed and verified the results theoretically.
Questions:1.
2.
3.
4.
5.
6.
7.
8.
BISTABLE MULTIVIBRATOR
Aim:
stable Multivibrator circuit and verify the operation.
a) Design the Bi-stable
b) Obtain the resolving time of Bi-stable
Bi stable Multivibrator and verify
theoretically. Choose R1 = 10K, C = 0.3f, VCE Sat = 0.2V, ICmax = 15mA,
VCC = 15V,
VBB = 15V, VB1 = -1.2V
Apparatus:
1.
2.
3.
4.
5.
6.
7.
8.
Resistors(1k,10k,100k)-5nos,2nos,2nos.
Resistors(1k,10k,100k)
Capacitors(0.001f,0.33f)
Capacitors(0.001f,0.33f)-2nos,3nos.
Diodes(1N4007)
Diodes(1N4007)-3nos.
Transistors(BC107)
Transistors(BC107)-2nos.
Function Generator
Regulated Power Supply
CRO
Connecting wires.
Circuit diagram:
Theory:
A Bistable circuit is one which can exist indefinitely in either of two stable
states and which can be induced to make an abrupt transition from one state to the
other by means of external excitation. The Bistable circuit is also called as Bistable
multivibrator, Eccles jordon circuit, Trigger circuit, Scale-of-2 toggle circuit, FlipFlop & Binary.
A bistable multivibratior is used in a many digital operations such as counting and
the storing of binary information. It is also used in the generation and processing of
pulse-type waveform. They can be used to control digital circuits and as frequency
dividers .
There are two outputs available which are complements of one another. i.e.
when one output is high the other is low and vice versa .
Design :
RC =
VCC VCESat
I C max
15 x10 + 0.2 R2
;
10 + R 2
VB1 =
V BBR1 VCESat R2
+
R1 + R2 R1 + R2
R2 =100K
10 + 100K
R1 + R2
= 55KHz
=
2CR1 R 2
2x0.3x106 x10Kx100K
Procedure:
1. Switch ON the system and observe for the power LED indication.
2. Apply two Square waves with same frequency or different frequency at
terminals T1 & T2. You may observe symmetrical or Asymmetrical square
waves respectively. Observe both I/P & O/P waveforms on CRO.
3. Set the I/P frequency at 500hz.
4. Until you get a 500Hz at the O/P, increase the trigger I/P amplitude, note
down the I/P amplitude, this is the minimum pulse step required for trigger
the bi-stable Multivibrator with the given circuit parameters.
5. Now slowly increase the frequency and at one particular frequency the
circuit does not respond and the output disappears. Just lesser than this
frequency, the circuit again responds, this is the maximum allowable
frequency.
6 Sketch the O/P waveforms. Sample O/P waveforms are as shown in
figure
Expected waveforms:
Vt Trigger Input
Result:
Questions: 1.
2.
3.
4.
5.
6.
7.
8.
SCHMITT TRIGGER
Aim:(a)
(b)
(c)
Apparatus:
Bread board
Function Generator
Regulated Power Supply
C.R.O
Connecting wires
Resistors(1k,3.3k,15k,2.2k,4.7k)-2nos,1no.
Capacitors(10f,1f)-1no,1no.
Transistors(BC107)-2nos.
Circuit diagram:
Procedure:(1)
(2)
(3)
(4)
Observations:-
With Re = 480ohms
DC
UTP = 2.9V
LTP = 1.8V
VH = UTP LTP
AC
UTP = 3V
LTP = 2V
VH = UTP LTP
VCC R2
;
RC1 + R1 + R2
Rb =
VEN = (V - VBE2) *
R2 ( RC1 + R1 )
RC1 + R1 + R2
VCC = 12V
Re (hFE + 1)
Rb + Re (hFE + 1)
(Accurate value)
V1 = VEN + Vr1
V2 calculation:
a =
R2
R1 + R2
Re = Re(1+
V2 = VBE1 +
R =
RC1 ( R1 + R2 )
;
RC1 + R1 + R2
1
);
hFE
Re '+ Rs / hFE
(V - Vr2)
a R + Re '
(or) V2 = VBE1 +
Re
(V Vr2)
aR + Re
Expected Waveforms:
VBE = 0.6V
Vr = 0.5V
(approximately)
Result: Schmitt Trigger circuit has designed and the square wave is
observed from the sine wave.
Questions:
1. What are the applications of Schmitt Trigger?
2. Define hysteresis action?
3. Why is Schmitt Trigger called a squaring circuit?
4. What is UTP?
5. What is LTP?
6. What is the difference between a Binary and Schmitt Trigger?
UJT (2N2646)
Capacitor
Resistors
C.R.O
Regulated Power Supply
Bread board.
Theory:
Circuit Diagram:
Theoretical Values:
We have
Vb1=iRb1.
Vbb
12
But i=
=
=0.0082A
Rb1 + Rb 2
470 + 1k
Vbb
12
* Rb1 =
* 470 =3.84v
Vb1=
Rb1 + Rb 2
470 + 1k
Rb1
=
* Vbb
Rb1 + Rb 2
Rb1
470
Intrinsic Standoff Ratio =
=
=0.32.
Rb1 + Rb 2 470 + 1k
Emitter Voltage Ve= V+Vb1
= 0.7+3.84=4.54v
1
f=
RC log(1 /(1 n))
1
=
33k * 0.1 *10^ 6 log(1 /(1 0.32))
= 1.81kHz.
Procedure:(1)
(2)
(3)
(4)
(5)
(6)
ModelWaveforms:
Observations:Vb1 = 3.84v
= 0.32
Ve = 4.54v
f = 1.81kHz.
Result: The UJT Relaxation Oscillator has studied.Theoretical values are compared
with the practical values.
Transistors
Capacitors
Resistors
C.R.O
Regulated Power Supply
Bread board.
Connecting Wires
Diode
Theory:
Circuit Diagram:
VCC
20V
D1
DIODE_VIRTUAL
C2
R1
1k?
C1
0.001F
V1
1kHz
5V
R2
1k?
0.0F
U2
U1
BD135
BD135
C3
0.001F
R3
1k?
VEE
-12V
Procedure:-
(1)
(2)
(3)
(4)
ModelWaveforms:
Observations:-
Ts=
Tr=