EE 5311 Digital IC Design: Assignment 1

Extraction of model parameters from SPICE simulations

1. Simulate the ID vs VDS characteristics for various values of VGS for a minimum sized nMOS transistor
(W = 0.36m, L = 0.18m). Vary VGS from 0.2V to 1.8V and VDS from 0 to 1.8V in steps of 0.2V. Obtain
these characteristics for VSB = 0V and VSB = 1V.
(a) Estimate the level 1 model parameters (VT , , Kn and ) using the characteristic for VGS equal to
0.6V and 0.8V. [Hint: Use the current equation for saturation region along with the drain current
values from the characteristics to solve for the parameters.]
(b) Plot the ID vs VDS characteristics using the level 1 model parameters. (Use the .MODEL command in SPICE. For example for an nMOS transistor, it is .MODEL nfet1 NMOS (LEVEL=1 KP=xx
VT0=xx LAMBDA=xx GAMMA=xx PHI=0.6) )
(c) Tabulate the error in the current at VDS = 1.8V obtained in (b) for various values of VGS and explain
the results.
(d) Estimate the level-1 model parameters and the parameters (VT , , Kn and ) with the model including velocity saturation (assume VDsat = 0.35 V) using the characteristic for VGS equal to 1.6V
and 1.8V. Which one of these models is better for this operating region?
(e) Estimate the current ID at VDS = 1.8V for various values of VGS using the parameters extracted in
part (d) with the model including velocity saturation. Also tabulate the error in this case.
2. Redo question 1 for a minimum size PMOS transistor. Vary VGS in the range -0.2V to -1.8V and VDS
in the range 0V to -1.8V in steps of -0.2V. Use VSB = 0V and VSB = 1V. Assume |VDsat | = 0.6 V for
velocity saturation model.
RC equivalent model for transistor
3. (a) Create an RC equivalent model for minimum size NMOS transistor using the level 1 model parameters extracted in 1(a). Compare the propagation delay and fall time using the RC model against
the values obtained using SPICE simulations for an input rise time of 10ps and various load capacitance values (0.5fF, 1fF, 2fF, 5fF and 10 fF). [Hint. Use suitable equations to create the RC model
and its propagation delay and fall time. For SPICE simulations, consider an NMOS transitor with
drain connected to the load capacitor which is initially charged to 1.8V].
(b) Create another RC equivalent model for minimum size NMOS transistor using the model including velocity saturation and the parameters extracted in 1(d). Compare the propagation delay and
fall time using this RC model against the values obtained using SPICE simulations for an input rise
time of 10ps and various load capacitance values (0.5fF, 1fF, 2fF, 5fF and 10 fF).
(c) Which one of these RC models is better for timing?
4. Redo question 3 for a minimum size PMOS transistor. Compare the propagation delay and rise time
using the RC model against the values obtained using SPICE simulations. [Hint. For SPICE simulations,
consider a PMOS transitor with drain connected to the load capacitor which is initially uncharged].