Beruflich Dokumente
Kultur Dokumente
abs(frequency-60) > 2) or
VlinAvg < 72 Volts (79 VRMS)
Sin
VCO
Frequency
Control
Cos
ADC
A
A*B
Mains
Noise
Filter
Phase
PI
Controller
Phase
Detectors
A
A*B
B
Noise
Filter
VlineAvg
The first reset condition accomplishes the antiislanding function when the Inverter is supplying
power to the grid, and the second condition signals
a grid power loss when in standby. The sine output
of the VCO is used to switch synchronous rectifiers
used to transfer power between the grid and the
backup system when a backup battery is present.
Backup systems require transferring power in either
direction to account for load phase shift (motors)
and battery charging, so the use of synchronously
switched rectifiers is required.
Vcp
First Stage
Tsample=40 usec
zipd
SUM2
A5
ZDELAY
Z - 1
zopd
X15
K1 = b0
K2 = 1
X13
K1 = a*gain
K2 = 1
zi10
K1
SUM2
2
K1
zo10
X5
K1 = -a2
K2 = -a1
V7
unknown
X14
K1 = b1
K2 = b2
zi32
Z - 1
A6
ZDELAY
tsample = {T}
ic = 0
zo32
Table 1, Parameters
Parameters
gain=.1
Radix=13
onee=2^Radix; sets quantizing levels
T=1m
Tsc=40u
Fc=37.1; adjust for minimum at 120 Hz
DR=-.5148;pole real part
DI=.9424;pole imaginary part
NR=0; zero real part
NI=3.205; zero imaginary part
BW=2*3.14159*Fc
K2
SUM2
SUM2
K2
A7
ZDELAY
tsample = {T}
ic = 0
K2
SUM2
Z - 1
K1
K2
K1
K1
K2
X12
SUM2
K1 = .01
K2 = .99
ph
ci
K1
A1
ZDELAY
tsample = 40u
ic = 8192
K1
SUM2
K1
SUM2
V1
K2
zos
Z^-1
k2
Z^-1
frequency
void vco(void)
{
si= (long)((((long)freq*zoc)>>13)*2684) >> 13 ;
zis=si+zos;
ci = (long)((((long)freq*zis)>>13)*2684) >> 13;
zic=zoc-ci;
zoc=zic;
zos=zis;
if(zos > 8192) {
zos = 8192;
zoc=0;
}
}
v14
v(ph)
v7
Frequency
59.0
Frequency
zif
zic
K2
A3
ZDELAY
tsample = 1m
ic = {ic}
zof
Z^-1
A2
ZDELAY
tsample = 40u
ic = 0
Figure 4, VCO
Plot1
frequency in Hertz
ph
(v(k)*v(zoc)*{Tsc}+.5)
SUM2
K2
X9
SUM2
K1 = -gain
K2 = Wcn*T
X8
SUM2
K1 = -gain
K2 = .9995
K1
B2
Voltage
K2
zoc
X2
SUM2
K1 = 1
K2 = 1
si
SUM2
B1
Voltage
X1
SUM2
K1 = -1
K2 = 1
zis
(v(k)*v(zis)*{Tsc}+.5)
1
2
55.0
Vavg Line
51.0
Phase
3
47.0
43.0
Sync
References:
[1] Phaselock Techniques, Floyd M. Gardner
[2] Downloads of the detailed design are
available at www.intusoft.com/DigitalPLL.zip.