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Part - 3

ADDRESSING MODES OF
Fixed point DSPs (TMS320C54X series)

What is Addressing modes?


Addressing modes are the different ways by which the
operand (data) from the memory can be accessed
(Read and Write) and given to CPU for processing.
The operand (data) access is mainly from Data
Memory (DM).
Some times the operand (data) access is from
Program Memory (PM).

Types of Addressing modes


Common Addressing modes:

Specific Addressing modes:

Immediate Addressing mode Register Addressing mode


Direct addressing mode
Two operand/Dual addressing

Indirect addressing mode


General Indirect
addressing mode

mode
Parallel addressing mode

Absolute addressing mode

Indexed addressing mode Accumulator addressing mode


Circular addressing mode

Bit-reversed addressing
mode
MMREG addressing mode
Stack addressing mode

Assembly Instruction basics


Instruction word (IW)/ Program word contains two fields
opcode and operand.
The syntax of any Instruction word(IW) /Assembly instruction is
opcode src,dst.
Opcode specifies the type of operation to be performed with the

operand. e.g. - ADD, SUB, MPY, LD, ST etc.


The operand field specifies the source (src) & destination (dst).
src specifies the location of the source operand for processing
and dst specifies the destination of the processed data that is to
be stored.
If the architecture has only one accumulator dst is not specified
If there are more than one accumulators dst is mandatory

Immediate Addressing mode

The only addressing mode where the operand is available in


Program memory (PM)
The operand is stored along with opcode in PM.
Used to load up to 16-bit constants in various registers.
The syntax for immediate addressing mode is the symbol # followed
by the operand
ADD #10h,A
(opcode src,dst)
In processors the IW is one word.
e.g. In 16-bit DSP the IW is 16-bits.
IW 16 bits
Opcode (8 MSB) Operand (8 LSB)

Normally half of the IW is assigned for opcode (MSB) and remaining


half of the IW is assigned for operand (LSB).
If the opcode and operand fit in to one word, then those instructions
are called one word instructions.
If the opcode and operand occupies more than one word, then those
instructions are called two word instructions.

Types of Immediate Addressing mode

Short Immediate addressing mode:


Syntax ADD #10h,A
If the operand size is 7-bits or less than 7-bits the IW is one word
Then the mode is called Short immediate addressing
The mini. and max. value of the operand is 0 127 in decimal and

0h - 7Fh in Hexadecimal
Long Immediate addressing mode:
Syntax ADD #200h,A ; SUB #1200h,B
If the operand size is greater than 7-bits the IW is two word
One word is opcode and the next word is operand
Then the mode is called Long immediate addressing
The mini. and max. value of the operand is 0 65535 in decimal
and 0h - FFFFh in Hexadecimal

Direct Addressing mode

Direct addressing mode Instruction format

8 MSBs Opcode
7th Bit - I bit, I = 0 Direct addressing
I = 1 Indirect addressing mode
7 LSBs location in a page

Direct addressing mode is based on


paging concept.
To point data page, Data page pointer
(DP) 9 bits is used.
To access a page, the page number
is to be programmed in DP.
Next the location in a page is given in
instruction along with opcode in LSB
7-bits.
For direct addressing mode No
symbol is used after the opcode in
`C54X. It will vary from processor to
processor.
Syntax:
LD #10h,DP load page no. in DP
ADD 20h,A access the data using location in a page
The data memory address 16-bits
(dma) is obtained by concatenating
7 LSBs of opcode with 9 MSBs of DP.

Direct Addressing mode with Stack pointer (SP)

Direct addressing mode in `C54x can use


stack pointer (SP) Only in `C54X
The stack pointer (SP) is 16 bit register.
The stack pointer is used to point the
starting address of a page.
Next the location in a page is given in
instruction along with opcode in LSB 7-bits.
Syntax:

LD #1000h,SP load page starting address in

SP

ADD 20h,A access the data using location in a page


The data memory address 16-bits

(dma) is obtained by adding the 7 LSB bits


as postive offset to (SP) stack pointer value.

Indirect Addressing mode

Indirect addressing mode Instruction format MSB 8 bits : Opcode

7th Bit I bit : 1 for Indirect addressing mode


6-3 MOD field : Address modification field
2-0 ARF
: Auxiliary register field

In Indirect addressing mode, the


address of the operand is stored in a
register .
In DSPs a dedicated unit ARU/DAU is
used with dedicated 8 ARs.
Any one of these ARs can be used to
point the address of the operand.
To point AR for the instruction out of
8, auxiliary register pointer (ARP) used.
For Indirect addressing mode * symbol
is used after the opcode in `C54X.
Syntax:
LD #1200h,AR2 load the address in AR2
ADD *AR2,A - access the data using the
content of AR2 as dma
The content of ARn pointed by ARP is
used as data memory address (dma).

Indirect Addressing mode cont

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a. General Indirect addressing mode


Using the current content of ARn for data memory address (dma) and if the
address displacement is 1 dma locations then it is general Indirect addressing
a) Syntax:
mode.
LD #1200h,AR2 load the address in AR2
ADD *AR2,A access the data using the content of
AR2 as dma
The content of ARn pointed by ARP is used as
data memory address (dma).
b) Syntax: Post increment
LD #1200h,AR2 load the address in AR2
ADD *AR2+,A access the data using the content
of AR2 as dma
After the access of current AR2 content, AR2 is
incremented by one by the ARAU
ADD *AR2-,A access the data using the content
of AR2 as dma
After the access of current AR2 content, AR2 is
decremented by one by the ARAU
c) Syntax: Pre increment
ADD *+AR2,A access the data using the
incremented content of AR2 as dma
After the access of incremented AR2 content, AR2 is
incremented by one by the ARAU

Indirect Addressing mode cont

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b. Indexed addressing mode


Using the current content of ARn for data memory address (dma).
If the address displacement is > 1 dma locations then Indexed addressing
mode is used.
The content of index register is used for specifying the displacement value.
If a separate index register is not available then AR0 reg. is used for indexing
Syntax:
LD #1200h,AR2 load the address in AR2
LD #10h, Indx/AR0- load the displacement value in
index register
ADD *AR2+0,A access the data using the
content of AR2 as dma
After the access of current AR2 content, AR2 is
incremented by the value in index register by
ARAU
ADD *AR2-0,A access the data using the
content of AR2 as dma
After the access of current AR2 content, AR2 is
decremented by the value in index register by
ARAU

Indirect Addressing mode cont

c. Circular addressing mode

Why circular addressing mode is required?


To access the data memory locations in a circular way many times without
any instruction overhead
The register used for circular addressing mode is BK (Block size) register
It is a memory mapped register and it specifies the size of the circular buffer.
If the size of the circular buffer is R, then N LSB bits in BK register are to be
set 1 in such a way that it satisfies the relation 2N > R

BK Block size register


TOB Top of buffer
EOB End of buffer
ARx The current auxiliary\
register

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Indirect Addressing mode cont

c. Circular addressing mode example


16 data values present in data memory starting address
1020h to 102Fh are to be accessed 10 times.
Syntax:

Instructions
LD # 0Fh, BK
LD #1020h,AR2
LD #10, AR3
loop ADD *AR2+%,A

ADD *AR2+%, A

Operation
load the buffer size in BK
load the address in AR2

load the count value in AR3


access the data using the content of
AR2 as dma
After the access of current AR2
content, AR2 is incremented and
compared with EOB by ARAU
without any instruction
access the data using the content of
AR2 as dma

Repeat the above instruction 13 times

ADD *AR2+%, A

BANZ *AR3_, loop

16th instruction
After the access of current AR2
content, AR2 is incremented by one
and it is compared with EOB, if the
comparison is true the AR2 is
automatically loaded with
TOB without any instruction.
Branch on no zero of AR3 to label loop
Decrementing of AR3 and checking its
zero value will be done by ARAU
without any instruction

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Indirect Addressing mode cont

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d. Bit-reversed addressing mode

Bit-reversed addressing enhances execution speed and program memory for


FFT algorithms that use a variety of radixes.
In this addressing mode, AR0 specifies one half of the size of the FFT.
The value contained in AR0 must be equal to 2N1, where N is an integer, and
the FFT size is 2N.
An auxiliary register points to the physical location of a data value.
When you add AR0 to the auxiliary register using bit-reversed addressing,
the address is generated in a bit-reversed fashion, with the carry bit
propagating from left to right, instead of the normal right to left
Syntax:
LD #1200h,AR2 load the address in AR2
LD #4h, Indx/AR0 - load the half the size of the FFT in index register/AR0
ADD *AR2+0B,A access the data using the content of AR2 as dma
After the access, AR0 is added to AR2 with reverse carry (rc)
propagation

Memory mapped register Access

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Different methods to access memory mapped registers:


1) Immediate addressing
LD #20h,BK
Uses program memory
For multiple access of many registers will reduce the PM size.
2) Direct addressing
LD #20h,A
LD #0h,DP
STL A, BK
For the beginning of the program update of DP=0 is not required. In the
middle of the program update of DP=0 and update of the corresponding
page number needs extra instructions.
3) Indirect addressing
LD #10h,AR2
LD #20h,A
STL A,+ar2
The user should know the address of each memory mapped register to load
it in ARn. For multiple access needs extra instructions
To reduce the extra instructions needed to access memory mapped registers
the memory mapped register addressing mode is used

Memory mapped register Addressing mode

Memory-mapped register addressing is used to modify the memory-mapped


registers without affecting either the current data-page pointer (DP) value or
the current stack-pointer (SP) value. Because DP and SP do not need to be
modified in this mode, the overhead for writing to a register is minimal.
Memory-mapped register addressing works for both direct and indirect
addressing.
Forcing the nine most significant bits (MSBs) of data-memory address to 0,
regardless of the current value of DP or SP when direct addressing is used
Using the seven LSBs of the current auxiliary register value when indirect
addressing is used
Instructions that use memory mapped register
addressing
STLM src, MMR
LDM MMR, dst
MVDM dmad, MMR
MVMD MMR, dmad
MVMM MMRx, MMRy
POPM MMR
PSHM MMR
STM #lk, MMR
4) Memory mapped register addressing
LD #20h,A
STLM A,BK

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Stack Addressing
The system stack is used to automatically store the program counter during
interrupts and subroutines
Four instructions access the stack using the stack addressing mode:
PSHD pushes a data-memory value onto the stack.
PSHM pushes a memory-mapped register onto the stack.
POPD pops a data-memory value from the stack.
POPM pops a memory-mapped register from the stack.

Register Addressing
Register addressing mode uses the CPU general purpose registers.
If the CPU of the processor has more number of general purpose registers,
then the CPU register can be used to hold operands and results.
Example: In `C3X there are eight general purpose registers R0-R7. These
register can be used for addressing.
ADD R0,R1
SUB R2,R3
MPY R1,R2

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Two operand/Dual operand Addressing mode


Dual operand addressing is used for instructions that perform
two reads
These instructions are all one word long
Operate in indirect addressing and register addressing modes
only.
Hardware Requirements for Dual operand addressing mode
Dual access RAM (DARAM) Two operand read
Two address generation units Two ARUs
Two data buses from CPU to on-chip memory To carry the
two addresses from ARU to DARAM

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Two operand/Dual operand Addressing mode cont


Dual operand addressing mode Instruction format
Xmod operand 1 address modification
Xar operand 1 auxiliary register selection
Ymod operand 2 address modification
Yar operand 2 auxiliary register selection
Syntax:
LD #1200h,AR2

- load the address in AR2

LD #1300h, AR3

- load the address in AR3

ADD *AR2, *AR3,A - access the data using the


content of AR2 and AR3 as dma, the contents
are added and result stored in Accumulator A.
ADD *AR2+, *AR3+,A - access the data using
the content of AR2 and AR3 as dma, the
contents are added and result stored in
Accumulator A. After the access the

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Two operand/Dual operand Addressing mode cont


Constrains in dual operand addressing mode
1. The auxiliary register used are AR2,AR3,AR4 and AR5 only.
2. Only four address modifications allowed.
3. The two auxiliary registers used in the instruction should not
be the same.
E.g.

ADD *AR2, *AR2, A wrong syntax

4. The content of the two auxiliary registers (dma) should not be

the same.

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Parallel Addressing mode


Parallel addressing mode is used to execute two instructions in a
single cycle .
Parallel mode is used for instructions that perform two reads or a single
read and a parallel store .
Operate in indirect addressing and register addressing modes only.
The parallel addressing mode is represented by the symbol ||
e.g. LD *ar2,A
|| ADD *ar3,B
The load, store, add, subtract, multiply and MAC instructions can be
used in parallel addressing mode.

Hardware Requirements for Dual operand addressing mode


Dual access RAM (DARAM) Two operand read
Two address generation units Two ARUs
Two data buses from CPU to on-chip memory To carry the
two addresses from ARU to DARAM

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Absolute Addressing mode


There are four types of absolute addressing:
1) dmad addressing: Data-memory address addressing (dmad)
It uses a specific value to specify an address in data space.
MVDK Smem, dmad
MVDM dmad, MMR
MVKD dmad, Smem
MVMD MMR, dmad
(Smem addressing mode type direct & indirect)
e.g. MVDK 20h, 1200h ; MVDK *ar3, 1250h
2) pmad addressing: Program-memory address addressing (pmad)
It uses a specific value to specify an address in program space.
FIRS Xmem, Ymem, pmad
MACD Smem, pmad, src
MACP Smem, pmad, src
MVDP Smem, pmad
MVPD pmad, Smem
e.g. MACD *ar4, 080h

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Absolute Addressing mode cont

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3) PA addressing: Port address addressing (PA)


It uses a specific value to specify an external I/O port address.
PORTR PA, Smem
PORTW Smem, PA
4) *(lk) addressing : Long constant (lk)
It is used with all instructions that support the use of a single data-memory

(Smem) operand.
e.g. ADD *(1000h),A

Absolute addresses are always encoded with a length of 16 bits,


so instructions that encode absolute addresses are always at
least two words in length.

Accumulator Addressing mode

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Accumulator addressing uses the accumulator as an address.


This addressing mode is used to address program memory as data.
Two instructions allow you to use the accumulator as an address:
1) READA Smem
2) WRITA Smem
READA transfers a word from a program-memory location specified

by accumulator A to a data-memory location specified by the single


data-memory(Smem) operand of the instruction.
e.g. READA *ar4
WRITA transfers a word from a data-memory location specified by
the Smem operand of the instruction to a program-memory location
specified by accumulator A.
e.g. WRITA *AR5

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End of Part-3