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//###########################################################################

// FILE: cpu_Timers_cpu01.c
// TITLE: Cpu Timers Example for F2837xS.
//
//! \addtogroup cpu01_example_list
//! <h1> CPU Timers </h1>
//!
//! This example configures CPU Timer0, 1, and 2 and increments
//! a counter each time the timer asserts an interrupt.
//!
//! \b Watch \b Variables \n
//! - CpuTimer0.InterruptCount
//! - CpuTimer1.InterruptCount
//! - CpuTimer2.InterruptCount
//
//###########################################################################
// $TI Release: F2837xS Support Library v191 $
// $Release Date: Fri Mar 11 15:58:35 CST 2016 $
// $Copyright: Copyright (C) 2014-2016 Texas Instruments Incorporated //
http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#include "F28x_Project.h"

// Device Headerfile and Examples Include File

// Prototype statements for functions found within this file.


__interrupt void cpu_timer0_isr(void);
__interrupt void cpu_timer1_isr(void);
__interrupt void cpu_timer2_isr(void);
int control=5;
int conteo=0;
//Uint32 t1;
//Uint32 t2;
//Uint32 t0;
//int
//int
//int
float
float
float
Uint32
Uint32
Uint32
Uint32

t1;
t2;
t0;
t1;
t2;
t0;

//float
//float
//float
//float

t1X;
t2X;
t0X;
t0X2;
t1X;
t2X;
t0X;
t0X2;

void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xS_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initialize GPIO:

// This example function is found in the F2837xS_Gpio.c file and


// illustrates how to set the GPIO to it's default state.
InitGpio();
GPIO_SetupPinMux(65, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(65, GPIO_OUTPUT, GPIO_PUSHPULL);
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
//
//
//
//

Initialize the PIE control registers to their default state.


The default state is all PIE interrupts disabled and flags
are cleared.
This function is found in the F2837xS_PieCtrl.c file.
InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:


IER = 0x0000;
IFR = 0x0000;
//
//
//
//
//
//

Initialize the PIE vector table with pointers to the shell Interrupt
Service Routines (ISR).
This will populate the entire table, even if the interrupt
is not used in this example. This is useful for debug purposes.
The shell ISR routines are found in F2837xS_DefaultIsr.c.
This function is found in F2837xS_PieVect.c.
InitPieVectTable();

// Interrupts that are used in this example are re-mapped to


// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.TIMER0_INT = &cpu_timer0_isr;
PieVectTable.TIMER1_INT = &cpu_timer1_isr;
//
PieVectTable.TIMER2_INT = &cpu_timer2_isr;
EDIS;
// This is needed to disable write to EALLOW protected register
s
// Step 4. Initialize the Device Peripheral. This function can be
//
found in F2837xS_CpuTimers.c
InitCpuTimers(); // For this example, only initialize the Cpu Timers
// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
// 200MHz CPU Freq, 1 second Period (in uSeconds)
ConfigCpuTimer(&CpuTimer0, 100, 100);
ConfigCpuTimer(&CpuTimer1, 100, 5);
//
ConfigCpuTimer(&CpuTimer2, 200, 1000000);
// To ensure precise timing, use write-only instructions to write to the ent
ire register. Therefore, if any
// of the configuration bits are changed in ConfigCpuTimer and InitCpuTimers
(in F2837xS_cputimervars.h), the
// below settings must also be updated.
CpuTimer0Regs.TCR.all = 0x4000; // Use write-only instruction to set TSS bit
= 0
CpuTimer1Regs.TCR.all = 0x4000; // Use write-only instruction to set TSS bit
= 0
//
CpuTimer2Regs.TCR.all = 0x4000; // Use write-only instruction to set TSS b
it = 0
// Step 5. User specific code, enable interrupts:

EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO12 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO13 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO14 = 1;
EDIS;
// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
// which is connected to CPU-Timer 1, and CPU int 14, which is connected
// to CPU-Timer 2:
IER |= M_INT1;
IER |= M_INT13;
//
IER |= M_INT14;
// Enable TINT0 in the PIE: Group 1 interrupt 7
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
// Step 6. IDLE loop. Just sit and loop forever (optional):
while(1)
{
//
CpuTimer1.RegsAddr->TCR.bit.TSS = control;
// 1 = Stop timer, 0 =
Start/Restart
// Timer
}
}
__interrupt void cpu_timer0_isr(void)
{
CpuTimer0.InterruptCount++;
t1=30;
t2=50;
t0=20;
//
//
//
//

t1X=t1*0.5;
t2X=t2*0.5;
t0X=t0*0.25;
t0X2=t0*0.5;
t0X = (long) (100 * t0 * 0.24);
t0X2 = (long) (100 * t0 * 0.5);
t1X = (long) (100 * t1 * 0.5);
t2X = (long) (100 * t2 * 0.5);

CpuTimer1.RegsAddr->PRD.all = (t0X - 1); // Counter decrements PR


D+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Disable/ 1 = Enable
Timer
// Interrup

GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=0;
// Acknowledge this interrupt to receive more interrupts from group 1
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
__interrupt void cpu_timer1_isr(void)
{
CpuTimer1.InterruptCount++;
// switch (control) {
// case 1 :
if (control ==1)
{
if (conteo ==0)
{
CpuTimer1.RegsAddr->PRD.all = (t1X - 1); // Counter decremen
ts PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = reload time
r
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Disable/ 1
= Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=1;
}
else if (conteo ==1)
{
CpuTimer1.RegsAddr->PRD.all = (t2X - 1); // Counter decreme
nts PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = reload
timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Disabl
e/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=2;
}
else if (conteo ==2)
{

CpuTimer1.RegsAddr->PRD.all = (t0X2 - 1); // Counter decrem


ents PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = reload
timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Disabl
e/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=3;
}
else if (conteo ==3)
{
CpuTimer1.RegsAddr->PRD.all = (t2X - 1); // Counter decreme
nts PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = reload
timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Disabl
e/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=4;
}
else if (conteo ==4)
{
CpuTimer1.RegsAddr->PRD.all = (t1X - 1); // Counter decreme
nts PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = reload
timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Disabl
e/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=5;
}
else
{
CpuTimer1.RegsAddr->PRD.all = (t0X - 1); // Counter decrements
PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Disable/ 1 = E
nable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;

//

conteo=0;
}

//
break;
}
else if (control ==2)
// case 2 :
{
if (conteo ==0)
{
CpuTimer1.RegsAddr->PRD.all = (t1X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = rel
oad timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Dis
able/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=1;
}
else if (conteo ==1)
{
CpuTimer1.RegsAddr->PRD.all = (t2X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=2;
}
else if (conteo ==2)
{
CpuTimer1.RegsAddr->PRD.all = (t0X2 - 1); // Counte
r decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=3;
}

else if (conteo ==3)


{
CpuTimer1.RegsAddr->PRD.all = (t2X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=4;
}
else if (conteo ==4)
{
CpuTimer1.RegsAddr->PRD.all = (t1X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=5;
}
else
{
CpuTimer1.RegsAddr->PRD.all = (t0X - 1); // Counter dec
rements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = reloa
d timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Disabl
e/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
//

conteo=0;
}

//
break;
}
//
// case 3 :
else if (control ==3)
{
if (conteo ==0)
{
CpuTimer1.RegsAddr->PRD.all = (t1X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = rel

oad timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;

// 0 = Dis

able/ 1 = Enable Timer


GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=1;
}
else if (conteo ==1)
{
CpuTimer1.RegsAddr->PRD.all = (t2X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=2;
}
else if (conteo ==2)
{
CpuTimer1.RegsAddr->PRD.all = (t0X2 - 1); // Counte
r decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=3;
}
else if (conteo ==3)
{
CpuTimer1.RegsAddr->PRD.all = (t2X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;

GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=4;
}
else if (conteo ==4)
{
CpuTimer1.RegsAddr->PRD.all = (t1X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=5;
}
else
{
CpuTimer1.RegsAddr->PRD.all = (t0X - 1); // Counter dec
rements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = reloa
d timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Disabl
e/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
//

conteo=0;
}

//
}

break;

else if (control ==4)


{
//
// case 4 :
if (conteo ==0)
{
CpuTimer1.RegsAddr->PRD.all = (t1X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = rel
oad timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Dis
able/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=1;

}
else if (conteo ==1)
{
CpuTimer1.RegsAddr->PRD.all = (t2X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=2;
}
else if (conteo ==2)
{
CpuTimer1.RegsAddr->PRD.all = (t0X2 - 1); // Counte
r decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=3;
}
else if (conteo ==3)
{
CpuTimer1.RegsAddr->PRD.all = (t2X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=4;
}
else if (conteo ==4)
{
CpuTimer1.RegsAddr->PRD.all = (t1X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1

= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;

// 0

= Disable/ 1 = Enable Timer


GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=5;
}
else
{
CpuTimer1.RegsAddr->PRD.all = (t0X - 1); // Counter dec
rements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = reloa
d timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Disabl
e/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
//

conteo=0;
}

//
break;
}
else if (control == 5)
//
// case 5 :
{
if (conteo ==0)
{
CpuTimer1.RegsAddr->PRD.all = (t1X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = rel
oad timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Dis
able/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=1;
}
else if (conteo ==1)
{
CpuTimer1.RegsAddr->PRD.all = (t2X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer

GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=2;
}
else if (conteo ==2)
{
CpuTimer1.RegsAddr->PRD.all = (t0X2 - 1); // Counte
r decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=3;
}
else if (conteo ==3)
{
CpuTimer1.RegsAddr->PRD.all = (t2X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=4;
}
else if (conteo ==4)
{
CpuTimer1.RegsAddr->PRD.all = (t1X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=5;
}
else
{

CpuTimer1.RegsAddr->PRD.all = (t0X - 1); // Counter dec


rements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = reloa
d timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Disabl
e/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=0;
}
}
//
break;
else
{
// default :
if (conteo ==0)
{
CpuTimer1.RegsAddr->PRD.all = (t1X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = rel
oad timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Dis
able/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=1;
}
else if (conteo ==1)
{
CpuTimer1.RegsAddr->PRD.all = (t2X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=2;
}
else if (conteo ==2)
{
CpuTimer1.RegsAddr->PRD.all = (t0X2 - 1); // Counte
r decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1

= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;

// 0

= Disable/ 1 = Enable Timer


GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPASET.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=3;
}
else if (conteo ==3)
{
CpuTimer1.RegsAddr->PRD.all = (t2X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPASET.bit.GPIO14 = 1;
conteo=4;
}
else if (conteo ==4)
{
CpuTimer1.RegsAddr->PRD.all = (t1X - 1); // Counter
decrements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1
= reload timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0
= Disable/ 1 = Enable Timer
GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
conteo=5;
}
else
{
CpuTimer1.RegsAddr->PRD.all = (t0X - 1); // Counter dec
rements PRD+1 times each period
CpuTimer1.RegsAddr->TCR.bit.TRB = 1;
// 1 = reloa
d timer
CpuTimer1.RegsAddr->TCR.bit.TIE = 1;
// 0 = Disabl
e/ 1 = Enable Timer
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;
//

conteo=0;
}

//

break;
}

}
//__interrupt void cpu_timer2_isr(void)
//{
// CpuTimer2.InterruptCount++;
// // The CPU acknowledges the interrupt.
//
//}
//===========================================================================
// No more.
//===========================================================================