Analysis

================================================================================
===========================================
all_connected
reports the list of all connected
objects of the specified object
check_design
reports information on design sta
te
clock_ports
finds clock ports of the design
fanin

traces fanin from a pin or port

fanout

traces fanout from a pin or port

report

generates one of various reports

validate_timing
tem timing report

generates an Encounter Timing Sys

ChipWare
================================================================================
===========================================
cwd
creates various HDL objects for C
hipWare developer
hdl_create
creates various HDL objects for C
hipWare developer
Constraint
================================================================================
===========================================
clock_uncertainty
specifies the uncertainty on the
clock network
create_mode
create a new constraint mode
define_clock
m
define_cost_group
imization
derive_environment
tance
external_delay
he design
multi_cycle
ction
path_adjust
ng analysis
path_delay
ng analysis
path_disable
ain paths
path_group
roup
specify_paths
or a timing exception or a report

defines and apply a clock wavefor

defines a new goal for timing opt
derives the environment of an ins
specifies delay that is outside t
overrides default clock edge sele
adjusts path constraints for timi
constrains certain paths for timi
disables timing analysis for cert
assigns certain paths to a cost g
describes a set of timing paths f

Customization
================================================================================
===========================================
add_command_help
adds a help string for a new comm
and
define_attribute
defines a new attribute

mesg_make
archive

generates new messages in message

mesg_send
message archive
parse_options
re

sends out generated message from

parses arguments to a tcl procedu

Design Explorer
================================================================================
===========================================
dex_create_exploration_scenarios
creates the exploration scenarios
for the specified design
dex_define_exploration_power_domain
creates an exploration power doma
in
dex_execute_exploration_scenarios
execute the different scenarios
dex_report
s)
dex_write_scenario
CPF file for the specified scenario

print the design explorer report(

generates a basic run script and

Design Manipulation
================================================================================
===========================================
change_link
changes the reference of a instan
ce with a new design or subdesign or
libcell.
change_names

change names of select objects

delete_unloaded_undriven
from the design
edit_netlist

deletes unused ports and subports

insert_tiehilo_cells
with tie-cells
mv

replaces constants 1'b0 and 1'b1

remove_assigns_without_optimization
uffers
reset_design

replaces assign statements with b

rm

removes an object

ungroup

ungroups one or more instances.

edits a gate-level design

renames a design object

resets a design

Design for Test

================================================================================
===========================================
add_opcg_hold_mux
replaces a single scan flop by op
cg equivalent flop
analyze_scan_compressibility
performs a scan-based compressibi
lity analysis of the design and produces
actual compression results for ea
ch compression setting
analyze_testability
performs ATPG analysis of the des
ign in either assume or fullscan mode

check_atpg_rules
iles to check if a design is ATPG ready
check_dft_pad_configuration
tion control of the pad logic for the

generates Encounter Test script f

checks and reports the data direc
test I/O ports

check_dft_rules

checks for DFT rule violations

check_mbist_rules

checks for MBIST rule violations

compress_scan_chains
tual (existing) scan chains
concat_scan_chains
or a specific test mode of operation
configure_pad_dft
put mode for DFT
connect_opcg_segments
ins
connect_scan_chains
nts which pass DFT rules into scan chains
define_dft

inserts compression logic into ac

dft_trace_back
pin
fix_dft_violations

trace back one level from a given

fix_scan_path_inversions

fixes inversions in the scan path

concatenates actual scan chains f

configures pads into input or out
connects OPCG logic into scan cha
connects scan registers and segme
defines a DFT object

fixes DFT rule violations

identify_multibit_cell_abstract_scan_segments identifies abstract_segments for

multibit scan cells
identify_shift_register_scan_segments
identifies functional shift-regis
ter(s) in the design and defines those as
scan segment(s)
identify_test_mode_registers
in the design, and auto-asserts them as

identifies fixed value registers

internal test mode signals.

insert_dft

inserts a DFT object

read_dft_abstract_model
for top-level scan chain stitching
read_io_speclist
dary scan insertion
replace_opcg_scan
ps by their opcg equivalent flops
replace_scan
s DFT rules by their scan equivalent flops
reset_opcg_equivalent
pcg-equivalency table which was

reads in abstraction models used

reads an IOSpecList file for boun
replaces domain blocking scan flo
replaces non-scan flops which pas
removes the scan cells from the o
previously defined using a (numbe

r of) set_opcg_equivalent commands

reset_scan_equivalent
brary cells from the scan-equivalency

removes the specified non-scan li

table which was previously define

d using a (number of) set_scan_equivalent

command(s)
set_compatible_test_clocks
clocks

define the set of compatible test

set_opcg_equivalent
is used during the conversion of a scan

controls the opcg cell type that

flip-flop by the 'replace_opcg_sc

an' command
set_scan_equivalent
type that is used during the conversion

controls the scan-equivalent cell

of a non-scan flip-flop which pas

ses the DFT rule checks to a scan flop

write_atpg
terface
write_bsdl
design
write_compression_macro
n macro
write_dft_abstract_model
ion of the actual scan chains
write_dft_rtl_model
in Verilog assuming DFT RTL insertion

describes scan chains for ATPG in

writes out BSDL information for a
writes the RTL for the compressio
writes an abstract model descript
writes an RTL model of the design
flow has been enabled and DFT ins

ertion commands supporting the RTL update

flow have been run
write_et
for Encounter Test ATPG and RRFA analysis

writes out data and script files

and BSV verification

write_et_atpg
for Encounter Test ATPG analysis
write_et_bsv
for Encounter Test BSV verification
write_et_dfa
for Encounter Test for DFA
write_et_mbist
for Encounter Test for MBIST
write_et_rrfa
for Encounter Test RRFA analysis
write_io_speclist
which describes the boundary scan

writes out data and script files

writes out data and script files
writes out data and script files
writes out data and script files
writes out data and script files
writes an IOSpecList output file
architecture of the design

write_mbist_testbench
es by executing the Encounter Test

generates mbist Verilog testbench

commands: build_model, create_emb

edded_test and write_vectors. If there

are ROMs in the design, ensure th
e rompath and romcontentsfile keywords
are passed to create_embedded_tes
t via the -create_embedded_test_options
keyword.
write_scandef
actual scan chains for physical

writes scandef information of the

reordering

GUI
================================================================================
===========================================
gui_hide
hide all windows

gui_hv_clear

remove file data in HDL viewer

gui_hv_get_file
DL viewer
gui_hv_load_file

return name of file loaded into H

gui_hv_set_indicators
L viewer
gui_info

set line and column numbers in HD

gui_legend

add a legend dialog

gui_pv_airline_add
s in physical viewer
gui_pv_airline_delete
wer
gui_pv_airline_display
er
gui_pv_airline_raw_add
in physical viewer
gui_pv_clear
wer
gui_pv_draw_box

add an airline between two object

gui_pv_draw_circle

draw a circle in physical viewer

gui_pv_draw_line

draw a line in physical viewer

gui_pv_draw_triangle
r
gui_pv_highlight
wer
gui_pv_highlight_update
al viewer
gui_pv_label

draw a triangle in physical viewe

gui_pv_redraw

redraw physical viewer contents

gui_pv_selection
list
gui_pv_snapshot
wer
gui_pv_zoom_box
viewer
gui_pv_zoom_fit
ewer
gui_pv_zoom_in
wer
gui_pv_zoom_out
ewer
gui_pv_zoom_to
ted objects in physical viewer
gui_raise

returns physical viewer selection

gui_reset

reset GUI busy indicators

gui_selection

return selection list

gui_show

show all windows

load a file into HDL viewer

set GUI persistent info message

delete an airline in physical vie

display airlines in physical view
add an airline between two points
clear selection from physical vie
draw a box in physical viewer

highlight objects in physical vie

update object highlight in physic
add a label to physical viewer

create a snapshot of physical vie

zoom to specified box in physical
perform 'zoom fit' in physical vi
perform 'zoom in' in physical vie
perform 'zoom out' in physical vi
zoom to bounding box around selec
raise main window

gui_status

set GUI status message

gui_sv_clear
and highlight
gui_sv_cone
matic viewer
gui_sv_get_instance
d in schematic
gui_sv_grey
ode
gui_sv_highlight
ewer
gui_sv_load
esign in schematic viewer
gui_sv_snapshot
ic viewer
gui_update
viewers with current design database

clear schematic viewer selection

load an instance into a cone sche
returns current instance displaye
configure schematic viewer grey m
highlight objects in schematic vi
load a hierarchical instance or d
create a snapshot of main schemat
force synchronization of primary

General
================================================================================
===========================================
?
alias for 'help' command
all_inputs

returns all the input ports.

all_outputs

returns all the output ports.

apropos
and commands
clear

search for strings in attributes

date

print date

enable_transparent_latches
rent latches
exit

disable En to D paths for transpa

get_attribute
n object
help
nd
include

returns an attribute value from a

lcd
y to the specified directory
license
k-out
lls
ed UNIX directory
lpopd
k and cd to it
lpushd
stack and cd to new directory
lpwd
y
man
cified command, attribute, or message
more
d

changes the UNIX working director

clear terminal window

exit this program

provides help for specified comma

reads in a command file

manages license check-in and chec

lists the contents of the specifi
remove top of UNIX directory stac
push current UNIX directory onto
returns the UNIX working director
returns information about the spe
emulates UNIX shell 'more' comman

quit

exits this program

redirect
iable temporarily
reset_attribute
t value
sdc_shell
ands can be used without the dc:: prefix

redirects stdout to a file or var

resets an attribute to its defaul
opens the SDC shell. All SDC comm
inside the SDC shell

set_attribute
s
shell
m within the tool
suppress_messages
ssages.
suspend
ourced script
timestat
ed up to this stage
unsuppress_messages
were disabled by the suppress_messages

sets an attribute value on object

executes a UNIX shell command fro
disables printing of specified me
brings up a Tcl prompt within a s
reports the runtime and memory us
enables printing of messages that
command.

Input and Output

================================================================================
===========================================
check_cpf
checks the validity of the CPF ru
les against the design
compare_sdc
checks the impact of updating the
SDC constraints with respect to the
known golden sets to validate the
correctness of the revised SDC file
decrypt
decrypts a Tcl file generated wit
h the 'encrypt' command
encrypt
encrypts a Tcl or HDL design file
exec_embedded_script
d in given design or subdesign. To

execute the embedded scripts foun

execute the scripts on all top-de

signs and their subdesigns, run

'exec_embedded_script' without an
y arguments.
export_critical_endpoints
comparing RC and Encounter endpoint

generates a 'path_adjust' file by

timing reports.

generate_constraints
pecified in the SDC file and generates

verifies the design constraints s

any missing functional false path

s or multi-cycle paths
get_read_files
have been read
propagate_constraints
constraints to top level and integrates

returns information on files that

propagates the block level design
them to generate an SDC at chip l

evel
read_dfm

reads in yield coefficient file

read_hdl

reads in Verilog or VHDL files

read_netlist
Verilog(v1995) files
read_sdc
C format
validate_constraints
specified in the SDC file, against RTL or

reads (and elaborates) Structural

reads in design constraints in SD
validates the design constraints
netlist

verify_power_structure
lls in the design conform to the CPF file
write_design

verifies whether the low power ce

write_do_ccd

writes out a CCD command file

write_do_clp
Low Power Extended Checks
write_do_lec

generates a dofile for Conformal

write_do_verify
Verify
write_ett
s in ETT format
write_hdl
n in Verilog
write_script
tools native format
write_sdc
SDC format
write_sdf
a Standard Delay Format (SDF) file
write_set_load
nets
write_template
for running the tool with the necessary

writes out a dofile for Conformal

generates design snapshot

writes out an LEC command file

writes out test design constraint

writes out a design or a subdesig
writes design constraints in the
writes out design constraints in
writes out delay information into
generates set_load values for all
writes out a template script file
commands and attributes

Low Power
================================================================================
===========================================
build_rtl_power_models
builds detailed power models for
more accurate RTL power analysis. The
models are used in subsequent RTL
power analysis reports.
check_library
allows you to check specific info
rmation in the loaded libraries with
regard to level shifters, isolat
ion cells, and state retention cells. The
report also lists the unusable ce
lls.
clock_gating
performs a clock_gating command
commit_cpf
er logic based on CPF rules
read_cpf

inserts isolation and level shift

read_saif
SAIF format

reads in switching activities in

reads in CPF files

read_tcf
TCF format
read_vcd
file for power analysis
reload_cpf
ead in earlier to newly added design

reads in switching activities in

reads in Value Change Dump (VCD)
re-applies rules from CPF files r
objects

remove_inserted_sync_enable_logic
us enable logic of flops inserted by

removes timing critical synchrono

tools through sequential analysis

of RTL
state_retention
d
write_forward_saif
IF file
write_saif
n SAIF format
write_tcf
n TCF format

performs a state_retention comman

writes out the library forward SA
writes out switching activities i
writes out switching activities i

Multiple Supply Voltage

================================================================================
===========================================
create_library_domain
creates a new library domain
isolation_cell

performs isolation cell insertion

level_shifter

performs a level shifter command

Navigation
================================================================================
===========================================
basename
removes leading directory names a
nd returns the object name
cd
sets position in object hierarchy
dirname
ns the directory name
dirs

removes the object name and retur

filter
e value
find

filters objects based on attribut

inout_mate
t object
ls

returns the other half of an inou

popd
d cd to it
pushd
cd to new dir
pwd
t hierarchy
vdir_lsearch
t in a list of objects
what_is

removes top of directory stack an

lists directory stack

finds an object by type and name

browses an object or directory

pushes current dir onto stack and

returns current position in objec
does lsearch of a vdir type objec
returns an object's type

what_is_list

returns an object's type

Physical
================================================================================
===========================================
create_placement_blockage
create a placement blockage
create_placement_halo_blockage

create a placement halo blockage

create_routing_blockage

create a routing blockage

create_routing_halo_blockage

create a routing halo blockage

generate_reports
ny stage in the flow. Statistics include

generates the QoS statistics at a

Timing, Area, Instance count, Uti

lization, Congestion and Power details.

This command is followed by summa
ry_table command to generate a summary
table for these QoS statistics.
move_instance
e
move_port

change the location of an instanc

predict_qos

predicts design QoS

read_def

reads in a DEF file

read_encounter

read in Encounter data files

read_spef
at
restore_congestion_map

reads the parasitics in SPEF form

restore_design
into RC
save_congestion_map

loads an encounter saved database

specify_floorplan

specify design floorplan

summary_table
ng various QoS numbers for various stages

generates a summary table includi

change the location of a port

restore congestion map data

save congestion map data

in RC flow. This command has to b

e preceded with generate_report command,
which creates the QoS statistics
to be used by this command.
update_congestion_map

update congestion map data

update_gcell_congestion

update gcell congestion values

update_gcell_pin_density

update gcell pin density values

update_gcell_utilization

update gcell utilization values

write_def

exports floorplan in DEF format

write_encounter

write out Encounter data files

write_spef
mat

writes the parasitics in SPEF for

Synthesis
================================================================================
===========================================
elaborate
elaborates previously read HDL fi
les and creates corresponding design and
subdesigns
retime

retimes the design

set_remove_assign_options
atements during synthesis
synthesize

controls replacement of assign st

synthesizes the design