Beruflich Dokumente
Kultur Dokumente
S K AHEMED ALI
B V PAVAN KUMAR,
Department of ECE,
SASI Institute of Technology and
Engineering,
Tadepalligudem, Andhra Pradesh, India
Department of ECE,
SASI Institute of Technology and
Engineering,
Tadepalligudem, Andhra Pradesh, India
Department of ECE,
SASI Institute of Technology and
Engineering,
Tadepalligudem, Andhra Pradesh, India
Abstract
This paper proposes Carry Speculative Addition using
Modified Carry generators to reduce critical path delay
there by reducing area and power. This paper proposes
Modified Carry generators uses less number of gates. A
data latching circuit is modified to get continuous data
into circuit. In order to generate accurate results, the
CSPA using Modified Carry generators(CSPA-M) is
implemented with error detection and error recovery
circuits to construct a variable latency carry speculative
adder(VLCSPA-M).The complete proposed Carry
Speculative Addition using Modified Carry generators
architecture is implemented using Verilog HDL and the
design is simulated using ModelSim and Xilinx ISE 9.2i,
Spartan 3 family device XC3S5000 -4FG1156.In this
proposed architecture, the area is reduced by 10% and
delay is reduced by 15%.
Key words: full adder, error detection, error recovery,
speculation, critical path delay, variable latency.
I. INTODUCTION
In any digital system, adder is the most crucial
arithmetic circuit. For traditional adders, the critical path
delay and area over head are very high (log n), (n).
Increasingly huge data sets and the need for instant
response require the adder to be large and fast.
Traditional ripple carry adder (RCA) is not suitable for
large adders because of its low speed performance. To
reduce the critical path delay and power consumption,
approximate designs are used by sacrificing accuracy.
Approximation can increase performance or reduce
power consumption with a simplified or inaccurate
circuit where strict requirements are relaxed. In [5] an
accuracy-configurable approximate (ACA) adder for
which the accuracy of results is configurable during
runtime. Because of its configurability, the ACA adder
can adaptively operate in both approximate (inaccurate)
mode and accurate mode. The ACA adder achieves
approximately 30% power reduction than conventional
pipelined adder.
By adopting an emerging concept in VLSI
design, error tolerance (ET), a novel error tolerant adder
(ETA I, ETA II, ETA III, ETA IV) is proposed in [8],
[12], [15], [16]. ETAI is divided into an accurate part
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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 5, Issue 2, February 2016
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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 5, Issue 2, February 2016
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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 5, Issue 2, February 2016
DELAY(ns)
CSPA
CSPAM
15.877
13.878
16.230
13.899
16.515
13.940
16.733
14.061
V. CONCLUSION
In this paper, two types of carry generators are
used for input carry one and carry zero
.implementation of separate design, the carry out bit
of the adder is produced in only one gate delay
thereby decreasing the area over head. A data latching
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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 5, Issue 2, February 2016
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